Vidyalankar

S.E. Sem. III [CMPN]

Digital Logic Design and Application
Prelim Question Paper Solutions

1. (a) (i) (357.46)8

= (011101111.100110)2
grouping into 4bits and writing the HEX equivalent we have.
= (OEF.98)H = (EF.98)H
(ii) (656.25)8 = (6 × 82 + 5 × 8 + 6 × 8° + 2 × 8−1 + 5 × 8−2)
= (430.33)10
6 430 4
6 71 5 0.33 × 6 = 1.98
6 11 5 0.98 × 6 = 5.88
1 0.88 × 6 = 5.28
= (0.1551)6 0.28 × 6 = 1.68
= (1554)6
∴ (656.25)8 = (1554.1551)6
(iii) (123)4
Since base = 4 = 2 × (2)
we write the 2 bit binary equivalent of the each digit
∴ (123)4 = (011011)2
= (11011)2
(iv) (11011.101)2 = (1 × 24 + 1 × 23 + 0 × 22 + 1 × 2 + 1 × 20 + 1 × 2−1 + 0 × 2−2 + 1 × 2−3)
= (27.625)10

1. (b)
[
Y = ∑m (0, 1, 2, 4, 6, 9, 12, 14)
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
AB = 00, Y = ? AB = 01, Y = ? AB = 10, Y = ? AB = 11, Y = ?
C C C C
0 1 0 1 0 1 0 1
D D D D
0 1 1 0 1 1 0 0 0 0 1 1
1 1 0 1 0 0 1 1 0 1 0 0

Y=C+D Y=D Y = CD Y= D
(2) Vidyalankar : S.E. – DLDA

A B Y C D
0 0 C+D
0 1 D
1 0 CD
0
1 1 D
1
4:1
2 MUX Y
3

A B
1. (c) (i) AB + AB = (A + B) (AB)
R.H.S. = (A + B) (A + B)
= (A.A + AB + BA + B.B)
= (0 + AB + BA + 0) (∵ A.A = 0)
= AB + BA
= L.H.S.

(ii) A(B + C) + (AB + BC) + A(B + C)

= A(B + C) + (AB + BC) (∵ A + A = A)
= A(B + C) + AB . BC
= A(B + C) + (A + B). (B + C) (Demorgan’s Theorem)
= A(B + C) + A.B + A.C + B.B + B.C
= A(B + C) + A B + A C + B + BC ∵ B.B = B
= A(B + C) + A B + A C + B ∵ B + BC = B(1 + C) = B
= AB + AC + A B + B + A C
= AB + B + AC + A C
= A + B + AC + A C
= A + A C + B + AC
= A + C + B + AC
= A+ B+C
RHS = B(AC + 1) + C
B + C ≠ LHS
∴ cannot be proved.

1. (d) Full Adder using Half Adder :

• The full adder circuit can be constructed using two half adders as shown in fig.1 and the
detail circuit is shown in fig.2.

Fig.1
 Prelim Question Paper Solutions (3)

• A full adder can be implemented using two half adders and the OR gate as shown in fig.2

Fig.2

• Now let us prove that this circuit acts as a full adder.

Proof :
• Refer fig.2 and write the expression for sum output as,
S = (A ⊕ B) ⊕ Cin = A ⊕ B ⊕ Cin
This expression is same as that obtained for the full adder.
• Now write the expression for carry output C0 as
C0 = (A ⊕ B) Cin + AB
C0 = (AB + AB)Cin + AB
= ABCin + ABCin + AB
= ABCin + ABCin + AB(1 + Cin )
= ABCin + ABCin + AB + ABCin
= BCin (A + A) + ABCin + AB
= BCin + ABCin + AB
= BCin + ABCin + AB(1 + Cin )
= BCin + ABCin + AB + ABCin
= BCin + AB + ACin .(B + B)
∴ C0 = BCin + AB + ACin

• This expression is same that for a full adder. Thus we have proved that circuit shown in fig.2
really behaves like a full adder.

Applications of Full Adder :

• The full adder acts as the basic building block of the 4 bit/8 bit binary/BCD adder ICs such as
7483.

2. (a) (i) Let T be time to lift off

T = 1 ⇒ More than 10 minutes to lift off.
T = 0 ⇒ Less than 10 minutes to lift off.

Let PF be pressure in the fuel tank.

PF = 1 ⇒ Pressure in fuel tank is above the required minutes.
PF = 0 ⇒ Pressure in fuel tank is below the required minutes.

Let PO be pressure in the oxidizer tank.

PO = 1 ⇒ Pressure in Oxidiser tank is above the required minutes.
PO = 0 ⇒ Pressure in Oxidiser tank is below the required minutes.
(4) Vidyalankar : S.E. – DLDA

As per the data given, the truth table is constructed as follows :

Input Output
The k − Map is as drawn
T PF Po Y T
0 0 0 0 PF
0 0 1 0 Po 00 01 11 10
0 1 0 0 0 0 0 1 1
0 1 1 1 1 0 1 0 1
1 0 0 1
y = T.PO + T.PF + T.PF .PO
1 0 1 1
1 1 0 1
1 1 1 0
The realization is as follows :
T PO PF

T.PO

y = T.PO + T.PF + T.PF .PO

T.PF

T.PF PO

T PO PF
(ii) (1) Prime Implicant : The tabular method of simplification consists of two parts. The first is
to find by an exhaustive search all the terms that are candidate for inclusion in the
simplified function. These terms are called prime implicants.
(2) Input Variable : Binary logic deals with variables that take on two discrete values and
with operations that assume logical meaning. The two values the variables take may be
called by different names (e.g. true and false, yes and no, etc.) The variables that are
assigned to the input values are called as input variables.
(3) Min term : A min term is a product term that contains all of the input variables (each
literal no more than once) make up a Boolean expression.
(4) Max term : A max term is a sum term that contains all of the input variables that makes a
Boolean expression.
2. (b) (1) Arrays all minterms according to the number of 1's and group are form as one 1's, two 1's,
etc., as shown in table.
Group Minterm A B C D
1 4 0 1 0 0
8 1 0 0 0
2 5 0 1 0 1
9 1 0 0 1
12 1 1 0 1
3 11 1 0 1 1
13 1 1 0 1
4 15 1 1 1 1
Table (a)
(2) Combine the minterms into a group of two :
• Table shows the matched pairs of minterms in the adjacent groups of table (a) which
differ at only one location (bit position) with respect to each other. Place (
) mark on the
matched pairs in table (a).
 Prelim Question Paper Solutions (5)

• The bit position where the minterms differ are represented by dashes (−) in the new terms
written in front of matched pairs.
Group Minterm A B C D
1 4−12 − 1 0 0

8−12 1 − 0 0

2 5−13 − 1 0 1

9−11 1 0 − 1

8−13 1 − 0 1

12−13 1 1 0 −
3 11-15 1 − 1 1

13−15 1 1 − 1

Table (b)
(3) Combine the minterm pairs into groups of four (Quad) : Group the minterm pairs of table (b)
(adjacent groups) to form minterm quads as shown in table (c) and place a (
) mark on the
matched pairs in table (b).
Group Minterm A B C D
1 4−12−5−13 − 1 0 −
8−12−9−13 1 − 0 −
2 9−11−13−15 1 − − 1
9−13−11−15 1 − − 1
Table (c)
No further grouping is possible after this. So the process of grouping stops here.
(4) Collect all nonchecked terms : Collect all the nonchecked (non-tick marked) terms from
tables (a), (b) and (c), because they are the prime implicants (PI)
∴ y = AD + BC + AC + ABC
(5) Prepare the PI table and obtain the EPIs : The PI table is shown in table (d).
Decimal number Give Minterms
PI
corresponding to PI 4 5 8 9 11 12 13 15
ABC 12, 13 × ×
AD 9, 11, 13, 15 × × × ×
BC 4, 5, 12, 13 × × × ×
AC 8, 9, 12, 13 × × × ×
Table (d)
(6) In the PI table find the columns containing only 1 cross (×) and encircle those (×) marks. Put
(
) mark in front of the corresponding PIs.
These (
) marked prime implicants in table (d) are the essential prime implicants (EPIs).
Hence the simplified expression for F is
F (A, B, C, D) = BC + AD + AC

Logic Diagram :
Step 1 : A B C D

y
(6) Vidyalankar : S.E. – DLDA

Step 2 : Convert AND-OR-NOT into NAND-NAND logic

Replace every AND by NAND
every OR by a bubbled OR
every inverter by a NAND inverter to get the NAND-NAND logic
A B C D

Step 3 : Draw circuit using only NAND gates :

A B C D

3. (a) Given the logical expression A + BC + ABD + ABCD

K map can be drawn as follows :
AB AB AB AB AB
CD 00 01 11 10
CD 00 1 0 1 1

CD 01 1 0 1 1

CD 11 0 0 1 1

CD 10 0 0 1 1

Standard SOP can be written as

F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
+ ABCD + ABCD + ABCD … (i)

The simplified expression from the K-map is :

F = A + BC
Now, F = A + BC
 Prelim Question Paper Solutions (7)
A B C

F
C BC

From equation (i), the standard POS form is obtained as follows :

F = (A + B + C + D)
(A + B + C + D) ⋅ (A + B + C + D) ⋅ (A + B + C + D)
(A + B + C + D) ⋅ (A + B + C + D) ⋅ (A + B + C + D) ⋅ (A + B + C + D)
(A + B + C + D) ⋅ (A + B + C + D)

3. (b) RS Flip Flop :

Working
Case I : S = 0 and R = 0
When any one input of a NAND gate becomes 0, its output is forced to 1.
Here S = R = 0. Q and Q both will be forced to be equal to 1.
This is an indeterminate state and hence should be avoided.
This is also called as Race condition or forbidden condition.
Case II : S = 0 and R = l
Since S = 0, it forces Q to be 1. Hence both inputs to NAND gate 1 are 1.
Hence Q = 0.
Thus with S = 0 and R = 1 the outputs are
Q = 0 and Q = 1. This is the reset condition.
Case III : S = l, R=0
Since R = 0, Q is forced to 1. Hence both inputs to NAND-2 are 1.
Hence Q = 0
Thus with S = 1 and R = 0 the outputs are
Q = 1 and Q = 0. This is the set condition.
Case IV : S = 1, R = 1
Q n +1 = R ⋅ Q n and Q n + 1 = S ⋅ Qn
Using De−Morgan's Theorem
Q n +1 = R + Q n and Q n +1 = S + Q n
Substitute R = 0 and S = 0 to get
Q n +1 = 0 + Q n = Qn and Q n +1 = Q n + Q n
Thus there is no change in the outputs if S = R = 1.
(8) Vidyalankar : S.E. – DLDA

Clocked RS Flip-Flop :

The clocked RS flip-flop shown above. It is basically the S - R flip-flop using NAND gates with
an additional “clock” input. It is also called as level triggered SR-FF.
The outputs of simple RS flip-flop used to change instantly in response to any change made at the
input. But this doesn’t happen with the clocked S R flip-flop.
For this circuit, the change in output will take place if and only if the clock input is made active
i.e Clk=1.In short, this circuit will operate as an SR flip-flop if clock = 1 but there is no change in
the outputs if clock = 0.

Disadvantage of R-S flip-flop :

From the truth tables of the R-S flip-flop using NOR and NAND gates we conclude.
When S=0 and R = 0 or S = R = 1, the outputs Q and Q either don’t change (NC) or they are
indeterminate (invalid) due to race condition. This disadvantage of R-S latch can be overcome by
using the gated D latch.
Applications : The RS flip-flop is used in electronic timers.

Race Around Condition and its remedy using Master Slave JK :

 Prelim Question Paper Solutions (9)

When we consider the TOGGLE state we assume that the inputs do not change during the clock
pulse (CLK = 1), which is not true because of the feedback connections.
Now we have J = K= 1 and Q = 1 and after another time interval of ∆t the output will change
back to Q=0. Hence, we conclude that for the duration t of the clock pulse, the output will
oscillate back and forth between 0 and 1. At the end of the clock pulse, the value of Q is
uncertain. This situation is referred to as the race-around condition.

3. (c) J-K Flip flop :

Clk

Truth Table :
J K Qn Qn Qn + 1 Qn +1
0 0 0 1 0 1
1 0 1 0
0 1 0 1 0 1
1 0 0 1
1 0 0 1 1 0
1 0 1 1
1 1 0 1 1 0
1 0 0 1

Excitation :
Qn Qn + 1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0

4. (a) Shift Registers : An array of flip-flops is required to store binary information i.e., number of bits
in binary word. Thus one flip-flop is required for each bit. The combination of n flip flops can
therefore store n bit binary words. It is then called as a Register.

Registers find themselves in a variety of applications including microprocessors. In a

microprocessor (8085) there are seven 8 bit registers referred to as general purpose registers and
five one bit registers referred to as flags.

A shift register is a n bit register with a provision for shifting its stored data by one bit position at
each tick of the clock. This type of bit movement or shifting is essential for certain arithmetic and
logic operations used in microprocessors. According to the data movement in a register, they are
classified as shown in the block diagram.
(10) Vidyalankar : S.E. – DLDA
Serial Serial Serial
Input Register(s) Output Input Register(s)
MSB ……… LSB
Parallel Input
Parallel Output
MSB ……… LSB
Serial Parallel Input
Register(s) Output
………
Register(s)
………

Parallel in Serial out Shift Register : Parallel Output

D0 D1 D2 D3

Serial
Input

D0 Q0 D1 Q1 D2 Q2 D3 Q 3 Serial
Clk Clk Clk Clk Output

Clock
At each clock tick the register load from the data D3D2D1D0 or shifts the data depending on the
value of LOAD/SHIFT. Internally the device uses 2 input multiplexer on each flip flop to select
between the two cases.
When LOAD/SHIFT = 1,
The register loads a new data from the input D3D2D1D0
When LOAD/SHIFT = 0,
The register shifts the current contents by one bit position.
4. (b) (i)
Asynchronous Counter Synchronous Counter
1. In an Asynchronous Counter the output of In a Synchronous Counter all the Flip Flop’s
one Flip Flop acts as the clock Input of the are connected to a common clock signal.
next Flip Flop.
2. Speed is High. Speed is Low.
3. Only JK or T Flip Flop can be used to Synchronous Counter can be designed using
construct Asynchronous Counter. JK, RS, T and D Flip Flop.
4. Problem of Glitch arises. Problem of Lockout.
5. Only serial count either up or down is Random and serial counting is possible.
possible.
6. Settling time is more. Settling time is less.
7. Also called as serial counter. Also called as Parallel Counter.
8.
 Prelim Question Paper Solutions (11)

(ii)
Combinational Circuits Sequential Circuits
1. In combinational circuits the output depends In sequential circuits the output depends not
only on the present set of inputs at any only on the present set of inputs but also the
instant of time. previous output.
2. No concepts of memory are used. To store the previous output memory is used.
3. Outputs are lost when input signals are Output signals are retained till the next
removed. levels of inputs are applied.
4. e.g., MUX DEMUX, ENCODER, e.g., FLIP FLOPS, COUNTERS SHIFT
DECODER. REGISTERS.
5. Clock is not used in combinational Logic Clock is the main feature of sequential
Circuits Circuits.
6.
INPUTS OUTPUTS
Input Combinational
Logic
Combinational
Logic Circuit

Memory

4. (c) Lock out condition is an erroneous condition which generally occurs in synchronous counters. It
occurs when the counter enters an invalid count state from a valid state and tends to remain in the
invalid loop.
Consider the 3-bit counter which counts the following sequence:

0 1 3 4 5 7
Here the invalid states are 2, 6.
If the counter enters state 2 (invalid) the counter becomes unpredictable and may enter the loop
For eg.
2 6

This is known as Lock-out condition.

To avoid such conditions we use bushing.
In this method all the invalid states next state is given to some valid state so that the counter may
not enter in an invalid loop.
Considering the above eg. The counter can be designed as shown.
2 6

0 1 3 4 5 7

4. (d) f(A, B, C) = ∑ m(0, 2, 5, 7)

AB
C 00 01 11 10
0 1 1 0 0
1 0 0 1 1
F = A C + AC
= A⊕C
(12) Vidyalankar : S.E. – DLDA

5. (a) (i) Fanout :

This is the number of similar gates
which can be driven by a gate. High
i/ps fanout = 3
fanout is advantageous because it
reduces the need for additional drivers
to drive more gates.

(ii) Current and voltage parameters :

(a) High level input voltage VIH : This is the minimum input voltage which is recognized by the
gate as logic 1.
(b) Low level input voltage VIL : This is the maximum input voltage which is recognized by the
gate as logic 0.
(c) High level output voltage VOH : This is the minimum voltage available at the output
corresponding to logic 1.
(d) Low level output voltage VOL : This is the maximum voltage available at the output
corresponding to logic 0.
(e) Low level input current IIL : This is the minimum current which must be supplied by a driving
source corresponding to 0 level voltage.
(f) High level input current IIH : This is the minimum current which must be supplied by a
driving source corresponding to 1 level voltage.
(g) High level input current IOH : This is the maximum current which the gate can sink in 1 level.
(h) Low level output current IOL : This is the maximum current which the gate can sink in 0 level.

(iii) Propagation delay (or speed of operation) :

50 %
Input
tPHL tPLH
Output
50 %

The delay times are measured between the 50 % voltage levels of input and output waveforms.
There are two delay times
tPHL → when output goes from High to Low
tPLH → when output goes from Low to High
Propagation delay is average of above two delay times.

(iv) Noise immunity (or Noise margin) :

The input & output voltage levels defined above are shown in figure. Voltages
Stray electric and magnetic fields may induce
V0H
unwanted voltages, known as noise on the connecting 1 state noise
wires between logic circuits. This may cause the margin V0H − V1H
voltage at the input to a logic circuit to drop below V1H
V1H or rise above V1L and may produce undesired
operation. V 1L
0 state noise
V1L − V0L
The circuit’s ability to tolerate noise signals is referred margin
to as the noise immunity, a quantitative measure of V0L
which is called noise margin. 0
There are two types of noise margins.
(a) High level noise margin (NMH)
NMH = V0H − V1H
 Prelim Question Paper Solutions (13)

(b) Low level noise margin (NML)

NML = V1L − V0L

5. (b) (1) TTL to CMOS :

Here TTL is a driver circuit and CMOS is a load circuit. The two circuits are from different
families with different electrical characteristics. Therefore we must check that the driving
device can meet the current and voltage requirement of the load device or not.
For TTL output and CMOS input voltage and current parameters.
TTL CMOS
VOH (min) = 2.4 V VIH (min) = 3.5 V
VOL (max) = 0.4 V VIL (max) = 1.5 V
IOH = 400 µA IIH = 5 nA
IOL = 16 mA IIL = 5 nA
5V VCC = 5 V logic 1
logic 1 400 µA 5 nA
VOH = 2.4 V VIH = 3.5 V

Indeterminate Indeterminate
logic 0
VOL = 0.4 V VIL = 1.5 V
16 mA 5 nA logic 0
0V 0V
[TTL output current & voltage [CMOS input current & voltage
profile] profile]

TTL driving CMOS at logic 0 level :

When TTL is at logic 0 its VOL is acceptable for CMOS input i.e. VIL.
Because VOL (TTL) ≤ VIL (CMOS).
Similarly IOL (TTL) ≥ IIL (CMOS). So when TTL is interfaced with CMOS at logic 0 level
interfacing is not required.
TTL driving CMOS at logic 1 level :
From above table it shows that IOH (TTL) ≥ IIH (CMOS). So there is no problem of current.
But when we compare the TTL output voltage with CMOS input voltage requirement we find
that VOH (TTL) ≤ VIH (CMOS). So for this situation TTL output must be raised or increased
to an acceptable for CMOS. This can be done using following interfacing circuits.

(i) TTL driving CMOS with same power supply: (+5 V)

To get TTL output acceptable to CMOS
3.3 KΩ
at logic 1 is use pull up resistor between
TTL driver to CMOS load.
TTL driver CMOS load

When output of TTL low, the lower end of 3.3 KΩ is grounded. Therefore the TTL driver
sinks a current of
VCC 5V
Isink = = = 1.52 mA
R 3.3 K
Therefore there is no effect of 3.3 KΩ at low level of TTL.
When the TTL output is in the high state, means its output VOH = 2.4 V. Because of pull−up
resistor, output rises above 2.4 V, which forces the upper totem pole transistor (Q4) into
cutoff. The pull up action is now passive because the supply voltage pulling the output upto
+5V through pull-up resistor.
(14) Vidyalankar : S.E. – DLDA

The minimum resistance is determined by the maximum sink current of the TTL device
IOL (max) = 16 mA. In worst case, supply voltage may be high as 5.25 V. So minimum
resistance is
5.25 V
Rmin = = 328 ohms [std. 330 Ω]
16 mA
(ii) Different power supply:
(+5 V) (+12 V)
We know TTL works on supply voltage
from 4.75 V to 5.25 V. Similarly CMOS 6.8 KΩ
works on 3 to 15 V. So if different supplies
are present then net interfacing will be
following way.
TTL driver CMOS load

When TTL output is low, we can visualize a ground on the lower end of the pull up resistor.
Therefore TTL device has to sink current approximately.
12
Isink = = 1.76 mA
6.8 K
Similarly when TTL output is high, the output rises passively to +12 V. In other case the TTL
output is compatible with the CMOS input.
Rmin value we can take upto
12
Rmin = ≈ 750 Ω
16 mA

(iii) Level shifter IC 40104 :

To interface from TTL to CMOS, (+12 V)
(+5 V)
second alternative is to use level
translator circuit such as 40104. Level shifter
This is the CMOS chip that is (40104)
designed to take a low voltage input CMOS load
TTL driver
and translate into high voltage
output for CMOS.

(2) Interface of CMOS to TTL :

For CMOS to TTL interfacing CMOS is the driver and TTL is the load. Output
characteristics, input voltage and current parameter of TTL should be compatible with input
characteristics of CMOS.
CMOS TTL
VOH = 4.5 V V1H = 2 V
VOL = 0.5 V V1L = 0.8 V
IOH = 0.36 mA I1H = 40 µA
IOL = 0.4 mA I1L = 1.6 mA

CMOS TTL
5V VCC = 5 V logic 1
logic 1 0.36 mA 40 µA
VOH = 4.5 V VIH = 2 V

Indeterminate Indeterminate
logic 0
VOL = 0.5 V VIL = 0.8 V
0.4 mA 1.6 mA logic 0
0V 0V
 Prelim Question Paper Solutions (15)

CMOS driving TTL in the high state:

Above voltage parameter shows that CMOS output and VOH (CMOS) can supply enough voltage
to satisfy the TTL input requirement i.e. (V1H) on TTL in the high state. The parameters also
shows that CMOS output can supply more than enough current IOH (CMOS) to meet the TTL
input current requirement I1H (TTL). Thus no special consideration is required for CMOS
driving TTL in the high state.
CMOS driving TTL in low state :
The above voltage parameter shows that CMOS output voltage (VOL) satisfies TTL input
requirement in the low state (V1L). However the current requirement in the low state are not
satisfied. i.e. the TTL input has relatively high input current in the low state (1.6 mA) &
CMOS output current at low state (0.4 mA) is not sufficient to drive TTL. So in such case
interface circuit is needed between CMOS and TTL device.
(a) For same power supply : +5 V +5 V +5 V
The buffer 4050 B is used as interfacing
circuit. It has an output current rating of
IOL (max) = 3 mA which satisfy the TTL
input current requirement. CMOS driver Buffer (4050 B) TTL load

(b) For different power supply :

If CMOS and TTL having different +12 V +5 V
power supplies use above
connection, then CMOS will be
compatible with TTL.

CMOS driver Buffer (4050 B) TTL load

(Either (1) or (2) is expected.)

5. (c)

Whenever a counter circuit is discussed it is assumed that outputs are reset. Whenever the power
is switched on, we cannot predict the output of Flip-Flop. Therefore a CLR terminal is normally
provided. The CLR terminal requires an external circuitry to force the output to go low. This is
called as the “POWER ON RESET” circuit.

In addition to the existing circuit one RC network with AND gate is used. When the power supply
is switched ON, Vcc will appear across RC network at time t0. Hence the capacitor starts
charging. The charging slope depends on RC time constant. When capacitor voltage (Voutput)
reaches to voltage Vth (Threshold Voltage), chip IC will consider it as HIGH logic. Therefore for
duration t1-t0 output of AND gate is ‘0’.Therefore the Flip Flop’s are cleared.
(16) Vidyalankar : S.E. – DLDA

5. (d) (i) D 4 D3 D 2 D1 = (1101)2

P1 = 0
P2 = 1
P3 = 0

D4 D3 D 2 P3 D1 P2 P1
∴ Hamming code =
(1 1 0 0 1 1 0) 2
= (1100110) 2

(ii) D 4 D3 D 2 D1 = (1001)2
P1 = 0; P2 = 0; P3 = 0

D4 D3 D 2 P3 D1 P2 P1
Hamming Code =
(1 0 0 1 1 0 0) 2
= (1001100) 2

6. (a) • The "Race Around Condition" that we are going to explain occurs when J = K = 1 i.e. when
the latch is in the toggle mode.
• Refer figure 1 which shows the waveforms for the various modes, when a rectangular
waveform is applied to the "Enable" input

Fig.1 : Waveforms for various modes of a JK latch.

Interval t0-t1 :
• During this interval J = 1, K = 0 and E = 0.
• Hence the latch is disabled and there is no change in Q.

Interval t1-t2 :
• During this interval J = 1, K = 0 and E = l.
• Hence this is a set condition and Q becomes 1.

Interval t2-t3 : Race Around

• At instant t2, J = K = 1 and E = 1 Hence the JK latch is in the toggle mode and Q becomes
low (0) and Q = l.
 Prelim Question Paper Solutions (17)

• These changed outputs get applied at the inputs of NAND gates 3 and 4 of the JK latch. Thus
the new inputs to Gates 3 and 4 are :
NAND-3 : J = 1, E = l, Q = 1
NAND-4 : K = 1, E = 1, Q = 0.
• Hence R' will become 0 and S' will become 1.
• Therefore after a time period corresponding to the propagation delay, the Q and Q outputs
will change to, Q = 1 and Q = 0.
• These changed outputs again get applied to the inputs of NAND-3 and 4 and the outputs will
toggle again.
• Thus as long as J = K = 1 and E = 1, the outputs will keep toggling indefinitely as shown in figure
1. This multiple toggling in the J-K latch is called as Race Around condition. It must be
avoided.

Interval t3-t4 :
• During this interval J = 0, K = 1 and E = 1. Hence it is the reset condition.
• So Q becomes zero.

Master Slave JK Flip-Flop :

• Figure 2 shows the master slave JK flip flop.
• It is a combination of a clocked JK latch and clocked SR latch.
• The clocked JK latch acts as the master and the clocked SR latch acts as the slave.
• Master is positive level triggered. But due to the presence of the inverter in the clock line, the
slave will respond to the negative level.
• Hence when the clock = 1 (positive level) the master is active and the slave is inactive.
Whereas when clock = 0 (low level) the slave is active and the master is inactive.

Fig.2 : Master Slave JK Flip Flip.

• Table 1 gives truth table of master slave JK flip flop.

Table 1 : Truth table of master slave JK flip flop.

Inputs Outputs
Case Remark
CLK J K Qn + 1 Q n +1
I × 0 0 Qn Qn No change
II (1) 0 0 Qn Qn No change
III (1) 0 1 0 1 Reset
IV (1) 1 0 1 0 Set
V (1) 1 1 Qn Qn Toggle
(18) Vidyalankar : S.E. – DLDA

Operation :
• We will discuss the operation of the master slave JK FF with reference to its truth table.
• We must always remember one important thing that in the positive half cycle of the clock, the
master is active and in the negative half cycle, the slave its active. This is shown in figure 3.

Fig.3

Case 1 : Clock = ×, J = K = 0
(i) For clock = 1, the master is active, slave inactive. As J = K = 0. Therefore, outputs of master i.e.
Q and Q1 will not change. Hence the S and R inputs to the slave will remain unchanged.
(ii) As soon as clock = 0, the slave becomes active and master is inactive. But since the S and
R inputs have not changed, the slave outputs will also remain unchanged.
∴ he outputs will not change if J = K = 0.

Case 2 :Clock = ,J=K=0

This condition has been already discussed in case 1.

Case 3 :Clock = , J = 0 and K = 1

• Clock = 1: Master active, slave inactive.
• Therefore, outputs of the master become Q1 = 0 and Q1 = 1. That means S = 0 and R= 1.
• Clock = 0: Slave active, master inactive.
• Even with the changed outputs Q = 0 and Q = 1 fed back to master, its outputs will Q1 =
0 and Q1 = 1. That means S = 0 and R = 1.
• Hence with clock = 0 and slave becoming active, the outputs of slave will remain Q = 0
and Q1 = 1.
• Thus we get a stable output from the Master slave.

Case 4 :Clock = , J = 1 and K = 0

• Clock = 1 : Master active, slave inactive.
∴ outputs of master become Q1 = 1 and Q1 = 0, i.e., S = 1, R = 0.
• Clock = 0 : Master inactive, slave active.
∴ outputs of slave become Q = 1 and Q = 0.
• Again if clock = 1 then it can be shown that the outputs of the slave are stabilized to Q =
1 and Q = 0.

Case 5 :Clock = , J = 1 and K = 1

• Clock = 1 : Master active, slave inactive.
∴ outputs of master will toggle. So S and R also will be inverted.
• Clock = 1 : Master inactive, slave active.
∴ outputs of the slave will toggle.
• These changed output are returned back to the master inputs.
• But since clock = 0, the master is still inactive. So it does not respond to these changed outputs.
• This avoids the multiple toggling which leads to the race around condition. Thus the
master slave flip flop will avoid the race around condition.
• The waveforms for the master slave flip flop are shown figure 4.
 Prelim Question Paper Solutions (19)

Fig.4 : Waveforms of master slave JK flip flop

Observations from the waveforms :

• We can make the following important observations from the waveforms of the master
slave JK FF.
• The slave always follows the master after a delay of half clock cycle period.
• The multiple toggling or the race around condition is successfully avoided.

6. (b) A gray number can be converted to binary step by step as follows.

Step I : MSB bit is kept as it is.
Step II : This bit is EX−ORed (added) with next bit from gray code.
Step III : The resulting bit in step II is EX−ORed with next bit from gray code.
Step IV : Step III is repeated till you reach LSB.

We will talk in terms of B3 B2 B1 B0 and G3 G2 G1 G0. Let’s say given gray code is G3 G2 G1 G0
(a) B3 (binary MSB) = G3 (MSB as it is)
(b) B3 bit should be EX−ORed with next of gray, means B3 ⊕ G2, this will give B2,
∴B2 = B3 ⊕ G2.
(c) Resulting bit in step II is B2, is EX−ORed with next bit from gray i.e. G1, i.e. B2 ⊕ G1. The
resulting bit is B1, B2 ⊕ G1 = B1.

(a) Step III Continued

∴B0 = B1 ⊕ G0.
Now we reached LSB so stop. The above procedure is graphically represented as follows.
(20) Vidyalankar : S.E. – DLDA

MSB LSB
Gray Code G3 G2 G1 G0

⊕ ⊕ ⊕
Binary Code B3 B2 B1 B0
(MSB) (LSB)

Let’s take one example to understand the same convert 0 1 0 1 gray to equivalent binary.
MSB LSB
Gray 0 1 0 1

⊕ ⊕ ⊕
Binary 0 1 1 0
MSB
B3 B2 B1 B0
B3 = G3 = 0.
B2 = B3 ⊕ G2 = 0 ⊕ 1 = 1
B1 = B2 ⊕ G1 = 1 ⊕ 0 = 1
B0 = B1 ⊕ G0 = 1 ⊕ 1 = 0
∴gray 0 1 0 1 ⇒ 0 1 1 0 binary.

Note : The same conversion you can perform by “Addition” method.

The code conversion from gray to binary is given in following table.

Gray Binary
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

Figure (a) shows 3-to-8 line decoder. Here, 3 inputs are decoded into eight outputs, each output
represent one of the minterms of the 3-input variables. The three inverters provide the
complement of the inputs and each one of the eight AND gates generate one of the minterms.
Enable input is provided to activate decoded output base on data inputs A, B and C. The table
shows the truth table for 3 to 8 decoder.
 Prelim Question Paper Solutions (21)

Table : Truth table for a 3-to-8 decoder.

Inputs Outputs
EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

Fig.: 3 : 8 line decoder.

7. (a) Multiplexer (Data Selector) :
• Multiplexer is a special type of combinational circuit. The block diagram of an n-to-1
multiplexer is shown in Figure 1(a) and its equivalent circuit is shown in Figure 1(b).
• As shown, there are n-data inputs, one output and m select inputs, with 2m = n.
• A multiplexer is a digital circuit which selects one of the n data inputs and routes it to the
output. The selection of one of the n inputs is done by the select inputs.
• To select n inputs we need m select lines such that 2m = n. Depending on the digital code applied at
the select inputs, one out of n data sources is selected and transmitted to the single output Y.
• E is called as a strobe or enable input which is useful for cascading. It is generally an active
low terminal, that means it will perform the required operation when it is low.
(22) Vidyalankar : S.E. – DLDA

• As shown in Figure 1(b) the multiplexer acts like a digitally controlled single pole, multiple way
switch. The output gets connected to only one of the n data inputs at given instant of time.
MUX

D0 D0
D1
D1
D2 n:1
Multiplexer Y (Output) D2 (Output)

Dn−1
E Dn−1
(Enable
input)
Sm−1 S1 S0 Sm−1 S0
Select inputs
(a) Block diagram of an n : 1 multiplexer (b) Equivalent circuit
Fig. 1
Necessity of Multiplexers:
• In most of the electronic systems, the digital data is available on more than one line. It is
necessary to route this data over a single line.
• Under such circumstances we require a circuit which selects one of the many inputs at a time.
• This circuit is nothing else but a multiplexer that has many inputs, one output and some select
inputs.
• Multiplexer improves the reliability of the digital system because it reduces the number of
external wired connections.

Advantages of Multiplexers:
1. It reduces the number of wires.
2. So it reduces the circuit complexity and cost.
3. We can implement many combinational circuits using MUX.
4. It simplifies the logic design.
5. It does not need the k maps and simplification.

Types of Multiplexers:
The types of multiplexer
1) 2: 1 multiplexer 2) 4: 1 multiplexer 3) 8: 1 multiplexer
4) 16: 1 multiplexer 5) 32: 1 multiplexer

Applications of a Multiplexer:
Some of the important applications of a multiplexer are as follows:
1. It is used as a data selector to select one out of many data inputs.
2. It is used for simplification of logic design.
3. In the data acquisition system.
4. In designing the combinational circuits.
5. In the D/A converters.
6. To minimize the number of connections.

Multiplexer Tree:
• The multiplexer having more number of inputs can be obtained by cascading two or more
multiplexers with less number of inputs.
• This is called as a multiplexer tree.
• This concept will be clear after solving the following examples.
 Prelim Question Paper Solutions (23)

Demultiplexer Principle :
• The block diagram of a demultiplexer or decoder is shown in Figure 2(a).
• It has only one input, “n” outputs, and “m” select inputs.
• A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and
distributes it over several outputs.
• At a time only one output line is selected by the select lines and the input is transmitted to the
selected output line.
• Hence a demultiplexer is equivalent to a single pole multiple way switch as shown in Figure 2(b).

Y0 Y0
Data Y1 Y1
Dn
input Y2 Data Y2
Demultiplexer Outputs input Outputs
Enable E
Yn−1 Yn−1

Sm−1 Sm−2 S0 Select inputs

Select inputs
(a) 1 : n demultiplexer Fig. 2 (b) Equivalent circuit
• The enable input will enable the demultiplexer.
• The relation between the n output lines and m select lines is as follows :
n = 2m
Types of Demultiplexers:
Similar to the multiplexers, the demultiplexers are classified as follows:
1. 1:2 demultiplexer 2. 1:4 demutliplexer
3. 1:8 demultiplexer 4. 1:16 demultiplexer
Demultiplexer Tree:
• Similar to multiplexer we can construct the demultiplexer with more number of lines using
demultiplexers having lower number lines.
• This is called as demultiplexer tree. It is also called as cascading of demultiplexers.
• This concept will be clear by solving the following examples.
Comparison of Multiplexer and Demultiplexer:

Table: Comparison of MUX and DEMUX.

Sr.
No. Parameter Multiplexer Demultiplexer
1. Type of logic circuit Combinational Combinational
2. Number of data inputs n l
3. Number of select inputs m m
4. Number of data output l n
5. Relation between input / n = 2m n = 2m
output lines and select lines
6. Operation principle Many to 1 or as data selector 1 to many or data distributor
7. Application • As a universal logic circuit. • We can implement some
We can implement any combinational circuit.
combinational circuit using a
MUX.
• In time division multiplexing • In TDM system at
at the sending end. receiving end.
(24) Vidyalankar : S.E. – DLDA

7. (b) ALU
Arithmetic Logic Unit (ALU) :
• ALU is a very widely used and popular combinational circuit.
• It is capable of performing the arithmetic as well as the logic operations.
• ALU is the heart of any microprocessor.
• Figure 1 shows the block diagram of ALU IC 74181, Table 1 gives the pin description and
Figure 2 gives its pin configuration.
• 74181 is a 24-pin IC dual in line (DTP) package.
• A (A0 − A3) and B (B0 − B3) are the two 4 bit variables.
Table 1: Pin description of 74181
Pin Name Description
A0 − A3 Operated inputs
B0 − B3 Operand inputs
S0 − S3 Function select inputs
M Mode control input
Cn Carry input (active low)
F0 − F3 Function output
A=B Comparator output (equality output)
G Carry generate output
P Carry propagate otput
Cn +4 Carry output (active low)

Fig. 1 : Block diagram of ALU IC 74181 Fig. 2 : Pin configuration of the ALU IC 74181
• It can perform a total of 16 arithmetic operations which includes addition, subtraction,
compare and double operations.
• It provides many logic operations such as AND, OR, NOR, NAND EX-OR, compare etc on
the two four bit variables.
• 74181 is a high speed 4 bit parallel ALU.
• It is controlled by four function select inputs S0 − S3. These lines can select 16 different
operations for one mode (arithmetic) and 16 another operations for the other mode (logic).
• M is the mode control input. It decides the mode of operation to be either arithmetic or logic.
M=0 For arithmetic operations
M =1 For logic operations
 Prelim Question Paper Solutions (25)

• G and P outputs are used when a number of 74181 circuits are to be used in cascade alongwith
74182, the look ahead carry generator circuit to make the arithmetic operations faster.
• When mode control input is high (M = 1), then the logic operations are performed on the
individual bits and all the internal carries are enabled.
• When mode control input is low (M = 0), the arithmetic operations are performed on the two
4-bit words and all the internal carriers are enabled.
• IC 74181 incorporates full internal carry lookahead. This enhances its speed of operation to a
great extent.
• It provides a ripple carry between the devices using the Cn+4 output. (see cascading of two
74181s).
• For exploiting the option of carry lookahead between the packages, we have to use the P
(carry propagate) and G (carry generate) outputs. This option should be used only when the
speed requirements are stringent.
• If low speed of operation is acceptable, the ripple carry operation using C n+4 and Cn should be
exercised.

A = B Output :
1. A = B output indicates the logical equality of the two operands. This output goes HIGH when
the unit is in the subtract mode and A = B.
2. This output also goes high when all the four “Function outputs” are HIGH.
3. It is possible to wire AND the A = B outputs when more than one 74181s are being used. The
wire ANDing becomes possible because A = B is an open collector output. This enables us to
compare words which are longer than 4-bits.

Function tables: (If the question is 10 marks, then mention the functional table in details)
• Table 2(a) shows the function table for IC 74181. It is valid for the active high operands and
active high outputs, and with C n = 1 i.e. no carry.

Table 2(a): Function table for IC 74181 with active high data and C n = 1 (no carry)
Function Select Inputs Active high data and Cn = 1
S3 S2 S1 S0 Logic operations (M = 1) Arithmetic operations (M = 0)
0 0 0 0 F = A (Inversion) F=A
0 0 0 1 F = A + B (NOR) F=A+B
0 0 1 0 F = A.B F=A+ B
0 0 1 1 F=0 F = minus 1 (2’s comp)
0 1 0 0 F = AB (NAND) F = A plus A B
0 1 0 1 F = B (Invert) F = (A + B)plus A B
0 1 1 0 F = A ⊕ B (EXOR) F = A minus B minus 1
0 1 1 1 F = AB F = A B minus 1
1 0 0 0 F = A+ B F = A plus AB
1 0 0 1 F = A ⊕ B (EXNOR) F = A plus B
1 0 1 0 F=B F = (A + B ) plus AB
1 0 1 1 F = AB (AND) F = AB minus 1
1 1 0 0 F = logic 1 F = A plus A*
1 1 0 1 F=A+ B F = (A + B) plus A
1 1 1 0 F = A + B (OR) F = (A + B ) plus A
1 1 1 1 F=A F = A Minus 1
Each bit is shifted to the next more significant position.
• The arithmetic operations listed in function Table 2(a), correspond to no carry input. They
will get modified if the carry input is present as shown in Table 2(b).
(26) Vidyalankar : S.E. – DLDA

• It is possible to use IC 74181 with either active high inputs or with active low inputs. With
active low inputs the device produces active low outputs and with active high inputs it
produces active high outputs.
• The function table for active low inputs and outputs has been given in Table 2(b).
Table 2(b) : Function table for IC 74181 with active low data and C n = 0 (with carry).
Function Select Inputs Active Low data and Cn = 0
S3 S2 S1 S0 Logic operations M = 0 Arithmetic operations M = 1
0 0 0 0 F = A (inversion) F = A minus 1
0 0 0 1 F = AB (NAND) F = AB minus 1
0 0 1 0 F = A+B F = A B minus 1
0 0 1 1 F=1 F = minus 1
0 0 1 1 F = A+B F = A plus (A + B )
0 1 0 1 F = B (inversion) F = AB plus (A + B )

7. (c) Asynchronous / Ripple Counters

Figure 1 shows 2-bit asynchronous counter using JK flip-flops. As shown in figure 1 the clock
signal is connected to the clock input of only first stage flip-flop. The clock input of the second
stage flip-flop is triggered by the QA output of the first stage. Because of the inherent
propagation delay time through a flip-flop, a transition of the input clock pulse and a transition of
the QA output of first stage can never occur at exactly the same time. Therefore, the two flip-
flops are never simultaneously triggered, which results in asynchronous counter operation.

Fig.1 : A two-bit asynchronous binary counter.

Figure 1(a) shows the timing diagram for two-bit asynchronous counter. It illustrates the changes
in the state of the flip-flop outputs in response to the clock.

Fig.1(a) : Timing diagram for the counter of Fig.1.

Synchronous Counters
When counter is clocked such that each flip-flop in the counter is triggered at the same time, the
counter is called as synchronous counter. Figure 2 shows two stage synchronous counter.

Fig.2 : A two-bit synchronous binary counter.

 Prelim Question Paper Solutions (27)

Here, clock signal is connected in parallel to clock inputs of both the flip-flops. But the QA
output of first stage is used to drive the J and K inputs of the second stage. Let us see the
operation of the circuit. Initially, we assume that the QA = QB = 0. When positive edge of the
first clock pulse is applied, flip flop A will toggle because JA = KA = 1, whereas flip-flop B output
will remain zero because JB = KB = 0. After first clock pulse QA = 1 and QB = 0. at negative
going edge of the second clock pulse both flip-flops will toggle because they both have a toggle
condition on their J and K inputs (JA = KA = JB = KB = 1). Thus after second clock pulse, QA = 0
and QB = 1. At negative going edge of the third clock pulse flip-flop A toggles making QA = 1,
but flip-flop B remains set i.e., QB = 1. Finally, at the leading edge of the fourth clock pulse both
flip-flop toggle as their JK inputs are at logic 1. This result QA = QB = 0 and counter recycled
back to its original state. The timing details of above operation is shown in figure 3.

CP

QA

QB

Fig.3: Timing diagram and state sequence for the 2-bit synchronous counter.

A 3-bit Synchronous Binary Counter

Figure 4 shows 3-bit synchronous binary counter and its timing diagram. The state sequence for
this counter is shown in Table 1.

Fig.4(a) : A three-bit synchronous binary counter.

Fig.4(b) : Timing diagram for 3-bit synchronous binary counter.

Table : State sequence for 3-bit binary counter.

CP QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
(28) Vidyalankar : S.E. – DLDA

Looking at figure 4(b), we can see that QA changes on each clock pulse as we progress from its
original state to its final state and then back to its original state. To produce this operation, flip-
flop A is held in the toggle mode by connecting J and K inputs to HIGH. Now let us see what
flip-flop B does. Flip-flop B toggles, when QA is 1. When QA is a 0, flip-flop B is in the no-
change mode and remains in its present state. We can notice that flip-flop C has to change its
state only when QB and QA both are at logic 1. This condition is detected by AND gate and
applied to the J and K inputs of flip-flop C. Whenever both QA and QB are HIGH, the output of
the AND gate makes the J and K inputs of flip-flop C HIGH, and flip-flop C toggles on the
following clock pulse. At all other times, the J and K inputs of flip-flop C are held LOW by the
AND gate output, and flip-flop does not change state.

III. Table : Comparison of Synchronous and Asynchronous Counters :

Sr.
Parameter Asynchronous counter Synchronous counter
No.
1. Circuit complexity Logic circuit is simple. With increase in number of
states, the logic circuit
becomes complicated.
2. Connection pattern Output of the preceding FF, is There is no connection
connected to clock of the next between output of preceding
FF. FF and CLK of next one.
3. Clock input All the FFs are not clocked All FFs receive clock signal
simultaneously. simultaneously.
4. Propagation delay P.D. = n × (td) where n is P.D. = (td)FF + (td)gate.
number of FFs and td is p.d. It is much shorter than that or
per FF. asynchronous counter.
5. Maximum frequency Low because of the long High due to shorter
of operation propagation delay. propagation delay.

7. (d) Octal to Binary Encoder :

• The octal to binary encoder has 8 − input lines and 3 − output lines. Corresponding to the
eight input octal numbers we get three bit binary output.
• Note that in encoders only one input will have a one value at any given time.
• Figure 1 shows the block diagram of octal to binary encoder and Table gives its truth table.

Table : Truth table of octal to binary encoder

Inputs Outputs
D0 D0 D1 D2 D3 D4 D5 D6 D7 B0 B1 B2
D1 1 0 0 0 0 0 0 0 0 0 0
D2 B0 0 1 0 0 0 0 0 0 0 0 1
D3 0 0 1 0 0 0 0 0 0 1 0
Inputs B1 Outputs 0 0 0 1 0 0 0 0 0 1 1
D4
D5 B2 0 0 0 0 1 0 0 0 1 0 0
D6 0 0 0 0 0 1 0 0 1 0 1
D7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Fig. 1: Block diagram of octal
to binary encoder

Logical expressions for the outputs :

Referring to the truth table we can write the logical expressions for the outputs as follows :
B0 = D4 + D5 + D6 + D7
B1 = D2 + D3 + D6 + D7
B2 = D1 + D3 + D5 + D7
 Prelim Question Paper Solutions (29)

Implementation using basic gates :

The octal to binary encoder using the basic gates is shown in Figure 2.
D0 D1 D2 D3 D4 D5 D6 D7

B0 = D4 + D5 + D6 + D7

B1 = D2 + D3 + D6 + D7

B2 = D1 + D3 + D5 + D7

Fig. 2: Octal to binary encoder

Encoder IC 74148 (Octal to Binary Encoder) :

• Pin configuration of IC 74148 is as shown in Figure 3. This is an 8 input priority encoder.
• All the inputs are active low inputs with a well defined priority associated with them.
• Input I7 has the highest priority and I0 has the lowest priority.
• This encoder has three output lines which provide the binary representation of the selected
input.

I4 1 16 VCC
Pins Description
I5 2 15 EO
I0 to I7 Active low inputs
I6 3 14 GS
A 0 to A 2 Ative low outputs
I7 4 13 I3
IC 74148 EI Enable Input
EI 5 12 I2
EO Enable Output
A2 6 11 I1
GS Group Singal
A1 7 10 I0

GND 8 9 A0

Fig.: Pin configuration of IC 74148

Description :
• I0 to I7 are the eight active low inputs.
• A 0 to A 2 are the three active low outputs.
• EI is the active low enable input terminal. If EI is at logic 1 then it will force all the output to
become high i.e. inactive. This feature can be used to allow some time for the new input data
to settle down.
• GS is the group signal output. It is used for indication that one of the inputs is low i.e. active.
• If all the inputs are inactive (high) the enable output (EQ) goes to logic 0.
(30) Vidyalankar : S.E. – DLDA

Truth table :
The truth table of IC 74148 is shown in Table.

Table : Truth table IC 74148 i.e. octal to binary encoder

Inputs Outputs
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X X X 0 0 0 0 0 1