Flip Flops Part2

11. Flip Flop Design Using VHDL

Synchronous sequential circuits usually events change on either the positive or negative edge of
a particular signal: the clock.
In VHDL, these events (positive and negative edges) are modelled in two possible ways. We can
use either a VHDL attribute or VHDL functions.

11.1 Using Attribute EVENT.

In VHDL the positive edge of a signal called Clk is described as

(clk’event and clk = ‘1’)
Whereas the negative edge of the same signal is described as
(clk’event and clk = ‘1’)

Notice the (tick) with Clk

11.2 Using VHDL function

For the same signal Clk, then
Positive edge is modelled as
rising_edge(Clk)
whereas the negative edge is modeled as
falling_edge(clk)

1
Example 1

Write the behavioral VHDL code of a D-FF described by the logic symbol of Figure 1.

D Q
D-FF

Clk Qn

Figure 1 Symbol of a negative edge-triggred D-FF

2
Example 2
Write the behavioral VHDL code to synthesize the JK-FF describes by the logic symbol of
Figure 2. We assume the CLR overrides PR.
PR

J Q
JK-FF
Clk
Qn
K

CLR

0..320 ns : Async CLEAR 2.6 µs .. end Toggle

380 .. 880 ns : Async SET
1.8 µs .. 2.2µs : Sync SET

3
Example 3
Write the behavioral VHDL code to synthesize the T-FF describes by the logic symbol of
Figure 3. We assume this time that PR overrides CLR. PR

T Q
T-FF
Clk
Qn

CLR

0..240 ns : Async SET 3.84 µs .. 4.08 µs: PR overrides CLR

240 .. 560 ns: Async CLEAR
560 ns .. 2.2 µs: Toggle
2.2 µs .. 3.4 µs: Hold

4
12. Timing consideration in edge-triggered devices

To insure proper operation of an edge-triggered device, the excitation inputs (D; J,K , T …)
should not change at the time the active edge occurs.

There are 2-time constraints:

Setup time
Hold time
Consider a positive-edge triggered D-FF
tsu thd

Clk

D Stable

D changing D changing

• Setup time (tsu) : The time interval that the D input signal must be stable at the input of
the FF prior to the active edge of the Clk signal
• Hold time (thd) : The time interval that the D signal must remain stable after the active
edge of the Clk signal.
Values of tsu and thd depend on the technology in which these devices are fabricated. Typical
values for CMOS technology are
tsu = 3 ns
thd = 2 ns