Chapter 11 ■ Combinatorial Logic: Putting It All Together on the FPGA

elsif ( rising_edge(CLOCK) ) then -- rising edge of clock happen

current_state <= next_state;
end if;
end process;

fsm_p2: process(ENABLE,current_state) -- Only execute when current_state or ENABLE changes

state
begin

case current_state is -- in this case statements, we define all of the possible transitions
between states
when S0 =>
if ( ENABLE = '1') then
next_state <= S1;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S1 =>
if ( ENABLE = '1') then
next_state <= S2;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S2 =>
if ( ENABLE = '1') then
next_state <= S3;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S3 =>
if ( ENABLE = '1') then
next_state <= S4;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S4 =>
if ( ENABLE = '1') then
next_state <= S5;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S5 =>
if ( ENABLE = '1') then
next_state <= S6;
else -- ENABLE = '0'
next_state <= current_state;
end if;

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when S6 =>
if ( ENABLE = '1') then
next_state <= S7;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S7 =>
if ( ENABLE = '1') then
next_state <= S8;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S8 =>
if ( ENABLE = '1') then
next_state <= S9;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S9 =>
if ( ENABLE = '1') then
next_state <= S10;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S10 =>

if ( ENABLE = '1') then
next_state <= S11;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S11 =>

if ( ENABLE = '1') then
next_state <= S12;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S12 =>

if ( ENABLE = '1') then
next_state <= S13;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S13 =>

if ( ENABLE = '1') then
next_state <= S14;

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Chapter 11 ■ Combinatorial Logic: Putting It All Together on the FPGA

else -- ENABLE = '0'

next_state <= current_state;
end if;

when S14 =>

if ( ENABLE = '1') then
next_state <= S15;
else -- ENABLE = '0'
next_state <= current_state;
end if;

when S15 =>

if ( ENABLE = '1') then
next_state <= S0;
else -- ENABLE = '0'
next_state <= current_state;
end if;

end case;
end process;

fsm_p3: process(current_state) -- this counter output ONLY depends on current_state

begin

case current_state is -- in this case statements, we define all of the possible transition
between states
when S0 => COUNTER <= "0000";
when S1 => COUNTER <= "0001";
when S2 => COUNTER <= "0010";
when S3 => COUNTER <= "0011";
when S4 => COUNTER <= "0100";
when S5 => COUNTER <= "0101";
when S6 => COUNTER <= "0110";
when S7 => COUNTER <= "0111";
when S8 => COUNTER <= "1000";
when S9 => COUNTER <= "1001";
when S10 => COUNTER <= "1010";
when S11 => COUNTER <= "1011";
when S12 => COUNTER <= "1100";
when S13 => COUNTER <= "1101";
when S14 => COUNTER <= "1110";
when S15 => COUNTER <= "1111";
end case;
end process;

end behavioral;

11.2.1 Using Altera Quartus to Understand the FSM

You can use the Altera Quartus tools to help you better understand the design. You'll need to compile the
code in Listing 11-1 in Altera Quartus and open the RTL viewer (Figure 11-3).

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Figure 11-3.  How to open the RTL viewer

The RTL viewer should look something like Figure 11-4. In the viewer, there are output combination
logic and finite state machine logic which is inside the "yellow" box. Double-clicking the “yellow” box will
open the state machine viewer (Figure 11-5). It shows all the states in the FSM and all the relationships
between the states.

Figure 11-4.  Quartus RTL view of 4-bit counter—FSM version

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Chapter 11 ■ Combinatorial Logic: Putting It All Together on the FPGA

Figure 11-5.  Quartus State Machine viewer

In here you may become rather excited and think that you can use FSM to solve all your digital
problems. Yes, you are 100% correct. You can solve all kinds of digital problems with FSM in the simulation
world. In the real world, however, we are all constrained by the hardware—FPGA (field-programmable gate
array). Everything depends on how many resource you can use for your design.
Let us show you the resource usage difference between the design in Chapter 10 and this chapter's 4-bit
up counter design. There is a compilation report after each compilation. In Chapter 1, we mentioned the
basic gate design block: logic element. You can find out how many logic elements are used by the compiled
design. Figure 11-6 is the compilation report for the FSM 4-bit adder. You can see that the total logic
elements is 17/8064 (<1 %). 17/8064 means that the 4-bit up counter with FSM uses 17 logic elements out of
8064. The FPGA (MAX10 10M08DAF484C8G) has a total of 8064. Figure 11-7 is the compilation report from
Chapter 10‘s 4-bit up counter design. It shows that the Chapter 10 version only used six logic elements. The
FSM version used nearly three times more logic than the normal up counter design.
If you have a design need to create more than 500 4-bit up counters in the FPGA, then you need to
use the Chapter 10 version; otherwise you will not have enough logic elements (500 x 17 = 8,500). There is
another benefit to using the Chapter 10 version, which is that the counter can run faster (assuming a faster
clock). In general, the smaller the design (i.e., the fewer logic elements used), the faster the clock it can use.
Please don’t use FSM to design a simple counter when working on a real design. It would be like using
the Titan (US supercomputer) or the Tianhe-2 (Chinese supercomputer) to do the elementary maths.
You can use VHDL to design a real counter that's far smaller, faster, and simpler (only a few lines of code
compared with two pages of code). If your design only has a linear sequence, you can use a simple up
counter to help you "count" the states.

■■Caution  Don't use FSMs to design a simple counter or linear design, even though an FSM can certainly do it.

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