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Microprocessor
Paper : Objective Questions for 8085 Microprocessor
1. In Synchronous data Transfer type both Transmitter and Receiver will operate in
b) H and L register
d) B and C register
3. In 8085 the MAR, or ….. register, latches the address from the program counter. A bit later
the MAR applies this address to the ……, where a read operations performed
4. In micro – processors like 8080 and the 8085, the …..cycle may have from one to live
machine cycle
a) micro – instruction
b) source program
c) instruction
d) fetch cycle
6. A —— is used to isolate a bit, it does this because that ANI sets all other bits to Zero
a) subroutine
b) flag
c) label
d) mask
7. Interaction between a CPU and a peripheral device that takes place during and imput
output operation is known as
a) handshaking
b) flagging
c) relocating
d) sub–routine
8. Addressing in which the instructions contains the address of the data to the operated on is
known as
a) immediate addressing
b) implied addressing
c) register addressing
d) direct addressing
a) 10, 5
b) 8,4
c) 7,5
d) 6,6
11. Serial input data of 8085 can be loaded into bit 7 of the accumulator by
b) executing RST1
c) using TRAP
a) vector location
b) SID
c) SOD
d) TRAP
13. TRAP is …..whereas RST 7.5, RST 6.5, RST 5.5 are….
b) maskable, maskable
14. micro processor with a 16 – bit address bus is used in a linear memory selection
configuration address bus lines are directly used as chip selects of memory chips with four
memory chips. The maximum addressable memory space is
a) 64K
b) 16 K
c) 8K
d) 4K
15. How many outputs are there in the output of a 10-bit D/A converter?
a) 1000
b) 1023
c) 1024
d) 1224
16. The stack is a specialized temporary …… access memory during ….. and ……
instructions
a) OF817H
b) OF818H
c) OF8OOH
d) OF801H
c) Bi – directional
d) mixed direction is when lines into micro processor and some other out of micro
processes.
29. The No. of input output ports can be accessed by direct method ——-
30. The No. of input output ports can be accessed by memory mapped method —— K
31. If instruction RST is written in a program the program will jump ——- location.
32. When TRAP interrupt is triggered program control is transferred to ——- location.
33. The RST 5.5 interrupt service routine start from ——– location.
b) It is used to provide for proper WAIT states when microprocessor is communicating with
slow peripheral device.
a) Direct
b) Indirect
c) Indexed
d) Immediate
a)bidirectional
b)unidirectional out of MP
c)unidirectional int MP
c)both a b
39. In the TRAP, RST 7.5, RST 6.5, RST 5.5, which is having top priority
a)TRAP
b)RST 7.5
c)RST 6.5
d)RST 5.5
a) 8
b)7
c)5
d)4
a)TRAP
b)INTR
c)RST 7.5
d)RST 6.5
a)0024 H
b)003C H
c)0034 H
d)002C H
(a) Rst7.5
b) Rst 6.5
c) TRAP
d) INTR
(a) ooooH
b) ooo8H
c) oo1oH
d)oo18H
(a) INTA
b)INTA
c) INTR
46. The maximum number of I\o devices can be interfaced with 8085 in the I\o mapped I\o
technique are
a) 128
b) 256
c) 64
d) 1024
47. The maximum number of I\o devices which can be interfaced in the memory mapped I\o
technique are
a) 256
b) 128
c) 65536
d) 32768
a) absolute decoding
b) linear decoding
c) partical decoding
49. The Instructions used for data transfer in I\o mapped I\O are
a) IN, OUT
c) STA add
a) 10
b)11
c) 12
d) 13