BAHIR DAR UNIVERSITY

INSTITUTE OF TECHNOLOGY

SCHOOL OF COMPUTING AND ELECTRICAL ENGINEERING

Analysis and Modeling of Cascaded Multilevel Inverter for

Transformerless Electric Railway Traction Drives
By
Henok Ayele Behabtu

Advisor
Dr. Mengesha Mamo

A Thesis submitted to the School of Computing and Electrical Engineering of Bahir Dar
University in partial Fulfillment of the Requirements for the Degree of Master of Science in
Power System Engineering.

January 2014,

Bahir Dar, Ethiopia

 Bahir Dar University

Institute of Technology

School of Computing and Electrical Engineering

Analysis and Modeling of Cascaded Multilevel Inverter for Transformerless

Electric Railway Traction Drives

By: Henok Ayele Behabtu

Approval by Board of Examiners

____________________________________ __________

Chair Person (School Director) Signature

____________________________________ __________

Thesis advisor Signature

____________________________________ __________

Internal Examiner Signature

____________________________________ _________

External Examiner Signature

DECLARATION
I hereby declare that this thesis is my original work and that it has not been presented and will not
be presented by me to any other university for similar or any other degree award. I have fully
cited and referenced all material and results that are not original to this work.

Henok Ayele Behabtu _____________

Signature

This is to certify that the above declaration made by the candidate is correct to the best of my
knowledge.

Dr. Mengesha Mamo _____________

Thesis advisor Signature
 Acknowledgement
First and foremost, I would like to express my deepest appreciation to my advisor, Dr. Mengesha
Mamo, for his support, all of his help and instructions during my study and research. Also, I
would like to thank my classmates and friends for their comments and instructions which gave
me a great strength to complete this thesis.

Finally, but most importantly, I would like to thank my beloved family members, who always
give me strong inspirations, moral supports, and helpful suggestions.

i
 Table of content

Contents page
Acknowledgement .......................................................................................................................i

List of table ................................................................................................................................. v

List of figure .............................................................................................................................. vi

List of Acronyms ......................................................................................................................vii

List of Symbols .......................................................................................................................... ix

Abstract ...................................................................................................................................... x

1.Introduction ............................................................................................................................. 1

1.1. Overview .......................................................................................................................... 1

1.2. Research Background ....................................................................................................... 2

1.2.1. Multilevel Inverter ..................................................................................................... 2

1.2.2. High-power medium-voltage drives classification ................................................ 5

1.2.3. Induction motor drives using multi-level inverter ....................................................... 7

1.3. Problem Description ......................................................................................................... 8

1.4. Objective .......................................................................................................................... 9

1.4.1. General Objective....................................................................................................... 9

1.4.2. Specific Objectives ..................................................................................................... 9

1.5. Significance of the Study .................................................................................................. 9

1.6. Scope of the Study ............................................................................................................ 9

1.7. Methodology .................................................................................................................. 10

1.8. Organization of the thesis ............................................................................................... 10

2.Literature review .................................................................................................................... 11

2.1. Multilevel Inverter .......................................................................................................... 11

2.2. Multilevel Modulation Techniques ................................................................................. 13

ii
3.Electric Traction .................................................................................................................... 15

3.1. Introduction .................................................................................................................... 15

3.2. Steam Engine Drive ........................................................................................................ 15

3.3. Diesel Engine Drives ...................................................................................................... 16

3.4. Electric Drive ................................................................................................................. 16

3.5. Railway Electric Traction Drive ...................................................................................... 17

3.5.1. Train Systems........................................................................................................... 17

3.5.2. Power Quality .......................................................................................................... 17

3.5.3. Input Voltage Source ................................................................................................ 19

3.6. Traction Motors .............................................................................................................. 20

3.7. Converters and Transformers in Traction Drive .............................................................. 21

3.8. Multilevel Voltage Source Inverter ................................................................................. 23

3.8.1. Diode-Clamped Multilevel Inverter .......................................................................... 24

3.8.2. Flying Capacitor Structure........................................................................................ 29

3.8.3. Cascaded Multilevel Inverter .................................................................................... 32

3.8.4. Comparison among Three Multilevel Inverters in Application Aspects ..................... 37

3.9. Control and Modulation Techniques of Multilevel Converters ........................................ 38

3.9.1. Classification of Modulation Strategies .................................................................... 39

3.9.2. Multilevel SPWM .................................................................................................... 40

3.9.3. Space Vector PWM Modulation ............................................................................... 41

3.9.4. Space Vector Control ............................................................................................... 42

3.9.5. Selective Harmonic Elimination ............................................................................... 42

4.Eleven Level Cascaded H-bridge Multilevel Inverter Modeling ............................................. 45

4.1. Cascaded H–bridge Multilevel Inverter ........................................................................... 45

4.2. Principle of Working of Eleven Level Inverter ................................................................ 47

iii
 4.3. Mathematical Model Equation of Eleven Level CHBMLI ............................................... 48

4.3.1. Switching States of Inverter and Expression of Output Voltage ................................ 48

4.3.2. Determination of Switching Angles .......................................................................... 51

4.3.3. The Newton-Raphson Method .................................................................................. 54

4.3.4. The Total Harmonic Distortion Calculation .............................................................. 56

4.4. Analysis of Switching Angles and Output THD of 11-Level CHBMLI by Newton-
Raphson Method ................................................................................................................... 57

5.Simulation and Result Discussion .......................................................................................... 66

5.1. Simulation of Three phase induction motor driven by 11 level CHBMLI ........................ 71

6. Conclusion and Future Work ................................................................................................. 75

6.1. Conclusion...................................................................................................................... 75

6.2. Future Work ................................................................................................................... 76

References ................................................................................................................................ 77

Appendices ............................................................................................................................... 81

Appendix A. ............................................................................................................................. 81

Appendix B. .............................................................................................................................. 81

iv
 List of table

Table 3.1: Switching states in one leg of the three-level diode clamped inverter ........................ 25
Table 3.2: Switching states of the five level inverter.................................................................. 26
Table 3.3: Comparison of power component requirements per phase leg among three ............... 38
Table 4.1: Output voltage levels and their switching states for eleven-level inverter .................. 48
Table 4.2: The number of eliminated harmonic components of SHEPWM technique. ............... 53
Table 4.3: content of matric , , and from MATLAB program by using the Newton‟s
method ...................................................................................................................................... 60
Table 4.4: The switching angles of 7-level cascaded inverter..................................................... 60
Table 4.5: The switching angles of 9-level cascaded inverter..................................................... 61
Table 4.6: The switching angles of 11-level inverter. ................................................................ 61
Table 4.7: Voltage THD of 7- level cascaded inverter ............................................................... 62
Table 4.8: Voltage THD of 9- level cascaded inverter ............................................................... 62
Table 4.9: Voltage THD of 11- level cascaded inverter ............................................................. 63

v
 List of figure

Fig 1.1: Classification of converters topologies for high-power drives .................................. 6

Fig 3.1: Schematic layout of an electric locomotive................................................................... 20
Fig 3.2: Schematic diagram of the drive system of induction motors used in railway traction
system. ...................................................................................................................................... 23
Fig 3.3: Topology of the diode-clamped inverter (a) three-level inverter, (b) five -level inverter25
Fig 3.4: FCMLI circuit topologies, (a) 3-level inverter (b) 5- level inverter ............................... 29
Fig 3.5: Single phase structures of Cascaded inverter (a) 3-level, (b) 5-level, (c) 7-level ........... 33
Fig 3.6: Power circuit of three phase cascaded H-bridge eleven level inverter using IGBT ........ 34
Fig 3.7: Output phase voltage waveform of an eleven level cascaded multilevel inverter ........... 35
Fig 3.8: Classification of multilevel modulation methods .......................................................... 40
Fig 3.9: Multi-carrier control (a) control signal and carrier signals; (b) output voltage ............... 40
Fig 3.10: Output waveform of virtual stage PWM control ......................................................... 43
Fig 3.11: Unipolar switching output waveform.......................................................................... 44
Fig 4.1: Power circuit of single phase cascaded eleven level inverter for traction drive.............. 46
Fig 4.2: Output voltage of single phase cascaded eleven-level inverter for traction drive ........... 46
Fig 4.3: Output voltage waveform of eleven-level inverter. ....................................................... 57
Fig 4.4: Voltage THD as function of the modulation index of 7-level cascaded H-bridge .......... 63
Fig 4.5: Voltage THD as function of the modulation index of 9-level cascaded H-bridge .......... 64
Fig 4.6: Voltage THD as function of the modulation index of 11-level cascaded H-bridge ........ 64
Figure 5.1: Simulation circuit for eleven level inverter using SHE PWM technique .................. 67
Fig 5.2: Pattern of gating signals ............................................................................................... 68
Fig 5.3: (a) Simulated phase voltage and (b) THD analysis for 11-level CMLI at m=1.00 ......... 69
Figure 5.4: (a) Simulated line voltage and (b) THD analysis for 11-level CMLI at m = 1.00..... 70
Fig 5.5: Rotor current of induction motor using an ideal ac source ............................................ 71
Fig 5.6: Stator current of induction motor using an ideal ac source ............................................ 71
Fig 5.7: Rotor speed of induction motor using of ideal ac source ............................................... 72
Fig 5.8: Rotor current in case of feeding with cascaded 11-level inverter .................................. 73
Fig 5.9: Stator current in case of feeding with cascaded 11-level inverter .................................. 73
Fig 5.10: Rotor speed in case of feeding with cascaded 11-level inverter ................................... 74

vi
 List of Acronyms

AC Alternating Current
ASD Adjustable Speed Drive
CHBMLI Cascaded H-bridge Multilevel Inverter

CMLI Cascaded Multilevel Inverter

CSI Current Source Inverter

DC Direct Current

DCMLI Diode Clamped Multilevel Inverter

DSP Digital Signal Processor

EMI Electromagnetic Interference

ER Electric Railway

FACTS Flexible Alternating Current Transmission System

FCMLI Flying Capacitor Multilevel Inverter

FFT Fast Fourier Transforms

GTO Gate Turn Off Thyristor

HV High Voltage

HVDC High Voltage Direct Current

IEEE International Electrical Electronic Engineers

IGBT Insolate Gate Bipolar Transistor

LCI Load-Commutated Inverter

MCB Main Circuit Breaker

vii
MLC Multilevel Converter

MW Mega Watt

NPC Neutral Point Clamping

PWM Pulse Width Modulation

SCR Silicon Controlled Rectifier

SDCS Separate DC Sources

SHE PWM Selective Harmonic Elimination Pulse Width Modulation

SPWM Sinusoidal Pulse Width Modulation

SVC Space-Vector Control

SVM Space-Vector Modulation

THD Total Harmonic Distortion

VAR Volt Ampere Reactive

VSI Voltage Source Inverter

VVVF Variable Voltage Variable Frequency

viii
 List of Symbols

C Capacitor

Amplitudes of the fundamental component, whose frequency is

Amplitudes of the harmonics at frequency

Phase Voltage

DC Voltage

, , Fourier Coefficients

Switching Angle

dv/dt Change in Voltage

m Number of output voltage level

Modulation Index

S Switch

V (ωt) Output Voltage

ix
 Abstract
Multilevel inverters have been attracting the attention of researchers both in the academia and the
industry in the recent decade for high-power and medium-voltage energy control. They can
synthesize switched waveforms with lower levels of harmonic distortion than an equivalently
rated two-level converter. In railway application, multilevel inverters can be directly supplied
from caternary voltage eliminating transformer on board the train, reducing deadweight of the
train and saving space on the train.
There are mainly three types of multilevel inverters; these are a) diode- clamped, b) flying
capacitor and c) cascade multilevel inverter (CMLI). Among these three, the cascaded multilevel
inverter is best suited for railway traction application because of its modular structure and use of
devices at low rating. This thesis presents the application of the cascaded multilevel inverter in a
transformerless railway traction drive. When these inverters are used for transformerless railway
traction drive directly, the THD contents in output voltage of inverters affects the drive
significantly as the performance of drive depends very much on the quality of voltage applied. In
this thesis, the THD contents of 7, 9 and 11 level cascade multilevel inverters have been
analyzed. The THD depends on the switching angles for different units of multilevel inverters;
therefore, the switching angles are calculated first by using Newton-Raphson method where
certain number of harmonic components has been eliminated. It has been found that the eleven
level CMLI satisfies this limit at modulation index of one while seven and nine level CMLI
violates this limit at all modulation index value.
In order to validate the analytical result, IGBT based three-phase cascaded eleven level inverter
using selected harmonic elimination (SHE) PWM technique is simulated with the use of
MATLAB/SIMULINK at modulation index equal to one. The FFT analysis is done and
performance of induction motor fed by eleven level CMLI and ideal AC source has been
compared.
Using calculated switching angles, THD analysis is carried out analytically as well as using
MATLAB simulation and found to be 5.0623% and 6.37% respectively. Both results are in close
agreement with IEEE-519 standard which is 5%.
This eliminates the need of a transformer in the railway traction drives and also results in the
reduction in the Total Harmonic Distortion of the voltage to be supplied to the traction motors.

x
 Chapter one

1. Introduction

1.1. Overview
Railways are basically categorized to Electrified and Diesel-electric systems. This classification
dictates a majority of their characteristics. Based on input voltage source, electrical railway
system can be categorized in to AC traction system and DC traction system. With utilization of
voltage source inverters, AC traction motors are presently common in electric railway traction
applications. Several AC motors such as switched reluctance, permanent magnet synchronous and
asynchronous motors are being used widely in electrified traction applications. Meanwhile,
induction motors are being used as the most popular AC motors for the electrified traction
systems
Several European railway networks supply their rolling stock from single phase 15 or 25 kV with

60, 50, or Hz frequencies. Therefore, the railway vehicles are equipped with a transformer
to reduce the line voltage to a more convenient level for the motor and semiconductors. At such
variable frequencies, the medium voltage transformer suffers from poor efficiency and high
weight. Several research activities have been going on to substitute the transformer by power
electronic concepts to improve its performance.

In this thesis, analysis and modeling of cascaded multilevel inverter fed induction motor with
transformerless approach is studied for traction applications. This system consists of a cascaded
converter and inverter which are serving different jobs such as producing three-phase, 50 Hz, 380
V output voltage for the induction motors through the input voltage with any amplitude and
frequency. This structure is used for converting single phase AC voltage of the catenary to DC
and converting the DC voltage to three phase AC voltage with a SHE PWM controlled inverter.
In such a structure, harmonic currents injected into the power system during the SHEPWM
switching process are low. Using such a structure can reduce the necessity of using a transformer
for feeding the induction motor and also reduce the amounts of harmonics injected to the power
system greatly.

1
1.2. Research Background

1.2.1. Multilevel Inverter

For many power converter applications, it is desirable for the converter to output a desired
waveform with minimum distortion. For example, a DC-AC converter is desired to output a
purely sinusoidal waveform. But for the practical converters, they can just output a series of
rectangular waves. The key issues for the control of the converters are to get the modulation
methods to control the output rectangular waves to synthesize the desired waveforms. Therefore,
a modulation control method needs to generate desired fundamental frequency voltage and
eliminate other higher order harmonics as much as possible.
The most popular modulation method for bi-level converters is the PWM method. Traditional
PWM methods employ switching frequencies on the order of several kHz.
The traditional PWM methods employ much higher switching frequencies for two reasons. The
first reason concerns harmonics. Undesirable harmonics occur at much higher frequencies. Thus,
filtering is much easier and less expensive. The second reason concerns audible noise. Several
kHz is well above the acoustic noise level. Also, if the generated high frequency harmonics are
above the bandwidth of some actual systems, there is no power dissipation due to these
harmonics [1].
But as mentioned above, traditional PWM schemes have the inherent problems of producing
electromagnetic interference (EMI). Rapid changes in voltages (dv/dt) are a source of EMI. The
presence of a high dv/dt can cause damage to electrical motors. High dv/dt produces common-
mode voltages across the motor windings. Furthermore, higher switching frequencies can make
this problem worse due to the increased number of times these common-mode voltages are
applied to the motor during each fundamental cycle. Problems such as motor bearing failure and
motor winding insulation breakdown can result due to circulating currents and voltage surges [2].

Multilevel converters inherently tend to have a smaller dv/dt due to the fact that switching
involves several smaller voltages. Furthermore, switching at the fundamental frequency (50Hz)
will also result in decreasing the number of times these voltage changes occur per fundamental
cycle. There are three topologies of MLCs. They are,
a) Diode clamped multilevel converter, b) Flying capacitor multilevel converter and
c) Cascaded multilevel converter

2
The diode clamped and the flying capacitor type MLCs are fed from a single DC source. The DC
voltage is equally divided employing a string of capacitors. In the diode clamped MLC, diodes
are employed to clamp the voltages to produce a staircase voltage, hence the name diode clamped
MLC. The voltage clamping to produce a staircase is achieved via capacitors in a flying capacitor
type MLC.
Due to the presence of a large number of capacitors in the flying capacitor MLC, the device is
bulky and the operation and control of the device is complex. Hence, the diode clamped and
cascaded MLC are the two topologies that are extensively employed for various applications.
The key issue for multilevel converter modulation is the harmonics elimination. The multilevel
fundamental switching method inherently provides the opportunity to eliminate certain higher
order harmonics by varying the times at which certain switches are turned “on” and turned “off”,
which is also called varying the switching angles.
Harmonic elimination is performed for several reasons. The first reason is harmonics are a
source of EMI. Without harmonic elimination, designed circuits would need more protection in
the form of snubbers or EMI filters [1]. As a result, designed circuits would cost more. The
second reason is that EMI can interfere with control signals used to control power electronics
devices and radio signals. The third reason is that harmonics can create losses in power
equipment. For example, harmonic currents in an electrical induction motor will dissipate power
in the motor stator and rotor windings. There will also be additional core losses due to harmonic
frequency eddy currents. The fourth reason is that harmonics can lower the power factor of a
load. Increased harmonic content will decrease the magnitude of the fundamental relative to the
magnitude of the entire current. As a result, the power factor would decrease [1].
The total harmonic distortion(THD) of the output voltage from a converter is limited by standards
specifications. IEEE-519 standard for the harmonic limit in the electric network is 5% for all
voltage levels below 69 kV and 3% for all voltage above 161kV [9]. Therefore, Harmonics must
always be limited below threshold levels prescribed by standards [9], both in their THD and
individual magnitudes. The THD of the output voltage can be reduced by eliminating or filtering
out the harmonics from the system. The harmonics in the system can be filtered by passive low
pass filters or the harmonics can be eliminated by harmonic elimination technique. The harmonic
elimination method involves solving complex trigonometric equations. The voltage magnitude of

3
the DC sources impacts the elimination of harmonics in the output voltage. Harmonic elimination
is simple when the DC source voltage magnitudes are equal and constant.
The second advantage of multilevel converters concerns switch ratings. Since multilevel
converters usually utilize a large number of DC voltages, several switches are required to block
smaller voltages. Since switch stresses are reduced, required switch ratings are lowered.
The third advantage of multilevel converters concerns system reliability. If a component fails on a
multilevel converter, most of the time the converter will still be usable at a reduced power level.
Furthermore, multilevel converters tend to have switching redundancies. In other words, there
might be more than one way to produce the desired voltage [1].
The fourth advantage of multilevel converters concerns application practicality. Some of the
applications of the multilevel converters include compressors, fans, grinding mills, rolling mills,
conveyers, blast furnace blowers, mine hoists, reactive power compensations, high voltage direct
current (HVDC) transmission, Flexible Alternating Current Transmission System(FACTS), wind
energy conversion, electric traction , railway traction , Hybrid Electric Vehicle. The multilevel
converters are not only for high power applications like HVDC etc but also for low power
requirements like in renewable energy sources. These converters can be easily interfaced with
the renewable energy sources like photo voltaic cells, fuel cells, and wind energy conversion [3].
Application of the multilevel inverters in electric railway traction is a recent development. Thus,
power electronics is contributing toward a greener and cleaner world.

One disadvantage of multilevel converters is that they require more devices than traditional
converters. The system cost may increase (part of the increased cost may be offset by the fact
switches with lower ratings are being used). Using more devices also means the probability of a
system failure will increase. Another disadvantage of multilevel converters concerns control of
the switches. The increased number of switches will result in more complicated control.

There are four popular modulation methods for multilevel converter control, space vector control
method, selective harmonic elimination method, space vector PWM method and sinusoidal PWM
method. Among these methods, space vector control method, space vector PWM method, and
sinusoidal PWM method cannot completely eliminate the specified harmonics. Only selective
harmonic elimination method can completely eliminate the specified harmonics. Due to this
reasons selective harmonic elimination (SHE PWM) method is selected for controlling the

4
switching angle of cascaded H-bridge multilevel inverter for transformerless railway traction
drive application.
The space vector PWM method and sinusoidal PWM method will cause high switching loss and
low efficiency due to the high switching frequency. A disadvantage for the space vector PWM
method and the space vector control method is that they cannot be applied to multilevel
converters with unequal DC voltages.

1.2.2. High-power medium-voltage drives classification

Fig1.1 shows a simplified classification of converters used in high-power medium-voltage
applications, which have a main division into direct and indirect connections of power supply
and load. The former usually connects the load to the source directly through power
semiconductors and suitable control method. The latter transfers the power indirectly in
to two stages of rectification and inversion via an energy-storage component [11].
For direct conversion, cycloconverters are the most used topology in high power
applications, which use a series of semiconductor switches to connect directly the high
power supply to the load. Cycloconverters convert a three- phase ac voltage with a fixed
magnitude and frequency to a three-phase ac voltage with variable magnitude and
variable frequency. Matrix converters are included in this category but they are not listed
in classification, since the technology is not available for high-power ranges, reaching
only u p t o 150 kVA [12].
In the other side of this classification, indirect converters are divided basically into current-
source and voltage-source topologies, depending on the dc-link energy-storage
Component.

For current-source drives, two topologies have found industrial applications in high power ranges:
the load-commutated inverter (LCI) and the PWM-CSI. The LCI has been utilized for many years
presenting simple converter topology, low manufacturing cost, and reliable operation. Its main
problems include low input power factor and distorted input current waveforms, which these
problems are overcame by the newer technology of PWM-CSI [13].

5
 Medium voltage drives

Direct conversion Indirect conversion

ac -ac
(DC-link) ac-dc-ac

cycloconverter
ac
Current source Voltage source

PWM current
source inverter
Multilevel inverter High power
Load commutated
2-Level
inverter

Single DC source Multiple isolated

DC source

NPC Cascaded H-Bridge

Flying
capacitor Symmetric (equal
DC source)

Asymmetric
(unequal DC)
)source)
Fig 1.1: Classification of converters topologies for high-power drives
On the other hand, high-power voltage-source inverters (VSI), have attracted more markets and
developed significantly over the last decades, compared to current-source topologies. The
voltage-source drives are divided in two groups of high-power two-level and multilevel inverters.
The simplest topologies of VSIs are single-phase half-bridge inverter which generates a 2 level
square-wave voltage and full-bridge inverter which generates 3-level waveform. These classical
inverters were limited to low or medium power applications due to the limitations on the power

6
semiconductor voltages and currents. The series connection of semiconductor switches enabled
high two level VSI for high-power applications.

However, the addition of some other power components, like diodes or capacitors, and utilization
of more complex switching methods permitted a more interesting use of these additional
components to enhance the quality of input and output currents and voltages, originating the
family of multilevel VSI technology.

Although multilevel inverters were basically developed to reach higher voltage operation, before
being restricted by semiconductor limitations, the extra switches and dc sources (supplied by dc-
link capacitors) could be used to generate different voltage levels, enabling the generation of
stepped waveform with less harmonic distortion, reducing dv/dt and common-mode voltages.
These characteristics have made them popular for high-power medium-voltage applications but
the large number of semiconductor switches in these inverters, result in a reduction both of the
reliability and efficiency of the drive [14]. Therefore, many power electronic researchers have
made great effort in developing multilevel inverters with the same benefits and less number of
semiconductor devices.

1.2.3. Induction motor drives using multi-level inverter

Many current and future designs will incorporate the use of induction motors as the primary
source for traction in electric vehicles. Designs for heavy duty trucks and many military combat
vehicles that have large electric drives will require advanced power electronic inverters to meet
the high power demands (1-50 MW)[2]. Development of electric drive trains for these large
vehicles will result in increased fuel efficiency, lower emissions, and likely better vehicle
performance (acceleration and braking). Multilevel inverters are uniquely suited for these
applications because of the high VA ratings possible with these inverters.

Nowadays, the induction motors are used in the inverter-driven electric train. It can withstand the
mechanical shock, high temperature and the vibration due to the harmonics present in the supply
voltage of the inverter. Due to the absence of the brushes in IMs, the maintenance is low and the
weight is reduced. It has better torque characteristics [15]. These favorable characteristics of IMs
served as a motivation to use IMs in the traction drive. First, the silicon-controlled rectifier (SCR)
or thyristor was developed, which made the voltage-regulation requirement for DC traction

7
motors much easier. Then the gate-turnoff thyristor was developed, which made the three-phase
induction-motor inverter drive become a standard. Now the insulated-gate bipolar transistor
(IGBT) is taking over from the GTO and is expected to consolidate the supremacy of the inverter
drive and further improve its performance.

1.3. Problem Description

Steam and diesel engines were considered to be a source of environmental disaster on wheels.
Thus, there was a desire to improve the efficiency and reliability of the steam traction drive.
Electric Railway Traction Drive has been introduced as a solution to the environmental problem
caused by the diesel or steam engines. Several European railway networks supply their rolling

stock from single phase 15 or 25 kV with 60, 50, or Hz frequencies. The Ethiopian under
construction railway network also supply the rolling stock from single phase 25kV with 50Hz
frequency. Therefore, the railway vehicles are equipped with a transformer to reduce the line
voltage to a more convenient level for the motor and semiconductors. The transformer used in the
electric locomotive is the most heavy and expensive equipment. It requires a large floor space and
harmonic currents in the transformer lead to increase in temperature because of the losses. The
alternating magnetic field caused by the harmonic current lead to unwanted noise and vibration,
thus making it uncomfortable for the passengers. So this thesis proposed to eliminate
magnetically coupled bulky transformer using cascaded multilevel converter method. This thesis
typically focused on the analysis and modeling of cascaded multilevel inverter for transformerless
electric railway traction drive part to get the desired voltage and frequency for induction motor
drive application. This transformerless drive increases efficiency and reduces the cost of the
traction drive.

8
1.4. Objective

1.4.1. General Objective

The general objective of this research is to design and analysis of cascaded H-bridge multilevel
inverter drive for electric railway traction.

1.4.2. Specific Objectives

 Propose the method to find proper switching angles to minimize the total harmonic
distortion in multilevel voltage waveform.
 Study the relationship between the number of output levels and the total harmonic
distortion with different modulation index.
 Simulate the results by Matlab/Simulink software

1.5. Significance of the Study

The benefits that can be achieved from this research are:

 It reduce the cost, weight, large floor space , unwanted noise and vibration effect by using
power electronics transformer rather than using the conventional type transformer. It also
increases the efficiency of the traction drive.
 Since multilevel voltage source inverter is recently applied in many applications such as
ac power supplies, static VAR compensators, flexible AC transmission systems,
renewable energy sources, active power filters and drive system, so having knowledge in
such area can contribute to transfer technology of the above listed applications in
Ethiopia.

1.6. Scope of the Study

The scope of this thesis:

 The study mainly focuses on analyzing and modeling of cascaded H-bridge multilevel
inverter drive for electric railway traction application.

 Computer simulation of cascaded H-bridge multilevel inverter using Matlab/

simulink.

9
1.7. Methodology
Literature review: A number of journals, article and papers on different types of multilevel
inverter and modulation techniques for electrical train drive application have been reviewed.

Conceptual study of selected method: Understanding the working principle of multilevel

inverter and modulation techniques in general and CHBMLI with SHEPWM modulation
techniques in particular and applying for electrical train drive application.

Data collection: Standard data that related to Ethiopian electrical railway train system have been
collected from Ethiopian Railways Corporation (ERC).

Analysis and modeling of eleven level cascaded H-bridge multilevel inverter: CHBMLI with
SHEPWM modulation technique have been modeled for electrical train drive application. The
switching angles have been analyzed using Newton-Raphson method.

Simulation of eleven level cascaded H-bridge multilevel inverter: using the calculated
switching angles by Matlab/Simulink software, simulation of 11 level CHBMLI have been
performed.
Result and analysis: The simulated results are compared with the results obtained using a
mathematical model to check the validity of the result.

1.8. Organization of the thesis

This thesis consists of six chapters. Chapter 2 reviews the technical literature related to the topics
multilevel inverters and multilevel modulation techniques .Chapter 3 discusses about the electric
traction drive, steam traction drive and the diesel traction drive used in railway systems. The
classical multilevel inverter topologies, their advantages and disadvantages are discussed.
Various applications of these inverters are also discussed. Different types of the modulation
techniques available for the multilevel converters are described. Chapter 4 presents about eleven
level cascaded H-bridge multilevel inverter modeling. The simulation result and discussion will
be presented in chapter 5. Finally chapter 6 will conclude all work and recommend the future
work.

10
 Chapter Two

2. Literature review
This section reviews the technical literature related to the topics multilevel inverters and
multilevel modulation techniques dealt in this research work.

2.1. Multilevel Inverter

History of multilevel inverters began in 1975 by Baker and Bannister. This first patent describes a
converter topology capable of producing multilevel voltage by connecting single phase inverter in
series. The topology called series connected H-Bridge inverter also known as cascaded H bridge
inverter.

Leopoldo G et al(2008)[4] presented that the railway electric traction requires high voltage
operation. This can be fulfilled by the series and/or parallel combination of various semi-
conductor devices. But because of the differences in their inherent characteristics, it will damage
the devices. This limitation can be overcome with the help of multilevel converter. The output
voltage of multilevel inverter has low harmonic content (THD) in comparison to that of a two
level inverter.

S.kouro et al (2010)[3] Proposed with the help of the multilevel inverter, the transformation of
the voltage level can be done without the help of the bulky transformer. This results in
transformerless traction drives. Thus, the multilevel inverter prevents the motor damage and
thereby increases the efficiency of the drive.

Shahnia and Sharifian(2005) [5] presented that the multilevel inverters can be directly connected
to the high voltage supply and can step down the voltage. Thus, it eliminates the need of the
transformer. This transformerless drive increases efficiency and reduces the cost of the traction
drive.

11
Manjrekar and Steimer (2000)[14] introduced a NPC PWM inverter and examined in detail about
the theory, design and performance of NPC PWM. Diode clamping inverter suffers from DC link
unbalance and indirect clamping of the inner devices. This inverter is unable to control real power
flow in multilevel inverter.

Verma and Thakur (2011)[24] proposed a FCM inverter with experimental results which had
been carried out to prove the validity and effectiveness of the scheme. In this inverter an
excessive number of storage capacitors are required and controlling circuit is complex.

Song et al (2006)[25] presented a generalized multilevel inverter topology with self voltage
balancing. The existing multilevel inverters such as diode-clamped and capacitor-clamped
multilevel inverters can be derived from the generalized inverter topology. Moreover, the
generalized multilevel inverter topology provides a true multilevel structure that can balance each
DC voltage level automatically without any assistance from other circuits. Thus, in principle
providing a complete and true multilevel topology that embraces the existing multilevel inverters.

Meynerd and Foch(1992)[29] presented a general structure for cascaded power converters in
which any numbers of H-bridge cells having any number of voltage levels are in series connected
to form an inverter phase leg. In this paper, it was experimentally verified by cascading a five-
level H-bridge cell with a three-level H-bridge cell.

Rodriguez et al (2002)[31] discussed the most important topologies such as diode clamped
inverter, capacitor clamped and cascaded multi cell with separate DC sources. The most relevant
control and modulation methods for this family of converters are also presented.

Chiasson and Knzie (2003)[41] designed and implemented control of a multilevel converter using
resultant theory which compute the switching angle to produce the required fundamental voltage
while at the same time it cancel out specified higher order harmonics. The experimental results
are validated and compared with simulation results.
S.kouro et al (2010)[3] investigated a survey on cascaded multilevel inverters. The survey of
different topologies, control strategies and modulation techniques used by the inverters are

12
investigated which reveals several remarkable features of cascaded multilevel inverter such as
high degree of modularity, high power quality and the control of power flow in the regenerative
version.

2.2. Multilevel Modulation Techniques

Tolbert and Peng (1999)[2] proposed multilevel Pulse Width Modulation (PWM) methods at low
modulation indices. In this paper, novel multilevel PWM strategies take advantage of the multiple
levels in both diode clamped inverter and cascaded H-bridges inverter by utilizing all of the levels
in the inverter even at low modulation indices. These novel carrier-based switching strategies can
be used to enable better switch utilization in multilevel inverters and to achieve an increase in the
effective switching frequency without exceeding the thermal limits of the individual active
devices.

Lee et al (1998)[37] presented the general analytical solution for carrier based PWM to
mathematically identify the harmonic cancellation that occurs in various PWM implementations
and converter topologies. In this paper, the opportunities for harmonic elimination in multilevel
inverter systems by carrier phase shifting are investigated and the optimum phase shift is
identified.

Patel and Hoft (1973)[39] developed cascaded and hybrid inverters using discontinuous PWM
with phase-shifted carriers within each H-bridge of each multilevel phase leg. The new
modulation strategy gives a similar improved harmonic performance for cascaded and hybrid
inverters.
Chiasson et al (2004)[40] presented analytical solutions for determining the spectral
characteristics of multicarrier based multilevel PWM. The proposed control strategy is to reduce
the undesirable harmonics in order to improve the performance and efficiency of multilevel
inverter. The analytical solutions have been cross verified extensively with simulation results
match with each other.

N.V.Suryanarayan (2005)[22] proposed a novel multilevel carrier based PWM control method for
GTO inverter in low index modulation region. Two PWM control based on adding a bias

13
reference voltage of the inverter and switching patterns are presented. The fluctuations of the
neutral point voltage are also reduced using this method.

M.Corpito et al (2008)[17] presented a detailed analysis of the impact of a hybrid multilevel

modulation strategy on the harmonic content of the input currents and output voltages. A new
modulation strategy for hybrid multilevel inverters which can be used with asymmetrical
multipulse connection of uncontrolled rectifiers to improve the input harmonic performance of
adjustable speed drives at every operating point.

Enjeti and Lindsay(2003)[7] proposed a novel algorithm by which switching angles can be
obtained in real-time in the context of step modulation for multilevel inverters. With the
algorithm, the voltage Total Harmonic Distortion (THD) is minimized, which is proven by the
mathematical derivation and verified by the THD comparison.

Maswood et al(2001)[8] presented that Selective Harmonic Elimination Pulse Width Modulation
(SHE-PWM) has been intensively studied in order to achieve low THD. The common
characteristic of the SHE-PWM method is that the waveform analysis is performed using Fourier
theory. Sets of non-linear transcendental equations are then derived, and the solution is obtained
using an iterative procedure, mostly by Newton-Raphson method.

The above literature review reveals that there exists a need for reducing the total harmonic
distortion and enhance the output voltage in multilevel inverter. Hence, in this work, minimizing
the total harmonic distortion and enhancing the output voltage is performed using SHEPWM
modulation techniques for railway traction drive application.

14
 Chapter Three

3. Electric Traction

3.1. Introduction
The development of electric and electric vehicles will offer many new opportunities and
challenges to the power electronics industry, especially in the development of the main traction
motor drive. Many current and future designs will incorporate the use of induction motors as the
primary source for traction in electric vehicles.

Large electric drives will require advanced power electronic inverters to meet the high power
demand (1-50MW) required of them [3]. The cascaded inverter with separate dc source closely
fits the needs of all-electric vehicles because it can use the onboard batteries or fuel cells to
synthesize a sinusoidal voltage waveform to drive the main vehicle traction motor. Where
generated ac voltage is available, a back-to-back cascaded H-bridge multilevel converter can be
used to output variable frequency ac voltage for driven motor.

Multilevel inverters also solve problems with present 2-level pulse width modulation (PWM)
adjustable speed drives (ASD‟s). Adjustable speed drives usually employ a front-end diode
rectifier to convert utility ac voltage to variable frequency and variable voltage for motor control.

In this chapter, the railway electrification and its traction drive has been discussed. Comparison
of the steam and diesel traction drive has been done with the electric traction. Different traction
units have been discussed. Traction motor and various other issues have been studied here.

In earlier days, the steam engine drives and the diesel engine drives were used [16]. Their
characteristics and drawbacks are discussed below.

3.2. Steam Engine Drive

Some of the important features of the rail traction employing steam engine drive are:
o Simple in construction
o It does not involve electrification of railway track and hence Low initial cost
o Easy to maintain
o Easy speed control

15
 o No Electromagnetic interference
But it has the following limitations:
o Even though the train may be idle, the fire has to be banked. This results in low thermal
efficiency.
o It requires adequate supply of feed water at regular interval. Also the supply of water and
coal add to the cost.
o To put the steam engine into operation, steaming time is required.
o The steam engine is greatly influenced by the firing rate of the coal.
o Power weight ratio is low.
o Its centre of gravity is high due to the presence of boiler.
o It causes environmental disaster with high carbon emissions.
o The man power requirement is more as compared to the electric drive.
o It cannot be used in underground railways because of the smoke.

3.3. Diesel Engine Drives

This drive has nearly the same characteristics and limitation as that of the steam engine. It does
not have a starting torque and thus requires an external means to start the engine.

3.4. Electric Drive

This involves use of the electric motors fed from overhead distribution system. Some of its
remarkable features are:

o It is the cleanest form of drive.

o It has high starting torque.
o It has high power to weight ratio.
o It enables quicker acceleration.
o Railway electrification leads to rural electrification which is the most important industrial
development.
o It requires less maintenance.
o It does not consume time to start
o Smooth braking is possible with electric braking
o No coal and water required and hence saves money

16
Similarly, the electric drive has some limitations. These include:

o High capital cost is required for electrification

o Power failure can affect the railway system.
o There is problem of electromagnetic interference due to the presence of both the
Communication lines and power lines.

3.5. Railway Electric Traction Drive

3.5.1. Train Systems

At the end of the nineteenth century, railway electrification emerged as a means of traction. The
advent of power electronics concept has proved to a blessing in the field of traction. It supplies
the energy of the catenaries to traction motors in a controlled manner [17].There is a general
power based classification in [18]: Light rails with less than 1MW. Medium loads are commuter
(3-4MW) and high speed intercity (4-6 MW) trains. Very high speed commuters ( 8-10MW) and
freight trains (18-24MW) are high demand railways. To establish a railway system its economical
and technical feasibility, compatibility with other power system customers and adjacent
communicational systems should be considered [18]. Light trains are designed to stop every 2 or
3 km to cover a wide urban area and they require accelerating and decelerating fast enough to be
efficient. When the working field of railway is wider to cover suburban areas, commuter trains
come along. They travel in longer distances and longer intervals (5 to 10 miles) between each
stop and with higher speeds (125 mile/h). Their feeder voltage needs to be AC to reach high
enough voltage levels of 15kV or 25 kV. If frequency of stops is reduced to achieve higher
speeds and more carriage, high speed intercity trains will be defined.

3.5.2. Power Quality

One of main problems regarding to electrified rail ways is power quality shortage that can reduce
other customers‟ usage efficiency below standards. Railway produced power disturbances which
can be classified as below:
A. Power Unbalance
Since electrified trains are single phase loads inherently, connection of these time varying (as
much as they are high speed) unbalance (as much as they are high power) loads to three phase
power system will lead to huge power unbalance. This problem has been facing different

17
solutions. Firstly some countries devoted a specific power system to their ERs and made other
customers isolated from power quality disturbances produced by railway. The other solution is to
use DC transmission systems for trains. This strategy is working and different standard and a few
not standard DC voltage levels are used to supply railway system. In this approach railway is
connected to a main power system through an AC\DC rectifier and all of the power turbulences
are cut off at a point of common coupling by this high voltage rectifier. The other solution was to
design railway train to work as AC load but not necessarily with standard frequency of 50/60 Hz.
There are different voltage levels for this type of railway power feeding.
B. Harmonic distortion
There are speed drives, power conversion equipment or frequency converters that inject harmonic
in to railways supplying power system. These harmonics can disturb other power systems or lead
to high frequency electromagnetic fields incompatible with close equipment as well as train
signaling system. There are some classic solutions for harmonic distortion reduction like third
sequence harmonic eliminator transformers. An active power filter is a modern solution for these
problems such as unbalance, harmonic distortion and low power factor problems.
C. Flicker
As the train passes between two adjacent substations voltage sag may happen and affect other
customers electrical light performance so called flicker. There are some structural solutions
regarding to all of these challenges which are used in different countries. In Germany and
Sweden low frequency systems are used which are low frequency power system in Germany and
frequency conversion in Sweden. However in England, France, USA and Africa higher voltages
has reduced the problem in different manners which are connecting railway supply system to
main network in a high voltage point of common coupling or designing railway system to work
under a higher catenary voltage.

18
3.5.3. Input Voltage Source
As mentioned in train systems classification there are some voltage sources which are used based
on trains exact application. Concentrating on input voltage source, railways can be categorized as
below:
A. DC Voltage Source
The main advantage of DC traction system is simplicity in control. DC voltage supplied ERs can
be split in two approaches. Firstly voltage level of the feeders and secondly the measure which is
used to feed the train. Standard DC voltage levels under load over the world are 600VDC, 750
VDC, 1500 VDC, 3000VDC. There are some non-standard voltage levels as well.
In another approach DC ERs can be classified in which main DC power supply is connected to
trains. Overhead line system and Conductor rail system is main sub categories which can be
manufactured in different schemes. Although the feeder structure for voltage level of 3000VDC
and more is limited to overhead lines. DC voltage supplied railway systems are recommendable
for low power applications. Higher DC voltages for higher power railway application are not
practical because of insulation and clearance restrictions. The power system interface of DC
feeder systems is limited to some harmonics injected to power system at substations that can be
attenuated by appropriate filters. The other problem with DC railway supply system is ground
return current that may be cause of corrosion.
B. AC Voltage Source
Standard AC voltage supply for ERs are 25 kV, 50 Hz which suppose to dominate Europe
railways as a regional standard to unify European railway system [20] or 25 kV, 60 Hz for
countries with 60 Hz power system ex. Japan, US and 15kV, 16.7Hz in Germany, Austria and
Scandinavia and 50kV 50/60 Hz or 2x25kV [21], 50/60 Hz using auto transformers for very high
power applications all installed as overhead single phase lines. Due to less insulation restriction
with higher frequency, much higher voltage level is feasible in AC power transmission to trains,
leading to remarkable reduction in power lose.
Distance between substations and power of each substation depending on trains load, speed and
catenary characteristics varies among 20 to 80 miles. Basically the higher feeder voltage the
longer distance between substations is allowed. Figure 3.1 is an illustration of an electric
locomotive. It can be seen that it consists of the transformer, the main rectifier, the main inverter

19
and the three phase AC motors [21]. This thesis is mainly concerned with the main rectifier, main
transformer, an inverter and three phase AC motors. So these are discussed here in brief.
Main transformer is used to step down the supply voltage before it can be used by the train. Main
rectifier is mainly used for the conversion of AC to DC. Main Inverter is mounted on the trains to
provide alternating current from direct current. It is used for three phase drives. Three phase AC
motors are used to generate tractive force to provide accelerate to the train. Earlier DC motors
were used but nowadays, three phase AC motors are used.

Fig3.1: Schematic layout of an electric locomotive

3.6. Traction Motors

A good traction motor should have the following features:
o Simple speed control
o Better speed torque characteristics
o High starting speed
o It should be suitable for dynamic or regenerative braking
o The commutations should be good even the supply voltage fluctuates.
o It should be robust and withstand continuous vibration due to the high speed.
o It should have less weight and small size.

20
 o They should be protected from dirt and dampness.
All these above requirements are not fulfilled by any single motor. For DC system, DC series and
compound motors are used. For single phase AC system, AC series motor is used and for three
phase system, induction motors are used [22].
DC series motors have high starting torque and variable speed characteristics. For this reason, it is
very much used for electric traction. But because of presence of brushes and commutation
problem, three phase induction motors are used.
Nowadays, the three phase induction motor is generally used as traction motor because of the
following reasons:
o Absence of brushes.
o Robustness and reliability with low maintenance
o Simple cooling arrangement with enclosed frames
o High uniform torque with inherent overload management
o High power to weight ratio
o High voltage operation
o Low cost to power ratio
o High maximum speeds
o Inherent regenerative braking capability
o Steep torque speed characteristics

3.7. Converters and Transformers in Traction Drive

The increase of the world energy demand has entailed the appearance of new power converter
topologies and new semiconductor technology capable to drive all needed power. A continuous
race to develop higher-voltage and higher-current power semiconductors to drive high power
systems still goes on. In this way, the last-generation devices are suitable to support high voltages
and currents (around 6.5 kV and 2.5 kA). However, currently there is tough competition between
the use of classic power converter topologies using high-voltage semiconductors and new
converter topologies using medium-voltage devices [4].
Earlier, thyristor were used in the converters. But nowadays, IGBTs are replacing GTO thyristor
and are commonly used in the cascaded multilevel inverter as it is smaller and requires less
current to operate the switching sequences [21]. It offer low on-resistance and require very little
gate drive power. Its switching takes place easily and with low power loss. Also it can handle the
21
high power required by the motor drives. The IGBT based traction propulsion system has lesser
losses, better controllability, superior performance, high reliability and modular design as
compared to the GTO- based system.
The Ethiopian under construction electrical railway locomotive main circuit system is composed
of primary circuit and secondary circuit of main transformer. Pantograph receives power of AC
25kV, 50Hz from catenary, then power will be input into main transformer via high voltage
isolation switch and MCB (main circuit breaker), and primary current will be returned to earth via
axle end earthing device. Primary circuit of main transformer is set with lightning arrester, HV
voltage transformer, HV current transformer and back-flow current transformer.
Locomotive micro-processer control system takes effect of detection and protection of over-
voltage, under-voltage and over-current against primary, and takes effect of differential protection
against transformer primary. Six secondary windings of main transformer supply power to 2 main
converters. Main converter applies IGBT converter unit with 3.3kV level to feed 6 traction
motors with vvvf AC power. Traction motor applies 3-phase AC asynchronous motor, and main
circuit is provided with over-voltage, over-current and earthing protection.
The transformer used in this electric locomotive is the most heavy and expensive equipment. It
causes several losses and reduces efficiency. It requires a large floor space. Due to the saturation
of the transformer, it leads to dc magnetizing and dc overvoltage of the inverters [25]. Harmonic
currents in the transformer lead to increase in temperature because of the losses. The alternating
magnetic field caused by the harmonic current lead to unwanted noise and vibration [26].Thus,
making it uncomfortable for the passengers. But with the help of the cascaded multilevel
converter, this magnetically coupled bulky transformer can be eliminated and the multilevel
converter can be used for stepping down the voltage. The Schematic diagram of drive system of
induction motors used in railway traction system is shown in fig 3.2.This transformerless drive
increases efficiency and reduces the cost of the traction drive.

22
 Single phase
1M
Overhead
distribution system
c

50 HZ, 25kV 2M
AC Supply
Cascaded Cascaded
Multilevel Rectifier Multilevel
Inverter

6M

Six Induction Motors

Fig 3.2: Schematic diagram of the drive system of induction motors used in railway traction
system.

3.8. Multilevel Voltage Source Inverter

The multilevel voltage source inverter is recently applied in many industrial applications such as
ac power supplies, static VAR compensators, drive systems, etc. One of the significant
advantages of multilevel configuration is the harmonic reduction in the output waveform without
increasing switching frequency or decreasing the inverter power output [27]. The output voltage
waveform of a multilevel inverter is composed of the number of levels of voltages, typically
obtained from capacitor voltage sources. The so-called multilevel starts from three levels. Due to
the bi-directional switches, the multilevel VSC can work in both rectifier and inverter modes.
This is why most of the time it is referred to as a converter instead of an inverter in this thesis. As
the number of levels reach infinity, the output THD approaches zero. The number of the
achievable voltage levels, however, is limited by voltage unbalance problems, voltage clamping
requirement, circuit layout, and packaging constraints.

23
The multilevel inverter structures are the main focus of discussion in this section; however, the
illustrated structures can be implemented for rectifying operation as well. Although each type of
multilevel converters share the advantages of multilevel voltage source inverters, they may be
suitable for specific application due to their structures and drawbacks. Operation and structure of
some important type of multilevel converters are discussed in the following sections.

In this thesis, three capacitor voltage synthesis-based multilevel inverters are introduced, i.e.

1) Diode-Clamped Multilevel Inverter [27].

2) Flying-Capacitor Multilevel Inverter [27].

3) Cascaded-Inverters with Separated DC Sources [27], [28].

3.8.1. Diode-Clamped Multilevel Inverter

The most commonly used multilevel topology is the diode clamped inverter, in which the diode is
used as the clamping device to clamp the dc bus voltage so as to achieve steps in the output
voltage. The neutral point converter proposed by Nabae, Takahashi, and Akagi in 1981 was
essentially a three-level diode-clamped inverter. A three-level diode clamped inverter consists of
two pairs of switches and two diodes. Each switch pairs works in complimentary mode and the
diodes used to provide access to mid-point voltage. In a three-level inverter each of the three
phases of the inverter shares a common dc bus, which has been subdivided by two capacitors into
three levels. The DC bus voltage is split into three voltage levels by using two series connections
of DC capacitors, and . The voltage stress across each switching device is limited to
through the clamping diodes Dc1 and Dc2. It is assumed that the total dc link voltage is and
mid point is regulated at half of the dc link voltage, the voltage across each capacitor is /2
( = = /2). In a three level diode clamped inverter, there are three different possible
switching states which apply the stair case voltage on output voltage relating to
DC link capacitor voltage rate. For a three-level inverter, a set of two switches is on at any given
time and in a five-level inverter, a set of four switches is on at any given time and so on. Fig 3.3
shows the circuit for a diode clamped inverter for a three-level and a five-level inverter.
Switching states of the three level inverter are summarized in table 3.1

24
Table 3.1: Switching states in one leg of the three-level diode clamped inverter

Switch Status State Pole voltage

S1 = ON, S2 =ON S = +ve = /2
S1‟ = OFF,S2‟ = OFF
S1=OFF,S2=ON S=0 =0
S1‟=ON,S2‟=ON
S1=OFF,S2=OFF
S1‟=ON,S2‟=ON S= -ve =- /2

The voltage across each capacitor for an N level diode clamped inverter at steady state is /
, N-level output phase voltage and a -level output line voltage. Although each
active switching device is required to block only a voltage level of , the clamping diodes
require different ratings for reverse voltage blocking.

Vdc/2 S1

C1
D1
Vdc/4 S2

C2
S3
D‟1 D2

D3 S4
Vdc
a
n
D‟2 S‟1
Vdc/2 S1
C1
Van
C3

D1 S2 S‟2
-Vdc/4
Van
a
Vdc D‟3
D‟1 S‟1 S‟3

C4
C2 -Vdc/2 S‟2 -Vdc/2
S‟4
0 0
(a)
(b)

Fig 3.3: Topology of the diode-clamped inverter (a) three-level inverter, (b) five -level inverter

25
In general for an N level diode clamped inverter, for each leg 2(N-1) switching devices, (N-1) *
(N-2) clamping diodes and (N-1) dc link capacitors are required. By increasing the number of
voltage levels the quality of the output voltage is improved and the voltage waveform becomes
closer to sinusoidal waveform. However, capacitor voltage balancing will be the critical issue in
high level inverters. When N is sufficiently high, the number of diodes and the number of
switching devices will increase and make the system impracticable to implement. If the inverter
runs under pulse width modulation (PWM), the diode reverse recovery of these clamping diodes
becomes the major design challenge.

A. Operation of DCMLI

Fig 3.3(a) shows a three-level diode-clamped converter in which the dc bus consists of two
capacitors, C1, C2. For dc-bus voltage , the voltage across each capacitor is /2 and each
device voltage stress will be limited to one capacitor voltage level /2 through clamping diodes.
To explain how the staircase voltage is synthesized, the neutral point n is considered as the output
phase voltage reference point. There are three switch combinations to synthesize three-level
voltages across a and n.
1) Voltage level = /2, turn on the switches S1 and S2.
2) Voltage level = 0, turn on the switches S2 and S1'
3) Voltage level =- /2 turn on the switches S1',S2'.
Fig 3.3(b) shows a five-level diode-clamped converter in which the dc bus consists of four
capacitors, C1, C2, C3, and C4. For dc-bus voltage , the voltage across each capacitor is /4
and each device voltage stress will be limited to one capacitor voltage level /4 through
clamping diodes.
Table 3.2: Switching states of the five level inverter

Voltage Switch state

S1 S2 S3 S4 S1‟ S2‟ S3‟ S4‟
= 1 1 1 1 0 0 0 0
= /2 0 1 1 1 1 0 0 0
=0 0 0 1 1 1 1 0 0
= - /2 0 0 0 1 1 1 1 0
=- 0 0 0 0 1 1 1 1

26
Four complementary switch pairs exist in each phase. The complementary switch pair is defined
such that turning on one of the switches will exclude the other from being turned on. In this
example, the four complementary pairs are (S1 –S1'), (S2- S2'), (S3 – S3'), and (S4 - S4').
Although each active switching device is only required to block a voltage level of / (m-1), the
clamping diodes must have different voltage ratings for reverse voltage blocking. Using D1' of
Fig 3.3(b) as an example, when lower devices S2'- S4', are turned on, D1' needs to block three
capacitor voltages, or 3 /4, and D1 needs to block /4. Similarly, D2 and D2' need to block
2 /4, and D3 needs to block 3 /4. Assuming that each blocking diode voltage rating is the
same as the active device voltage rating, the number of diodes required for each phase will be (m-
1)*(m-2). This number represents a quadratic increase in m.
B. Features of Diode clamped MLI
1) High-Voltage Rating Required for Blocking Diodes:
Although each active switching device is only required to block a voltage level of /(m - l), the
clamping diodes need to have different voltage ratings for reverse voltage blocking. Using D1' of
Fig 3.3 (b) as an example, when all lower devices, S1'-S4' are turned on, D1' needs to block three
capacitor voltages, or 3 /4. Similarly, D2 and D2' need to block 2 /4, and D3 needs to block
3 /4. Assuming that each blocking diode voltage rating is the same as the active device voltage
rating, the number of diodes required for each phase will be (m - 1) x (m - 2). This number
represents a quadratic increase in m. When m is sufficiently high, the number of diodes required
will make the system impractical to implement.
2) Unequal Device Rating,
In table 3.2 it can be seen that switch S1 conducts only during = , while switch S4
conducts over the entire cycle except during - . Such an unequal conduction duty
requires different current ratings for switching devices. When the inverter design is to use the
average duty for all devices, the outer switches may be oversized, and the inner switches may be
undersized. If the design is to suit the worst case, then each phase will have 2 x (m - 2) outer
devices oversized. In comparison with the traditional transformer coupling multipulse converters
using six-step operation for each converter, such unequal conduction duty is indeed an
advantageous feature because the six-step operation needs maximum duty in each device and
circulating currents between converters through transformers.

27
 3) Capacitor Voltage Unbalance:
In most applications, a power converter needs to transfer real power from ac to dc (rectifier
operation) or dc to ac (inverter operation). When operating at unity power factor, the charging
time for rectifier operation (or discharging time for inverter operation) for each capacitor is
different. Such a capacitor charging profile repeats every half cycle, and the result is unbalanced
capacitor voltages between different levels. The voltage unbalance problem in a multilevel
converter can be solved by several approaches, such as replacing capacitors by a controlled
constant dc voltage source such as pulse-width modulation (PWM) voltage regulators or batteries.
The use of a controlled dc voltage will result in system complexity and cost penalties. With the
high power nature of utility power systems, the converter switching frequency must be kept to a
minimum to avoid switching losses and electromagnetic interference (EMI) problems. When
operating at zero power factors, however, the capacitor voltages can be balanced by equal charge
and discharge in one-half cycle. This indicates that the converter can transfer pure reactive power
without the voltage unbalance problem
C. Advantages and Disadvantages of DCMLI

Advantages:
o All of the phases share a common dc bus, which minimizes the capacitance requirements
of the converter. For this reason, a back-to-back topology is not only possible but also
practical for uses such as a high-voltage back-to-back inter-connection or an adjustable
speed drive.
o The capacitors can be pre-charged as a group.
o Efficiency is high for fundamental frequency switching.
o When the number of levels is high enough, harmonic content will be low enough to avoid
the need for filters
Disadvantages
o Real power flow is difficult for a single inverter because the intermediate dc levels will
tend to overcharge or discharge without precise monitoring and control.
o The number of clamping diodes required is quadratic ally related to the number of levels
[1], which can be cumbersome for units with a high number of levels.

28
3.8.2. Flying Capacitor Structure
The capacitor clamped inverter alternatively known as flying capacitor was proposed by Meynard
and Foch in 1992 [30]. The structure of this inverter is similar to that of the diode-clamped
inverter except that instead of using clamping diodes, the inverter uses capacitors in their place.
The flying capacitor involves series connection of capacitor clamped switching cells. This
topology has a ladder structure of dc side capacitors, where the voltage on each capacitor differs
from that of the next capacitor. The voltage increment between two adjacent capacitor legs gives
the size of the voltage steps in the output waveform. Figure 3.4 shows the three-level and five-
level capacitor clamped inverters respectively.

Vdc/2 S1

C4

Vdc/4 S2
C3
C4
C3 S3

C3 S4
n C2
Vdc
a
C1
S‟1
C2 S1 C2
Van
C4

S2 S‟2
-Vdc/4
Van
n C1 a
Vdc
S‟1 S‟3

C4
C2 S‟2 S‟4
0 -Vdc/2
0
(a)
(b)

Fig 3.4: FCMLI circuit topologies, (a) 3-level inverter (b) 5- level inverter

29
 A. Operation of FCMLI

In the operation of flying capacitor multi-level inverter, each phase node can be
connected to any node in the capacitor bank . Connection of the a-phase to positive
node V3 occurs when S1 and S2 are turned on and to the neutral point voltage when S2 and S1‟
are turned on. The negative node V1 is connected when S1' and S2' are turned on. The clamped
capacitor C1 is charged when S1 and S1' are turned on and is discharged when S2 and S2' are
turned on. The charge of the capacitor can be balanced by proper selection of the zero states. In
comparison to the three-level diode-clamped inverter, an extra switching state is possible. In
particular, there are two transistor states, which make up the level V3. Considering the direction
of the a-phase flying capacitor current for the redundant states, a decision can be made to
charge or discharge the capacitor and therefore, the capacitor voltage can be regulated to its
desired value by switching within the phase. As with the three-level flying capacitor inverter, the
highest and lowest switching states do not change the charge of the capacitors. The two
intermediate voltage levels contain enough redundant states so that both capacitors can be
regulated to their ideal voltages.
Similar to the diode clamped inverter, the capacitor clamping requires a large number of bulk
capacitors to clamp the voltage. Provided that the voltage rating of each capacitor used is the
same as that of the main power switch, an N level converter will require a total of (N-1) * (N-
2) / 2 clamping capacitors per phase in addition to the (N-1) main dc bus capacitors.
Unlike the diode-clamped inverter, the flying-capacitor inverter does not require all of the
switches that are on (conducting) in a consecutive series. Moreover, the flying-capacitor inverter
has phase redundancies, whereas the diode-clamped inverter has only line-line redundancies.
These redundancies allow a choice of charging/discharging specific capacitors and can be
incorporated in the control system for balancing the voltages across the various levels.
The voltage synthesis in a five-level capacitor-clamped converter has more flexibility than a
diode-clamped converter. Using Fig 3.4 (b) as the example, the voltage of the five-level phase leg
a output with respect to the neutral point n (i.e. ), can be synthesized by the following switch
combinations.
1) Voltage level = /2, turn on all upper switches S1 - S4.
2) Voltage level = /4, there are three combinations.

30
 a) Turn on switches S1, S2, S3 and S1‟.

b) Turn on switches S2, S3, S4 and S4‟.

c) Turn on switches S1, S3, S4 and S3‟.

3) Voltage level = 0, turn on all upper switches S3, S4 and lower switches S1‟, S2‟.
4) Voltage level =- /4, turn on all upper switches S1 and lower switches S1‟,S2‟ and
S3‟
5) Voltage level =- /2, turn on all lower switches S1‟ , S2‟,S3‟ and S4‟
B. Features of FCMLI

The major problem in this inverter is the requirement of a large number of storage capacitors.
Provided that the voltage rating of each capacitor used is the same as that of the main power
switch, an m-level converter will require a total of (m - 1) x (m - 2)/2 auxiliary capacitors per
phase leg in addition to (m - 1) main dc bus capacitors. With the assumption that all capacitors
have the same voltage rating, an m-level diode-clamp inverter only requires (m - 1) capacitors. In
order to balance the capacitor charge and discharge, one may employ two or more switch
combinations for middle voltage levels (i.e., 3 /4. /2, and /4) in one or several
fundamental cycles. Thus, by proper selection of switch combinations, the flying-capacitor
multilevel converter may be used in real power conversions. However, when it involves real
power conversions, the selection of a switch combination becomes very complicated, and the
switching frequency needs to be higher than the fundamental frequency. In summary, advantages
and disadvantages of a flying capacitor multilevel voltage source converter are as follows.

C. Advantages and Disadvantages of (FCMLI)

Advantages
Compared to the diode-clamped inverter, this topology has several unique and attractive features
as described below:
o Added clamping diodes are not needed.
o It has switching redundancy within the phase, which can be used to balance the flying
capacitors so that only one dc source is needed.

31
 o The required number of voltage levels can be achieved without the use of the transformer.
This assists in reducing the cost of the converter and again reduces power loss.
o Unlike the diode clamped structure where the series string of capacitors share the same
voltage, in the capacitor-clamped voltage source converter the capacitors within a phase
leg are charged to different voltage levels.
o Real and reactive power flow can be controlled.
o The large number of capacitors enables the inverter to ride through short duration outages
and deep voltage sags.
Disadvantages
o Converter initialization i.e., before the converter can be modulated by any modulation
scheme the capacitors must be set up with the required voltage level as the initial
charge. This complicates the modulation process and becomes a hindrance to the
operation of the converter.
o Control is complicated to track the voltage levels for all of the capacitors.
o Precharging all of the capacitors to the same voltage level and startup are complex
o Switching utilization and efficiency are poor for real power transmission.
o Since the capacitors have large fractions of the dc bus voltage across them, rating of
the capacitors are a design challenge.
o The large numbers of capacitors are both more expensive and bulky than clamping
diodes in multilevel diode-clamped converters.
o Packaging is also more difficult in inverters with a high number of levels.

3.8.3. Cascaded Multilevel Inverter

Multilevel voltage source inverter using cascaded inverters with separate dc sources (SDCSs),
hereafter called a cascaded multilevel inverter appears to be superior to other multi level
structures in term of its structure that is not only simple and modular but also requires the least
number of output voltage levels without undue increase in power circuit complexity. In addition,
extra clamping diodes or voltage balancing capacitors are not necessary. An important key in
designing an effective and efficient cascaded H-bridge multilevel inverter is to ensure that the
total harmonic distortion (THD) in the output voltage waveform is small enough [9].
The series H-bridge inverter appeared in 1975[14]. Cascaded multilevel inverter was not fully
realized until two researchers, Lai and Peng. They patented it and presented its various
32
advantages in 1997. Since then, the CMI has been utilized in a wide range of applications. With
its modularity and flexibility, the CMI shows superiority in high-power applications, especially
shunt and series connected FACTS controllers. The CMI synthesizes its output nearly sinusoidal
voltage waveforms by combining many isolated voltage levels. A series of single-phase full
bridges makes up a phase for the inverter. A three-phase CMI topology is essentially composed
of three identical phase legs of the series-chain of H-bridge converters, which can possibly
generate different output voltage waveforms and offers the potential for AC system phase-
balancing. This feature is impossible in other VSC topologies utilizing a common DC link. Since
this topology consists of series power conversion cells, the voltage and power level may be easily
scaled. The dc link supply for each full bridge converter is provided separately, and this is
typically achieved using cascaded H-bridge multilevel rectifiers or diode rectifiers fed from
isolated secondary windings of a three-phase transformer. Phase-shifted transformers can supply
the cells in medium-voltage systems in order to provide high power quality at the utility
connection.

a
C1

a
C1 C2

a
C1 n C2 n C3 n

(a) (b) (c)

Fig 3.5: Single phase structures of Cascaded inverter (a) 3-level, (b) 5-level, (c) 7-level

33
 A. Operation of CMLI

The converter topology is based on the series connection of single-phase inverters with separate
dc sources. Fig 3.5 shows the power circuit for one phase leg of a three-level , five-level and
seven-level cascaded inverter. The resulting phase voltage is synthesized by the addition of the
voltages generated by the different cells. In a 3-level cascaded inverter each single-phase full
bridge inverter generates three voltages at the output: + , 0, - (zero, positive dc voltage,
and negative dc voltage). This is made possible by connecting the capacitors sequentially to the
ac side via the power switches. The resulting output ac voltage swings from - to + with
three levels, -2 to +2 with five-level and -3 to +3 with seven-level inverter. The
staircase waveform is nearly sinusoidal, even without filtering. For a three-phase system, the
output voltage of the three cascaded converters can be connected in either wye (Y) or delta (Δ)
configurations. Fig 3.6 shows an IGBT based three phase eleven level cascaded inverter which is
used in the modeling of the traction drive.
A B C

Fig 3.6: Power circuit of three phase cascaded H-bridge eleven level inverter using IGBT

34
Fig 3.7 shows the output phase voltage waveform of an eleven level inverter. The number of
output phase voltage levels m in a cascade converter with s separate DC sources is m = 2s + 1.
Load balance control for each H-bridge and each DC source can be acquired by rotating the
switching angles to the H-bridges [2].
Vph

π/2 π 2π
ωt

Fig 3.7: Output phase voltage waveform of an eleven level cascaded multilevel inverter

B. Features of CMLI

For real power conversions, (ac to dc and dc to ac), the cascaded-inverter needs separate dc
sources. The structure of separate dc sources is well suited for various renewable energy sources
such as fuel cell, photovoltaic, and biomass, etc. .
In summary, advantages and disadvantages of the cascaded inverter based multilevel voltage
source converter can be listed below

35
 C. Advantages and Disadvantages of CMLI

Advantages
o Modular in structure so packing and circuit layout is easier
o No clamping diodes present as in NPC
o No voltage balancing capacitors present in FC
o Low voltage switching devices required
o No EMI problem
o Less common mode voltage
o Less dv/dt
o Suitable for medium voltage , high power applications
o Separate DC sources eliminates the need of the voltage balancing circuits
o With the increase in the number of the level, the staircase waveform approximates to a
sinusoid
o It can work at reduced power level when one of its cell or SDCSs is damaged
o Soft switching techniques can be applied to CMI
o No transformer required as in multi-pulse inverters
o It makes Induction Motor more accessible / safer and open wiring possible for most of an
induction motor power system.
o The regulation of the DC buses is simple
o Modularity of control can be achieved. Unlike the diode clamped and capacitor
clamped inverter where the individual phase legs must be modulated by a central
controller, the full-bridge inverters of a cascaded structure can be modulated separately.
o Requires the least number of components among all multilevel converters to achieve
the same number of voltage levels.
Because of these advantages, the CMI converter has been used in this thesis for traction drive
application.

36
Disadvantages
o Communication between the full-bridges is required to achieve the synchronization of
reference and the carrier waveforms.
o Needs separate dc sources for real power conversions, and thus its applications are
Somewhat limited.

3.8.4. Comparison among Three Multilevel Inverters in Application Aspects

In high power system, the multilevel inverters can appropriately replace the exits system that
uses traditional multi-pulse converters without the need for transformers. All three multilevel
inverters can be used in reactive power compensation without having the voltage unbalance
problem [28]. In CMLI, the structure of separated dc sources is well suited for various renewable
energy sources such as fuel cell, photovoltaic, biomass, etc. This structure is, therefore, suited for
an ac power supply in vehicle system utilities. In the adjustable speed drive application, the
multilevel inverters can be used for a utility compatible adjustable speed drive (ASD) with the
input from the utility constant frequency ac source and the output to the variable frequency ac
load. The major differences, when using the same structure for ASDs and for back-to-back
interties, are the control design and the size of the capacitor. Because the ASD needs to operate at
different frequencies, the dc link capacitor needs to be large enough to avoid a large voltage
swing under transient state.
Table 3.3 compares the power component requirements per phase leg among the three multilevel
voltage source inverter mentioned above. Table 3.3 shows that the number of main switches and
main diodes, needed by the inverters to achieve the same number of voltage levels, is the same.
Clamping diodes do not need in flying-capacitor and cascaded-inverter configuration, while
balancing capacitors do not need in diode- clamp and cascaded-inverter configuration. Implicitly,
the multilevel converter using cascaded-inverters requires the least number of components.

37
Table 3.3: Comparison of power component requirements per phase leg among three
multilevel Inverters
Inverter Diode-Clamp Flying-capacitors Cascaded-inverters
Configuration
Main switching 2 2 2
Devices
Main diodes 2 2 2
Clamping diodes 0 0
DC bus capacitors /2
Balancing 0 /2 0
Capacitors

Another advantage of cascaded-inverter is circuit layout flexibility. Modularized circuit layout

and packaging is possible because each level has the same structure, and there are no extra
clamping diodes or voltage balancing capacitor. The number of output voltage levels can be
easily adjusted by adding or removing the full-bridge cells.

3.9. Control and Modulation Techniques of Multilevel Converters

In the power electronic converters, the electrical energy from one level of voltage, current or
frequency is converted into another using semiconductor based electronic switch. The essential
characteristic of these types of circuits is that the switches are operated only in one of the two
states - either fully ON or fully OFF - unlike other types of electrical circuits where the control
elements are operated in a linear active region.
As the power electronics industry has developed, various families of power electronic
converters have evolved, often linked by power level, switching devices, and topological
origins. Application areas of power converters get huge improvements in semiconductor
technology, which offer higher voltage and current ratings as well as better switching
characteristics. On the other hand, the main advantages of modern power electronic
converters, such as high efficiency, low weight, small dimensions, fast operation, and high
power densities.
The process of switching the electronic devices in a power electronic converter from one
state to another is called „modulation‟.
Each family of power converters has preferred modulation strategies associated with it that aims
at optimizing the circuit operation for the target criteria most appropriate for that family.

38
Parameters such as switching frequency, distortion, losses, harmonic generation, and speed of
response are typical of the issues which must be considered when developing modulation
strategies for a particular family of converters.

3.9.1. Classification of Modulation Strategies

It is generally accepted that the performance of an inverter, with any switching strategies, can be
related to the harmonic contents of its output voltage. Power electronics researchers have always
studied many novel control techniques to reduce harmonics in such waveforms. Up-to-date, there
are many techniques, which are applied to inverter topologies.
The modulation methods used in multilevel converters can be classified according to switching
frequency [31] as shown in Figure 3.8. Methods that work with high switching frequencies have
many commutations for the power semiconductors in one cycle of the fundamental output
voltage. The popular methods for high switching frequency methods are classic carrier based
sinusoidal PWM (SPWM) [32] and space vector PWM. A very popular method with high
switching frequency in industrial applications is the classic carrier-based sinusoidal PWM
(SPWM) that uses the phase-shifting technique to increase the effective switching frequency.
Therefore, the harmonics in the load voltage can be reduced [33].
Another interesting method is the SVM strategy, which has been used in three-level converters.
Methods that work with low switching frequencies generally perform one or two commutations
of the power semiconductors during one cycle of the output voltages to generate a staircase
waveform. Representatives of this family are the multilevel selective harmonic elimination [34]
based on elimination theory and the space-vector control (SVC) [35].

39
 Multilevel Modulation Control

Low Switching High Switching

Frequency control Frequency control

Space Vector Space Vector Sinusoidal

Selective Harmonic
Control PWM PWM
Elimination

Fig 3.8: Classification of multilevel modulation methods

3.9.2. Multilevel SPWM

Multilevel SPWM usually needs multiple carriers. Each DC source needs its own carrier. Several
multi-carrier techniques have been developed to reduce the distortion in multilevel converters,
based on the classical SPWM with triangular carriers. Some methods use carrier disposition and
others use phase shifting of multiple carrier signals [36].
This common SPWM method is the extension of bi-level SPWM. One reference signal is used to
compare to the carriers. This can be shown in Figure 3.9 (a). If the reference signal is higher than
the carrier, the corresponding converter cell outputs positive voltage; otherwise, the
corresponding converter cell outputs negative voltage. The output voltage of the converter is
shown in Figure 3.9 (b).

(a) (b)
Fig 3.9: Multi-carrier control (a) control signal and carrier signals; (b) output voltage

40
A number of cascaded cells in one phase with their carriers shifted by an angle and using the
same control voltage produce a load voltage with the smallest distortion [33]. A very common
practice in industrial applications for the multilevel converter is the injection of a third harmonic
in each cell to increase the output voltage [32]. Another advantageous feature of multilevel
SPWM is that the effective switching frequency of the load voltage is much higher than the
switching frequency of each cell, as determined by its carrier signal.
The advantage of the method is it is very simple. But it has two disadvantages. The first is the
method cannot completely eliminate the low order harmonics. Therefore the low order harmonics
cause loss and high filter requirements. The second is the high switching frequency causes high
switching loss and low efficiency.

3.9.3. Space Vector PWM Modulation

The space vector PWM modulation technique is popular for bi-level PWM converter control. It
can be extended to multilevel converters [37].
Space-vector PWM methods generally have the following advantages:
o Good utilization of DC-link voltage, low current ripple.
o Control is relatively easy; the hardware implementation can be easy by a digital signal
processor (DSP).
These advantages make it popular for converter control. But one disadvantage is as the number of
levels increases, redundant switching states and the complexity of selecting switching states
increase dramatically [31]. Another disadvantage is it cannot completely eliminate the low order
harmonics.
To conquer the computation difficulty, some authors have used decomposition of the five level
space-vector diagram into two three-level space-vector diagrams with a phase shift to minimize
ripples and simplify control [37].
Additionally, a simple space-vector selection method, which was called space vector control
method, is introduced for multilevel converter control without duty cycle computation of the
adjacent three vectors.

41
3.9.4. Space Vector Control
A conceptually different control method for multilevel converters, based on the space-vector
theory, has been introduced, which is called space vector control (SVC) [38].
The control strategy works with low switching frequencies but does not generate the mean value
of the desired load voltage in every switching interval, which is the principle of space-vector
PWM method. The key idea in SVC is to deliver to the load a voltage vector that minimizes the
space error or distance to the reference vector.
This method is simple and attractive for high number of levels. The advantages of SVC are the
computation is very easy and the switching frequency is very low, near the fundamental
switching frequency. But the disadvantage is as the number of levels decreases, the error in terms
of the generated vectors with respect to the reference will be higher [31].

3.9.5. Selective Harmonic Elimination

The popular selective harmonic elimination method is also called fundamental switching
frequency method which is based on the harmonic elimination theory developed by Patel et al
[40]. As shown in Figure 3.7, a multilevel converter can produce a quarter-wave symmetric
stepped voltage waveform synthesized by several DC voltages [2].
By applying Fourier series analysis, the output voltage can be expressed as

V(t) = ω
π

where s is the number of DC sources, and , are the level of DC voltages. The switching
angle must be satisfy the condition 0 π/2. However, if the switching
angles do not satisfy the condition, this method no longer exists. If = = = , this is called
equal DC voltages case. To minimize harmonic distortion and to achieve adjustable amplitude of
the fundamental component, up to s-1 harmonic contents can be removed from the voltage
waveform. In general, the most significant low-frequency harmonics are chosen for elimination
by properly selecting angles among different level converters, and high-frequency harmonic
components can be readily removed by using additional filter circuits. To keep the number of
eliminated harmonics at a constant level, all switching angles must satisfy the condition 0
π/2, or the total harmonic distortion (THD) increases dramatically.
Due to this reason, this modulation strategy basically provides a narrow range of modulation
index, which is one of its disadvantages [31].

42
In order to achieve a wide range of modulation indexes with minimized THD for the synthesized
waveforms, a generalized selective harmonic modulation method [34] was proposed, which is
called virtual stage PWM [1]. An output waveform is shown in Figure 3.10.
Vout

0 ωt
π/2 3π/2 2π
1

3
4

Fig 3.10: Output waveform of virtual stage PWM control

By applying Fourier series analysis, the output voltage can be expressed as

V(t)= π

ω (3.2)
Where s is the number of DC sources, and , are the level of DC voltages. In this
expression, the positive sign implies the rising edge, and the negative sign implies the falling
edge. Similar to the fundamental switching frequency method, the switching angle must be satisfy
the condition 0 π/2. However, if the switching angles do not satisfy the
condition, this method no longer exists.
Therefore, the modulation control problem is converted into a mathematic problem to solve the
following equations for a three-phase system. Here, m is modulation index.
cos cos cos ) cos =m
cos cos cos cos =0

cos cos cos cos = 0 (3.3)

The Virtual Stage PWM is a combination of Unipolar Programmed PWM and fundamental
frequency switching scheme [1]. The output waveform of Unipolar Programmed PWM is shown
in Figure3.11. When Unipolar Programmed PWM is employed on a multilevel converter,
typically one DC voltage is involved, where the switches connected to the DC voltage are

43
switched “on” and “off” several times per fundamental cycle. The switching pattern decides what
the output voltage waveform looks like.
When the multilevel fundamental switching method is used, all of the DC voltages are typically
involved, where all of the switches are turned “on” and “off” only once per fundamental cycle.
The multilevel fundamental switching method also refers to exactly one switching pattern.
For fundamental switching frequency method, the number of switching angles is equal to the
number of DC sources. However, for the Virtual Stage PWM method, the number of switching
angles is not equal to the number of DC voltages. For example, in Figure 3.10, only two DC
voltages are used, whereas there are four switching angles.
Bipolar Programmed PWM and Unipolar Programmed PWM could be used for modulation
indices too low for the applicability of the multilevel fundamental frequency switching method.
Virtual Stage PWM can also be used for low modulation indices. Virtual Stage PWM will
produce output waveforms with a lower THD most of the time [1]. Therefore, Virtual Stage
PWM provides another alternative to Bipolar Programmed PWM and Unipolar Programmed
PWM for low modulation index control.
Vout

Vdc

π/2 π 3π/2 2π
0 ωt
3
2
1

-Vdc

Fig 3.11: Unipolar switching output waveform

The major difficulty for selective harmonic elimination methods, including the fundamental
switching frequency method and the Virtual Stage PWM method, is to solve the transcendental
equations (3.3) for switching angles. Newton‟s method can be used to solve equations (3.3), but it
needs good initial guesses, and solutions are not guaranteed. Therefore, Newton‟s method is not
feasible to solving equations for large number of switching angles if good initial guesses are not
available.

44
 Chapter Four

4. Eleven Level Cascaded H-bridge Multilevel Inverter Modeling

4.1. Cascaded H–bridge Multilevel Inverter

Among three types of multilevel topologies discussed in chapter three, cascaded H-bridge
multilevel inverter type is considered for this work. In this configuration, five single phase H-
bridges are serially connected for single phase eleven-level inverter. In general the number of
bridges required for an m level inverter is (m-1)/2. All the switches in the inverter are turned on
only at the fundamental frequency and the voltage stress across the switches is only the
magnitude of dc source voltage. In the cascaded multilevel inverter all the voltage sources need to
be isolated from one another. Thus for single phase eleven-level inverter five dc sources are
needed. The switching stress can be reduced because of its better switch utilization. In the
proposed system, identical dc source voltages are used for the five H-bridges of the multi-level
inverter. The power circuit of single phase cascaded eleven level inverter is shown in Fig 4.1.
Each bridge module comprises of four IGBT‟s. Each bridge is energized by separate sources. The
cascaded multilevel inverter consists of a series of H-bridge (single phase, full bridge) inverter
units. As mentioned, the general function of this multilevel inverter is to synthesize a desired
voltage from several separate dc sources which is obtained from cascaded H-bridge multilevel
rectifier.
Each separate dc sources is connected to a single-phase full-bridge inverter. Each inverter level
can generate three different voltage outputs which are , 0, . The ac output of each levels
full bridge inverter is connected in series such that the synthesized voltage waveform is the sum
of all of the individual inverter outputs. The number of output phase voltage level in a cascaded
multilevel inverter is then 2s+1, where s is the number of dc sources. With enough levels and
appropriate switching algorithm the multilevel level results in an output voltage waveform which
is almost sinusoidal.

45
 S11 S13
A

V1

S14 S12

S21 S23

V2

S24 S22

S31 S33

V3

S34 S32

S41 S43

V4

S44 S42

S51 S53

N
V5

S54 S52

Fig 4.1: Power circuit of single phase cascaded eleven level inverter for traction drive
V0

V1+V2+V3+V4+V5

V1+V2+V3+V4

V1+V2+V3

V1+V2

V1
π/2 π 2π
0 ωt

Fig 4.2: Output voltage of single phase cascaded eleven-level inverter for traction drive

46
4.2. Working principle of Eleven Level Inverter
The model output voltage waveform of eleven-level cascaded multilevel inverter is shown in the
fig 4.2. The maximum output phase voltage is given as .
The steps to synthesize the eleven-level voltage waveforms are as follows.
1. For an output voltage level 0, no switch in the H-bridges is turned on.
2. For an output voltage level , turn on the switches , , , , , .
3. For an output voltage level , turn on the switches as mentioned in step 2 and

4. For an output voltage level turn on the switches as mentioned in step

3 and .
5. For an output voltage level turn on the switches as mentioned in
step 4 and .
6. For an output voltage level turn on the switches as
mentioned in step 5 and .
Where is the switches in the individual bridge. i is the number of bridge and j switch number
in the inverter.
Table 4.1 shows the voltage levels and their corresponding switch states in one quarter cycle of
output voltage. State condition 1 means the switch is on and 0 means the switch is off. Each
switch is turned on only once per cycle and therefore reduces switching losses.

47
Table 4.1: Output voltage levels and their switching states for eleven-level inverter

Switches

1 1 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 1 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0

4.3. Mathematical Model Equation of Eleven Level CHBMLI

4.3.1. Switching States of Inverter and Expression of Output Voltage

The output voltage waveform of cascaded multi level inverter has m levels. The problem under
consideration is to find appropriate switching angles namely so that the n - 1
non-triplen odd harmonics can be eliminated and control of the fundamental is also achieved. The
Fourier series expansion of the SHEPWM waveform is given by equation 4.1 assuming all the dc
sources are equal value. The Fourier expansion is used to find the expression for the output
voltage of the multi level inverter. The output voltage of the single phase cascaded eleven-level
inverter is shown in Fig 4. 2. There are six levels in the quarter wave of the output voltage

48
waveform including the level zero. As per the Fourier theorem the periodic output voltage V (ωt)
can be described by a constant term plus an infinite series of sine and cosine terms of frequency
nω, where n is an integer.
Therefore V (ωt) in general, can be expressed as
(4.1)

For periodic functions with odd quarter-wave symmetry, it can be shown that the equations
determining the Fourier coefficients simplify to the following expressions [43]:
(4.2)
for all n, (4.3)
for n even, (4.4)
and

ω Sin nω d ω for n odd (4.5)

When a periodic function possesses odd quarter-wave symmetry, the average value is zero. The
reason is due to the fact the function is odd. Also, odd symmetry results in all of the cosine
harmonics being zero. The half-wave symmetry of the periodic function forces the even sine
harmonics to be zero. Furthermore, in order to determine the amplitude of the odd sine
harmonics, one only needs to integrate over one-fourth of a fundamental period.
Since the output of the multilevel inverter is odd quarter-wave, (4.2) thru (4.5) can be used in
calculating the Fourier coefficients. As one can see from these equations, only the odd sine
harmonics can be nonzero.
Using the output of the multilevel inverter given in Figure 4.2, equation (4.5) then becomes

ω ω ω ω ω ω

ω ω

ω ω

49
Assuming all sources are of equal value , equation (4.6)
becomes

ω ω ω ω ω ω

ω ω ω ω

Where and are the switching angles and is the voltage of each dc source.
Performing the required integrations, (4.7) then becomes

ω ω ω
π π π π
π

ω ω
π

π
Finally, using the fact that when n is an odd integer and simplifying, (4.9)

becomes

Therefore, for any s and odd n, is given by

or

Finally, the Fourier series of the quarter-wave symmetric s H-bridge cell multilevel waveform is
written as follows

(ωt) =

50
Where
is the switching angles, which must satisfy the following condition

s is the number of H-bridge cells.

n is odd harmonic order and is the amplitude of dc voltages.

4.3.2. Determination of Switching Angles

Fourier series of the quarter-wave symmetric s H-bridge multilevel inverter output waveform is
written as given in equation (4.13) in which are the optimized switching angles, which must
satisfy the following condition.
.
The method to solve the optimized harmonic switching angles will be explained in this section.
From equation (4.1), the harmonic components in the waveform can be described as follows:
1. The amplitude of dc component equals zero.
2. The amplitude of all odd harmonic components including fundamental one, are given by
= . (4.13)

3. The amplitude of all even harmonics equal zero. Thus, only the odd harmonics in the
quarter-wave symmetric multilevel waveform need to be eliminated. The switching angles
of the waveform will be adjusted to get the lowest THD in the output voltage based on
IEEE-519 standards.
A set of nonlinear equation of single phase eleven-level inverter corresponding to equation (4.13)
can be given as follows:
 The nonlinear equation of the fundamental component:
= (4.14a)

 The nonlinear equations of the odd harmonic component:

= (4.14b)

= (4.14c)

= (4.14d)

= (4.14e)

51
For an output voltage waveform of five full-bridge cell circuit, five switching angles, namely
and , need to be known. It is implied that five equations are required to solve such
switching angles. Importantly, the expected solutions must be less than π/2.
From nonlinear equations system (4.14), equation (4.14a) is the nonlinear equation of the
fundamental component of an output voltage waveform, whereas (4.14b), (4.14c), (4.14d), and
(4,14e) are the nonlinear equation of the , the , the and the component of the
output voltage, respectively. On the right hand side of these equations, they are the amplitudes of
the components, which can be controlled. Basically, the lowest odd harmonic components should
be eliminated from a single-phase system. In a three phase system, because of 120 electrical
degree phase shift, the lowest non-triplen harmonic components need to be removed from phase
voltage. All even harmonics are not existed because of the symmetric characteristic of the
waveform. To control the amplitude of the fundamental component, (4.14a) will be considered.
The modulation index for the multilevel waveform is given as

M= (4.15)

where
h1 is the amplitude of the fundamental component.
s is the number of dc sources or H-bridge cells.
and is the voltages of the dc sources.
From (4.14a) and (4.15), the following equation can be obtained.
π
= (4.16)

From equation (4.16), varying the modulation index value can control the amplitude of the
fundamental component. The other s-1 nonlinear equations, which are the undesirable harmonic
components, can be eliminated. Usually, they are set to be zero. Therefore, in a single phase
multilevel inverter, the lowest s-1 odd harmonics can be removed, and in a three phase multilevel
inverter, the lowest s-1 non-triplen harmonics can be eliminated. The phenomenon is
mathematically proven as follows. Consider the third harmonic of the produced output.

= (4.17)

The voltages in the other two phases are shifted by 120 degrees each, and the equation is given as
follows.

52
 =

= (4.18)

and

= ) (4.19)

Hence

= =

In a three-phase system,

= =0

Similarliy,

= =0

Similarly, the other triplen harmonics cancel out each other. Hence, in a three phase system, one
has to deal only with the other odd number harmonics.
Table 4.2 shows the number of harmonic contents which can be eliminated as function of the
number of dc sources, s, in both single-phase and three-phase system.
Table 4.2: The number of eliminated harmonic components of SHEPWM technique.

The number of dc sources
The number of output
Voltage levels
The harmonics in the output
Phase voltage, which need
To be eliminated
Single-phase Three-phase
S s(per phase)
2s + 1 phase voltage 4s + 1 line to line voltage
levels
The lowest s -1 odd harmonics The lowest s -1 non-triplen
Odd harmonics

53
4.3.3. The Newton-Raphson Method
The set of equation in (4.14) are nonlinear in nature Newton Raphson method is used to solve
these equation [28], initially guesses are taken and then following steps are perform to calculate
the switching angles and iterations are perform till the harmonics content is reduce up to four
decimal places, which is suitable for implementation in a computer program.
Generally, the system of nonlinear equation in s variables can be represented as
=
=

= (4.20)
Then, (4.13) can be written in vector notation as
F =k (4.21)

Where
F=

k=
and F, , K are s x1 matrices
In a multivariable nonlinear system, a set of independent variables is formed in matrix format and
the statement of the algorithm of Newton‟s method can be shown as follows:
1) Guess a set of initial values for  with j =0

Suppose = (4.22)

2) Calculate the value of

F( )= (4.23)

3) Linearize equation (4.21) about

+ d =k (4.24)

54
Where

and
d =
4) Solve d from (4.24) by

d = INV (4.25)

Where INV is the inverse matrix of

5) As updated the initial values,

= + (4.26)
6) Repeat the process, equations (4.23) to (4.25), until is satisfied to the desired degree
of accuracy.

55
4.3.4. The Total Harmonic Distortion Calculation
The total harmonics distortion (THD) is mathematically given by

THD = (4.27)

Where
is the amplitudes of the fundamental component, whose frequency is and
is the amplitudes of the harmonics at frequency
From (4.11), the amplitude of the fundamental and harmonic components of the quarter-wave
symmetric multilevel waveform can be express as:

= (4.28)

From (4.27), let = and =

THD = (4.29)

Substitute equation (4.28) to (4.29),

THD (4.30)

By using (4.30), therefore, output voltage THD of multilevel inverter waveform can be
calculated. Theoretically, to get exact THD, infinite harmonics need to be calculated.
However, it is not possible in practice. Therefore, certain number of harmonics will be given. It
relies on how precise THD is needed. Usually, n = 63 is reasonably accepted.

56
4.4. Analysis of Switching Angles and Output THD of 11-Level CHBMLI by
Newton-Raphson Method
In this thesis, 7-level, 9-level and 11-level CMLIs are employed to generate ac output voltage
producing different magnitudes of THD at different values of modulation indices for comparison
purpose. The THD produced by 7-level and 9-level inverter is more than IEEE-519 standard [9]
for all values of m. The THD produced by 11-level inverter is satisfying this standard for
modulation index of one (not for all values), 11-level cascaded H-bridge multilevel inverter is
selected for induction motor drive of traction application at modulation index of one.
By using the Newton-Raphson method and MATLAB program, the switching angles of the
output voltage waveform and output THD are calculated. The output waveform of eleven-level
cascaded H-bridge multilevel inverter is shown in Fig 4.3. Since three phase induction motors are
used in traction system, three-phase system is assumed, and modulation index of output voltage,
m, is 1.
From the waveform shown in Fig 4.3, five unknowns, , , , and need to be known .
Because of a three-phase system, the lowest four odd harmonics, i.e the , , and
, should be eliminated.
V0

π/2 π 2π
ωt
4
1

2
3

Fig 4.3: Output voltage waveform of eleven-level inverter.

57
To control the fundamental amplitude and eliminate the harmonics, five nonlinear
equations can be set up as follows:

cos cos cos cos cos = (4.31a)

cos cos cos cos cos = 0 (4.31b)

cos cos cos cos cos = 0 (4.31c)
cos cos cos cos cos = 0 (4.31d)
cos cos cos cos cos = 0 (4.31e)
To solve the switching angles of nonlinear equations (4.31a) to (4.31e), the Newton‟s method
explained in 4.3.3 is applied, and the following matrices are implemented:
1) The switching angle matrix,

= (4.32a)
2) The nonlinear system matrix,

= (4.32b)

and

(4.32c)

3) The corresponding harmonic amplitude matrix

T= (4.32d)

Then, equations (4.31a) to (4.31e) can be rewritten in the following matrix format:
F =T (4.33)

58
By using matrices (4.32a) to (4.32d) and the Newton‟s method, the statement of algorithm, which
is suitable for implement in a computer program, is shown as follows:
1) Guess a set of initial values for  with j = 0
Assume = (4.34)
2) Calculate the value of
F = (4.35)
3) Linearize equation (4.33) about

+ =T (4.36)

and
d =
4) Solve d from equation (4.36), i.e.

d = INV (4.37)

Where INV is the inverse matrix of

5) As updated the initial values,

= + (4.38)
6) Repeat the process, equations (4.35) to (4.38), until is satisfied to the desired degree
of accuracy, and the solutions must satisfy the following condition:
, , , , < (4.39)

To implement this algorithm in a computer, MATLAB programming is used (see Appendix A).
After running the program, each iteration result is tabulated in table 4.3. In this case, the process
is repeated until all elements in matrix are less than 0.0001. The final solutions, in degree, are:
7.8649, 19.3815, 29.6656, 47.7057, 63.2464 (4.40)
Because these switching angles satisfy the condition (4.39), they are the correct solutions. By
using these switching angles in the waveform, the , , and harmonics will be
eliminated with the modulation index equal to 1. As the results, the first harmonics content,
which shows in the waveform, is the harmonic.

59
Table 4.3: content of matric , , and from MATLAB program by using the Newton‟s
method

Iteration index
(degree)
j =0 5 4.2165 1.4662
13 -0.0972 7.8433
25 0.8855 4.7000
40 -0.3869 6.3987
55 0.3166 10.5566

j =1 6.4662 3.9270 1.3987

20.8433 -0.0001 -1.4618
29.7000 -0.0003 -0.0344
46.3987 0.0011 1.3070
65.5566 0.0008 -2.3102
j=2 7.8649 3.9270 0.0000
19.3815 -0.0001 0.0000
29.6656 0.0000 0.0000
47.7057 0.0000 0.0000
63.2464 -0.0000 0.0000
j =3 7.8649 3.9270 0.0000
19.3815 0 0.0000
29.6656 0 0.0000
47.7057 0 0.0000
63.2464 0 0.0000

Using the same procedure, the switching angles of 7-level, 9-level, and 11-level with different
modulation index, are shown in Table 4.4 to 4.6, respectively.
Table 4.4: The switching angles of 7-level cascaded inverter.

Modulation
Index, M
1 11.6817 31.1783 58.5774
0.95 13.8210 37.2095 61.9509
0.90 17.5104 43.0523 64.1395
0.85 22.7654 49.3798 64.5562
0.80 29.2355 54.4383 64.4844
0.75 34.8935 54.4622 68.5500
0.70 38.3413 53.9297 73.9648
0.65 39.3876 55.5215 78.8979
0.60 39.4298 58.5839 83.1042

60
Table 4.5: The switching angles of 9-level cascaded inverter.

Modulation
Index, M
1 10.0154 22.1424 40.7521 61.7681
0.95 11.5499 27.3939 46.725 64.442
0.90 12.4367 34.5875 48.8091 68.8855
0.85 19.0991 39.7221 55.5860 66.9784
0.80 24.6998 45.5307 57.0398 68.8886
0.75 30.0144 49.2484 57.1585 72.8307
0.70 36.1183 47.8768 61.0723 76.2975
0.65 34.4790 51.4007 62.9388 83.8302
0.60 37.0314 51.023 67.1599 86.0159

Table 4.6: The switching angles of 11-level inverter.

Modulation
Index, M
1 7.8598 19.3725 29.6522 47.68 63.2122
0.95 13.3907 20.9886 36.299 58.915 59.3507
0.90 7.6592 27.5706 40.7891 52.5598 73.0391
0.85 17.7312 32.7053 50.0119 57.8089 68.37
0.80 22.3419 39.2785 52.6866 59.3192 70.9645
0.75 28.4564 45.3922 50.9961 63.5194 73.2291
0.70 34.3709 44.6208 54.1495 65.3723 77.917
0.65 35.7274 44.883 56.8276 68.0465 83.6168
0.60 35.3424 46.9528 58.5799 72.6121 87.8373

The phase and line-to-line voltage THD are calculated by using the following formula

THD = (4.41)

Where
s is the number of H-bridge inverters per phase
n is the harmonic order
, ,… are the calculated switching angles
In case of line voltage THD calculation using equation (4.41), all triplen harmonic components
are set to zero. To get a precise result, the harmonic components up to the are used to
calculate the voltage THD. From the calculated switching angles in table 4.4 to 4.6, the line and

61
phase voltage THD of 7-level, 9-level, and 11-level inverter as function of the modulation index,
are shown in table 4.7 to 4.9.

Table 4.7: Voltage THD of 7- level cascaded inverter

7 level(s=3)
Modulation index M THDphase(%) THDline(%)
1 12.2146 7.8950
0.95 15.4137 8.4329
0.90 20.4685 12.2248
0.85 27.9162 9.2206
0.80 36.7156 10.8829
0.75 42.0658 11.1212
0.70 45.2950 12.4183
0.64 46.8596 12.1812
0.60 47.3293 12.9483

Table 4.8: Voltage THD of 9- level cascaded inverter

9 level(s=4)
Modulation index M THDphase(%) THDline(%)
1 9.3633 6.4238
0.95 12.7828 7.8288
0.90 17.0568 8.6673
0.85 25.3925 8.2808
0.80 32.7299 7.3595
0.75 38.6554 9.6889
0.70 43.5572 8.6434
0.64 42.6945 9.889
0.60 44.6478 9.4710

62
Table 4.9: Voltage THD of 11- level cascaded inverter

11 level(s=5)
Modulation index M THDphase(%) THDline(%)
1 7.5873 5.0623
0.95 15.4734 5.9535
0.90 13.9569 6.5977
0.85 24.7241 4.9028
0.80 31.4369 7.1752
0.75 38.2359 6.6307
0.70 42.6908 5.8025
0.64 43.4610 7.2716
0.60 43.2388 7.2666

The line and phase voltage THD of 7-level, 9-level, and 11-level inverter as function of the
modulation index, are shown in Fig 4.4 to 4.6, respectively.

Voltage THD Vs. Modulation Index of 7-level inverter

50
45
40
35
THD(%)

30
25
20 Line Voltage
15 Phase voltage
10
5
0
1 0.95 0.9 0.85 0.8 0.75 0.7 0.64 0.6
Modulation Index

Fig 4.4: Voltage THD as function of the modulation index of 7-level cascaded H-bridge
Inverter

63
 Voltage THD Vs. Modulation Index of 9-level inverter
50
45
40
35
THD(%)

30
25
20 Line Voltage
15 Phase voltage
10
5
0
1 0.95 0.9 0.85 0.8 0.75 0.7 0.64 0.6
Modulation Index

Fig 4.5: Voltage THD as function of the modulation index of 9-level cascaded H-bridge
Inverter

Voltage THD Vs. Modulation Index of 11-level inverter

50
45
40
35
THD(%)

30
25
20 Line Voltage
15 Phase voltage
10
5
0
1 0.95 0.9 0.85 0.8 0.75 0.7 0.64 0.6
Modulation Index

Fig 4.6: Voltage THD as function of the modulation index of 11-level cascaded H-bridge
Inverter

64
From the figure 4.4 to 4.6, the phase voltage THD increases dramatically, when the modulation
index decreases, whereas, the line voltage THD increases slightly, when the modulation index
decreases. At the same modulation index, the line voltage THD is much less than phase voltage
THD. Similarly, the line voltage THD decreases, when the number of H-bridge inverter per phase
s, increases. Therefore, the line voltage THD can be reduced by increasing the number of
full-bridge inverter in the multilevel inverter circuit.
From figure 4.6, without any filter circuit, the line voltage of 11-level SHEPWM THD is 5.0623
percent with modulation index of 1. In practice, filter circuits may be applied; therefore, the line
voltage THD can meet IEEE-519 standard [9] without any difficulties.

65
 Chapter Five

5. Simulation and Result Discussion

In order to validate the analytical result, three-phase cascaded eleven level inverter using SHE
PWM technique is simulated with the use of MATLAB/SIMULINK. For three-phase cascaded
eleven level inverter fifteen H-bridges are needed for simulation. IGBTs are chosen as switching
device for simulation, since it has lesser losses, better controllability, superior performance, high
reliability and modular design than the other power semiconductor devices. Figure 5.1 shows the
simulation circuit for eleven level inverter using SHE PWM technique. For each of the H-bridges
in the CMLI, 76V dc source is used. The load is considered as pure resistance 50 Ω. In this
simulation 0.02sec is taken as one period. Diagonally IGBTs are in operation in each level for
positive and negative half cycle. Here phase delays for 11- level are taken as 0.00043665,
0.00107625, 0.0016473, 0.002648 and 0.00351178sec which are five switching angles calculated
using NR algorithm.
Figure 5.2 shows the gating signals generated in simulink for the power circuit shown in Fig 5.1.
The simulated phase and line voltage waveforms for 11-level CMLI for the modulation index
equal to 1.00 are shown in Figs 5.3 and Figs 5.4 respectively. From the powergui block FFT
analysis is done in both cases, so that THD can be calculated as shown in fig 5.3 (b) and fig 5.4
(b) respectively. Again there is a close agreement between analytical and simulated values of
output line voltage THD and these are 5.0623% and 6.37% respectively. It is to be noted that in
Fig 5.3 (b), THD shown is 8.34%, the reason for this is that the THD shown is for phase voltage
which includes triplen harmonic components while analytical value is for line voltage which
excludes triplen harmonic components.

66
 Discrete,
Ts = 5e-005 s.

C
powergui PgA11 PgA13

g
C

C
SA11 SA13
PgB11
SB11
PgB13 A A

g
C

C
PgC11 PgC13

C
E
SB13 SC11

E
SC13 B B

E
C C
PgA14 Three-Phase
DCA1 PgB14 PgC14 Series RLC Branch
PgA12 DCB1 PgB12
DCC1

C
PgC12

g
C

C
SA12

C
SA14 SB12

g
C
SB14

C
E
SC12
E

E
SC14

E
E
+
v
-
Voltage Measurement2
Scope
g

PgA21 PgA23
g

g
C

C
SA21 PgB21 PgB23

g
C
SA23 SB21

C
SB23 PgC21 PgC23

C
E

E SC21

E
SC23

E
PgA24
PgB24
DCA2 DCB2
PgC24
PgA22
PgB22 DCC2 PgC22
g

C
g

g
C

C
SA22

C
SA24 SB22

g
C
SB24

C
E

SC22
E

E
SC24

E
E
g

PgA31 PgA33
g

g
C

C
SA31 PgB31 PgB33

g
C
SA33 SB31

C
SB33 PgC33

C
E

PgC31 SC31
E

SC33

E
PgB34
PgA32 PgB32
PgA34
g

C
g

g
C

DCA3 SA34 SA32 PgC34 PgC32

g

DCB3 SB34 SB32

g
C
g

C
E

DCC3SC34 SC32
E

E
E

E
E
PgA41 PgA43
g

g
C

SA41 PgB41 PGB43

g
C

SA43

C
SB41 SB43 PgC41 PgC43

C
E

SC41
E

SC43
E

E
PgA44 PgB44
DCA4 PgA42 DCB4
PgB42 PgC44
PgC42
g

DCC4
g

g
C

SA42
g

SA44 SB42

g
C
SB44
g

C
E

SC42
E

SC44
E

E
E

PgA51
g

PgA53
g

SA51 PgB51
g

SA53 PgB53
g

SB51 PgC51
g
C
E

SB53 PgC53
g

C
E

SC51
E

SC53
E

PgA54
DCA5 PgA52
PgB54
DCB5 PgC54
g

PgB52
g

SA52 DCC5
g

SA54 PgC52
g

SB52
g
C
E

SB54
g

C
E

SC52
E

SC54
E

E
E

Figure 5.1: Simulation circuit for eleven level inverter using SHE PWM technique

67
 Signal(Magn) Gating pulse for Switch S11,S12,S22,S32,S42,S52
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Positive Voltage Gating Pulse Pattern

Signal(Magn.) Gating Pulse for Switch S21

1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Signal(Magn.) Gating Pulse for Switch S31
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Signal(Magn.) Gating Pulse for Switch S41
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Signal(Magn.) Gating Pulse for Switch S51
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Time(sec)

Signal(Magn) Gating pulse for Switch S13,S14,S24,S34,S44,S54

1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Nagative Voltage Gating Pulse Pattern

Signal(Magn.) Gating Pulse for Switch S23

1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Signal(Magn.) Gating Pulse for Switch S33
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Signal(Magn.) Gating Pulse for Switch S43
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Signal(Magn.) Gating Pulse for Switch S53
1

0.5

0
0 0.01 0.02 0.03 0.04 0.05 0.06
Time(sec)

Fig 5.2: Pattern of gating signals

68
 Line Voltage(Vac)
400

300

200
Phase Voltage Van(V)

100

-100

-200

-300

-400
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Time(sec)

(a)

Selected signal: 8 cycles. FFT window (in red): 2 cycles

200

-200

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16

Time (s)

Fundamental (50Hz) = 380.5 , THD= 8.34%

2.5
Mag (% of Fundamental)

1.5

0.5

0
0 1 2 3 4 5 6 7 8
Harmonic order

(b)
Fig 5.3: (a) Simulated phase voltage and (b) THD analysis for 11-level CMLI at m=1.00

69
 800

600

400
Line Voltage Vab(V)

200

-200

-400

-600

-800
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Time(sec)

(a)

Selected signal: 8 cycles. FFT window (in red): 2 cycles

500

-500

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16

Time (s)

Fundamental (50Hz) = 658.6 , THD= 6.37%

0.3
Mag (% of Fundamental)

0.25

0.2

0.15

0.1

0.05

0
0 1 2 3 4 5 6 7 8
Harmonic order

(b)
Figure 5.4: (a) Simulated line voltage and (b) THD analysis for 11-level CMLI at m = 1.00

70
 5.1. Simulation of Three phase induction motor driven by 11 level CHBMLI
At this study a three phase squirrel cage asynchronous machine modeled in a selectable dq
reference frame is selected from the library of MATLAB/Sims Power which is used as a load for
cascade 11-level multilevel inverter. Rotor current, stator Current and Rotor Speed are used for
comparing the effect of harmonic with ideal AC source fed induction motor.
Figure 5.5 to 5.7 shows the outputs of an ideal case with ideal AC source. The specification of
induction motor used in this simulation is shown in appendix B

30

20
Rotor Current (A)

10

-10

-20

-30
0 0.05 0.1 0.15 0.2 0.25
Time(sec)

Fig 5.5: Rotor current of induction motor using an ideal ac source

30

20

10
Stator Current (A)

-10

-20

-30
0 0.05 0.1 0.15 0.2 0.25
Time(sec)

Fig 5.6: Stator current of induction motor using an ideal ac source

71
 160

140
Rotor speed (rpm)

120

100

80

60

40

20

-20
0 0.05 0.1 0.15 0.2 0.25
Time(sec)

Fig 5.7: Rotor speed of induction motor using of ideal ac source

In this thesis the induction motor is fed with a three phase cascaded H-bridge 11-level inverter at
380 volt AC voltage source to compare the effect of harmonic with ideal AC source fed induction
motor simulated above. Fig 5.8 to 5.10 shows the rotor current, stator current and rotor speed of
induction motor in the case of feeding induction motor with cascaded 11-level inverter. It can be
observed that there are very few notches in the rotor and stator current waveforms compared to
ideal ac source. In Fig 5.8, the magnitude of rotor current is slightly decreased compared to ideal
ac source due to the harmonics of the output voltage, specifically the 17 th harmonic.
The open-loop speed response of the motor driven by the proposed converter has been shown in
Fig 5.10. In steady state, a small-speed ripple is introduced.

72
 20

15

10

5
Rotor Current(A)

-5

-10

-15

-20

-25
0 0.05 0.1 0.15 0.2 0.25
Time(sec)

Fig 5.8: Rotor current in case of feeding with cascaded 11-level inverter

25

20

15
Stator Current (A)

10

-5

-10

-15

-20

-25
0 0.05 0.1 0.15 0.2 0.25
Time(sec)

Fig 5.9: Stator current in case of feeding with cascaded 11-level inverter

73
 180

160

140
Rotor speed(rpm)

120

100

80

60

40

20

0
0 0.05 0.1 0.15 0.2 0.25
Time(sec)

Fig5.10: Rotor speed in case of feeding with cascaded 11-level inverter

74
 Chapter Six

6. Conclusion and Future Work

6.1. Conclusion
The multilevel inverter topology can overcome some of the limitations of the standard two-level
inverter. Output voltage and power increase with number of levels. Harmonics decrease as the
number of levels increase discussed in Chapter 3 and 4. In addition, increasing output voltage
does not require an increase in voltage rating of individual force commutated devices. In the
thesis, several multilevel voltage source inverters and their modulation topologies are introduced.
The current trend of modulation control for multilevel converters is to output high quality power
with high efficiency. For this reason, popular traditional PWM methods and space vector PWM
methods are not the best methods for multilevel converter control due to their high switching
frequency. The selective harmonic elimination method has emerged as a promising modulation
control method for multilevel converters.
For a cascaded H-bridges multilevel inverter, the switching angles can be selected such that the
output voltage THD is less than 5% as per IEEE-519 standard. It has been found that the eleven
level CMLI satisfies this limit at modulation index of one while seven and nine level CMLI
violates this limit at all modulation index value. Where adjustable speed drives are required,
modulation index has to change. Since the train is operated in maximum voltage rate for long
period of time at modulation index of one, it satisfy IEE-519 standard limit. But at starting and
stopping time the train is operated in minimum voltage rate for short period of time at modulation
index of less than one. At this modulation index output voltage THD is violate the standard limit.
Line voltage THD can be reduced by increasing the number of levels, but by considering circuit
complexity and cost, eleven level CMLI inverter at modulation index of one is selected for
electrical railway train application.
The switching angles for cascade multilevel inverters of 7, 9 and 11-level have been computed
for analysis of total harmonic distortions produced in output voltage and complexity in
computation of these angles. It has been found that complexity in computation of switching
angles increases with increase in number of levels. On other part, the THD in output voltage

75
decrease and output voltage increase with increase in number of levels. By using three-phase 11-
level CMLI, 5th,7th , 11th , and 13th order harmonics can be eliminated.
Analytical results are validated with simulation results for 11-level CMLI at modulation index of
one. The multilevel inverter improves output voltage; reduce THD and voltage stresses on
semiconductor switches which can be verified from simulation results. The Cascaded eleven level
inverter fed induction motor drive is simulated using the blocks of Simulink. The simulation
results of rotor current, stator current and rotor speed are presented. The results of 11-level CMLI
AC source drive system are compared with the results of ideal AC source drive system. At Steady
State, Performance of 11-level CMLI at modulation index of one driven induction motor is
similar to the ideal AC source driven induction motor. 11-level CMLI can be used in traction
drive system where adjustable speed drives are required to produce output voltage with reduced
harmonic content.
The cascaded eleven level converter system modeled in this thesis can be used in traction drive
consisting of six induction motors for stepping down the catenary voltage to the rated voltage of
the induction motors. Thus, this model eliminates the necessity of the transformer in railway
traction and hence lowers the cost and floor space and increases the efficiency of the traction
drive.

6.2. Future Work

Although this thesis has covered most of the interesting issues and challenges of the Cascaded
multi-level inverter induction motor drives, additional work has been left for future research.
The following can be considered for future work on the subject for traction drive application:
o Unified Approach switching scheme. The Unified Approach switching scheme makes use
of Unipolar Programmed PWM, Virtual Stage PWM, and multilevel fundamental
switching.
o Practical implementation of three-phase 11-level CMLI drive for electric railway traction
application in laboratory, to test the result for real world application can be done based on
the proposed model.
o Direct Torque Control strategy that can be employed in the transformerless inverter
traction drive.
o Cost and reliability analysis and comparison between transformerless multistage inverter
and conventional inverter equipped with transformer.

76
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Appendices

Appendix A.
An m-file used to solve the switching angles of selective harmonic elimination pulse width
modulation (SHEPWM) is presented as follows:
%Solve switching angle of three phase 11-level SHEPWM by using the Newton-
Raphson method
clear all; close all;
E=5; %The number of dc sources
Mstart= 1; %The initial modulation index
M=Mstart*E;
Mrange=4; %Range of calculation results
p1=5*pi/180; p2=13*pi/180; p3=25*pi/180; p4=40*pi/180; p5=55*pi/180;
%Guess initial value of switching angles
p=[p1 p2 p3 p4 p5]'; %The switching angle matrix

for j=1:Mrange
t=[M*pi/4 0 0 0 0 ]'; %The corresponding harmonic amplitude matrix
df=1; i=1;
while abs(df) > 1e-4 & i < 5 %i=5 %Degree of accuracy condition
p1=p(1,:); p2=p(2,:); p3=p(3,:); p4=p(4,:); p5=p(5,:);
f=[cos(p1)+cos(p2)+cos(p3)+cos(p4)+cos(p5);
cos(5*p1)+cos(5*p2)+cos(5*p3)+cos(5*p4)+cos(5*p5);
cos(7*p1)+cos(7*p2)+cos(7*p3)+cos(7*p4)+cos(7*p5);
cos(11*p1)+cos(11*p2)+cos(11*p3)+cos(11*p4)+cos(11*p5)
cos(13*p1)+cos(13*p2)+cos(13*p3)+cos(13*p4)+cos(13*p5)]; % The nonlinear
system matrix
delf=[-sin(p1) -sin(p2) -sin(p3) -sin(p4) -sin(p5);
-5*sin(5*p1) -5*sin(5*p2) -5*sin(5*p3) -5*sin(5*p4) -5*sin(5*p5);
-7*sin(7*p1) -7*sin(7*p2) -7*sin(7*p3) -7*sin(7*p4) -7*sin(7*p5);
-11*sin(11*p1) -11*sin(11*p2) -11*sin(11*p3) -11*sin(11*p4) –
11*sin(11*p5);
-13*sin(13*p1) -13*sin(13*p2) -13*sin(13*p3) -13*sin(13*p4) –
13*sin(13*p5)];% The differential matrix
df=inv(delf)*(t-f); % Calculate solution error
p=p+df; % Update the solutions.
i=i+1;
end
end

Appendix B.
The specification and the parameters of the induction motor is: Power = 5HP, line-line
voltage=380V, frequency = 50Hz, Stator resistance R= 8Ω, leakage stator inductance Lls =0.032
H, mutual inductance Lm = 0.45H,Rotor resistance R = 6Ω , leakage rotor inductance Llr =
0.032 H, moment of inertia J=0.16 kg-m, frication factor B=0.036 kg-m/s, torque =12 Nm..

81