STL16N65M2

N-channel 650 V, 0.325 Ω typ., 7.5 A MDmesh M2

Power MOSFET in a PowerFLAT™ 5x6 HV package
Datasheet − production data

Features
Order code VDS @ TJmax RDS(on) max ID
STL16N65M2 710 V 0.395 Ω 7.5 A

• Extremely low gate charge

1 • Excellent output capacitance (Coss) profile
2
3
4 • 100% avalanche tested
• Zener-protected
PowerFLAT™ 5x6 HV
Applications
• Switching applications
Figure 1. Internal schematic diagram
Description
D(5, 6, 7, 8)
8 7 6 5 This device is an N-channel Power MOSFET
developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical
structure, the device exhibits low on-resistance
and optimized switching characteristics, rendering
G(4)
it suitable for the most demanding high efficiency
converters.

1 2 3 4
Top View
S(1, 2, 3)
AM15540v2

Table 1. Device summary

Order codes Marking Package Packaging

STL16N65M2 16N65M2 PowerFLAT™ 5x6 HV Tape and reel

October 2014 DocID027128 Rev 1 1/16

This is information on a product in full production. www.st.com
Contents STL16N65M2

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuits .............................................. 8

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/16 DocID027128 Rev 1

STL16N65M2 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ± 25 V

ID Drain current (continuous) at TC = 25 °C 7.5 A
ID Drain current (continuous) at TC = 100 °C 4.7 A
IDM (1) Drain current (pulsed) 30 A
PTOT Total dissipation at TC = 25 °C 56 W
dv/dt (2)
Peak diode recovery voltage slope 15 V/ns
dv/dt (3)
MOSFET dv/dt ruggedness 50 V/ns
Tstg Storage temperature
- 55 to 150 °C
Tj Max. operating junction temperature
1. Pulse width limited by safe operating area.
2. ISD ≤ 7.5 A, di/dt ≤ 400 A/µs; V DS peak < V(BR)DSS, VDD=400 V.
3. VDS ≤ 520 V

Table 3. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case max 2.23 °C/W

Rthj-pcb Thermal resistance junction-pcb max(1) 59 °C/W
1. When mounted on 1 inch² FR-4, 2 Oz copper board

Table 4. Avalanche characteristics

Symbol Parameter Value Unit

Avalanche current, repetitive or not

IAR 1.5 A
repetitive (pulse width limited by Tjmax)
Single pulse avalanche energy (starting
EAS 115 mJ
Tj=25°C, ID= IAR; VDD=50)

DocID027128 Rev 1 3/16

16
Electrical characteristics STL16N65M2

2 Electrical characteristics

(TC = 25 °C unless otherwise specified)

Table 5. On /off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

Drain-source
V(BR)DSS VGS = 0, ID = 1 mA 650 V
breakdown voltage
VGS = 0, VDS = 650 V 1 µA
Zero gate voltage
IDSS VGS = 0, VDS = 650 V,
drain current 100 µA
TC=125 °C
Gate-body leakage
IGSS VDS = 0, VGS = ± 25 V ±10 µA
current
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V
Static drain-source
RDS(on) VGS = 10 V, ID = 3.5 A 0.325 0.395 Ω
on-resistance

Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance - 718 - pF

Coss Output capacitance VGS = 0, VDS = 100 V, - 32 - pF
f = 1 MHz
Reverse transfer
Crss - 1.1 - pF
capacitance
Equivalent output
Coss eq.(1) VGS = 0, VDS = 0 to 520 V - 189 - pF
capacitance
Intrinsic gate
RG f = 1 MHz open drain - 5.2 - Ω
resistance
Qg Total gate charge - 19.5 - nC
VDD = 520 V, ID = 11 A,
Qgs Gate-source charge - 4 - nC
VGS = 10 V (see Figure 15)
Qgd Gate-drain charge - 8.3 - nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS

4/16 DocID027128 Rev 1

STL16N65M2 Electrical characteristics

Table 7. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time - 11.3 - ns

tr Rise time VDD = 325 V, ID = 5.5 A, - 8.2 - ns
RG = 4.7 Ω, VGS = 10 V
td(off) Turn-off delay time (see Figure 14 and 19) - 36 - ns
tf Fall time - 11.3 - ns

Table 8. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 7.5 A

ISDM (1)
Source-drain current (pulsed) - 30 A
VSD (2)
Forward on voltage VGS = 0, ISD = 11 A - 1.6 V
trr Reverse recovery time - 342 ns
ISD = 11 A, di/dt = 100 A/µs
Qrr Reverse recovery charge - 3.5 µC
VDD = 60 V (see Figure 16)
IRRM Reverse recovery current - 20.4 A
trr Reverse recovery time - 458 ns
ISD = 11 A, di/dt = 100 A/µs
Qrr Reverse recovery charge VDD = 60 V, Tj=150 °C - 4.6 µC
(see Figure 16)
IRRM Reverse recovery current - 20.5 A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

DocID027128 Rev 1 5/16

16
Electrical characteristics STL16N65M2

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance
*,3')65 ZthPowerFlat_5x6_19
,' K
$ δ=0.5

0.2
LV
 HD 
DU  RQ —V 0.1
LV '6 10 -1 0.05
WK 5
 LQ D[ 0.02
Q P
WLR \ —V
UD GE 0.01
SH WH
2 LPL
 / PV

PV 10 -2 Single pulse


7M ƒ&
7F ƒ&
6LQJOHSXOVH

 10 -3
    9'69 10-6 10-5 10-4 10-3 10 -2 10 -1 100 tp(s)

Figure 4. Output characteristics Figure 5. Transfer characteristics

*,3')65 *,3')65
,' ,'
$ 9*6 9 $
 
9
 
9'6 9
 
9
 

 

 
9
 
    9'69      9*69

Figure 6. Normalized gate threshold voltage vs. Figure 7. Normalized V(BR)DSS vs. temperature
temperature
GIPD180920141442FSR GIPD180920141448FSR
VGS(th) V(BR)DSS
(norm) (norm)
ID = 250 µA
1.1 1.08
ID= 1mA

1.0 1.04

0.9 1.00

0.8 0.96

0.7 0.92

0.6 0.88
-75 -25 25 75 125 Tj(°C) -75 -25 25 75 125 Tj(°C)

6/16 DocID027128 Rev 1

STL16N65M2 Electrical characteristics

Figure 8. Static drain-source on-resistance Figure 9. Normalized on-resistance vs.

temperature
*,3')65 GIPD180920141459FSR
5'6RQ RDS(on)
ȍ 9*6 9 (norm)

 2.2
VGS= 10V

 1.8

 1.4

 1

 0.6

 0.2
       ,'$ -75 -25 25 75 125 Tj(°C)

Figure 10. Gate charge vs. gate-source voltage Figure 11. Capacitance variations
*,3')65 *,3')65
9*6 9'6 9 &
9 S)
9'6
9'' 9
 ,' $  &LVV


 

&RVV
 

 
&UVV

 

  
      4JQ&     9'69

Figure 12. Output capacitance stored energy Figure 13. Source-drain diode forward
characteristics
*,3')65 *,3')65
( 96'
—- 9
 7M ƒ&




 7M ƒ&


 7M ƒ&





 
       9'69       ,6'$

DocID027128 Rev 1 7/16

16
Test circuits STL16N65M2

3 Test circuits

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit
resistive load
VDD

12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. μF 2.7kΩ VG

PW
47kΩ

PW 1kΩ
AM01468v1 AM01469v1

Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit
switching and diode recovery times

L
A A A
D
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
S B 3.3 1000
B B μF μF
25 Ω VDD ID
D

RG S
Vi D.U.T.

Pw
AM01470v1 AM01471v1

Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform
9%5'66 ton toff
tr tdoff tf
9' tdon

90% 90%
,'0
10%
,' 10% VDS
0

9'' 9'' 90%

VGS

$0Y 0 10% AM01473v1

8/16 DocID027128 Rev 1

STL16N65M2 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

DocID027128 Rev 1 9/16

16
Package mechanical data STL16N65M2

Figure 20. PowerFLAT™ 5x6 HV drawing

8368143_Rev_B

10/16 DocID027128 Rev 1

STL16N65M2 Package mechanical data

Table 9. PowerFLAT™ 5x6 HV mechanical data

mm
Dim.
Min. Typ. Max.

A 0.80 1.00
A1 0.02 0.05
A2 0.25
b 0.30 0.50
D 5.00 5.20 5.40
E 5.95 6.15 6.35
D2 4.30 4.40 4.50
E2 3.10 3.20 3.30
e 1.27
L 0.50 0.55 0.60
K 1.90 2.00 2.10

DocID027128 Rev 1 11/16

16
Package mechanical data STL16N65M2

Figure 21. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm)

8368143_Rev_B_footprint

12/16 DocID027128 Rev 1

STL16N65M2 Packaging mechanical data

5 Packaging mechanical data

Figure 22. PowerFLAT™ 5x6 tape(a)

P2 P0
T 2.0±0.1 (I) 4.0±0.1 (II)
(0.30 ±0.05)
Do E1
Ø1.55±0.05 1.75±0.1
Y

20
0.
D1

EF

F(5.50±0.1)(III)
R

W(12.00±0.3)
Ø1.5 MIN.
Bo (5.30±0.1)

C
L

REF
.R0
.50

Y
P1(8.00±0.1) Ao(6.30±0.1)
Ko (1.20±0.1)

SECTION Y-Y

(I) Measured from centerline of sprocket hole Base and bulk quantity 3000 pcs
to centerline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ± 0.20 .
(III) Measured from centerline of sprocket
hole to centerline of pocket.
8234350_Tape_rev_C

Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape.

Pin 1
identification

a. All dimensions are in millimeters.

DocID027128 Rev 1 13/16

16
Packaging mechanical data STL16N65M2

Figure 24. PowerFLAT™ 5x6 reel

R0.60

W3
PART NO. 11.9/15.4
1.90
2.50

W2
18.4 (max)

R25.00

FOR HANDLING ELECTROSTATIC

OBSERVE PRECAUTIONS

SENSITIVE DEVICES
ATTENTION
ØN A
178(±2.0) 330 (+0/-4.0)
4.00

2.50

ESD LOGO

77
W1
12.4 (+2/-0)
PS
06 ØA

128

R1.10
2.20

Ø21.2

All dimensions are in millimeters

13.00

CORE DETAIL

8234350_Reel_rev_C

14/16 DocID027128 Rev 1

STL16N65M2 Revision history

6 Revision history

Table 10. Document revision history

Date Revision Changes

31-Oct-2014 1 First release.

DocID027128 Rev 1 15/16

16
 STL16N65M2

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2014 STMicroelectronics – All rights reserved

16/16 DocID027128 Rev 1