Arithmetic Circuits

Arithmetic Circuits
Digital
g Logic
g Analysis
y & Design
g
Poras T. Balsara & Dinesh K. Bhatia

Department of Electrical Engineering
University of Texas at Dallas
Outline
 Review - Positional Number Systems
 Radix Conversion
 Representation of Negative Numbers
 Addition and Subtraction of Signed Numbers
 Adders and Subtracters
 Multipliers
 Combinational Shifter
 C
Comparatort
 Floating Point Representation
 Floating Point Addition
 Floating Point Multiplication
© ptb/dkb (November 19, 2010) Arithmetic Circuits 2
1
Positional Number System – a review
 Value of a number is determined by a weighted sum of its digits
 Weighting is implicit and is determined for each digit by the position
of the digit in the number
 Let the number have n digits to the left of the radix point and m digits
to the right of the radix point. Di is the ith digit, R is the radix or base
of the number,V is the value of the number.
n 1
V   Di R i n digits m digits
i  m
E l : 12.3410  4  10 2  3  10 1  2  10 0  1  101
Example
Other common radices – binary (2), octal (8), hexadecimal/hex (16):

0-9,a,b,c,d,e,f.
Radix Conversion
 Conversion from radix R to Decimal
Example
11.011 2  1  2 3  1  2 2  0  2 1  1  2 0  1  21
 0.125  0.25  0  1  2
 3.37510
2
Conversion from Decimal to Radix R
Let rk be the kth digit of the radix R number :
Convert integer part: Let Di be the integer part of the decimal number
1. k=0; Dk =Di ;
2. rk =Dk mod R;
3. Dk 1  Dk / R  ;
4. if (Dk+1= 0) then quit ;
else k=k+1; and go to 2
Convert Fractional part: Let Df be the fractional part of the number

1. k = -1; Dk = Df;
2. X = Dk × R;
R
3. rk  X  ;
4. Dk-1 = X – rk;
5. k = k-1;
6. if ((Dk = 0) or (enough digits have been computed)) then quit;
else go to 2
Example
 Convert 3.375 to binary
D0  3.375  3; r0  3 mod 2  1
D1  3 / 2  1; r1  1 mod 2  1
D2  1 / 2  0;
D1  0.375 ; X  0.375  2  0.75

r1  0.75  0
D2  0.75 ; X  0.75  2  1.5
r2  1.5  1
D3  0.5 ; X  0.5  2  1.0
r1  1.0  1
D 4  0 ;
 The equivalent of 3.37510 is 11.0112

3
Conversion among Radices that are
Powers of 2
 Conversion among binary, octal and hex can be done by “grouping”
bits as follows:
1. First,, express
p each octal or hex digit
g as a binary
y number. This is the
conversion to binary.
2. To convert from binary to octal or hex, group sets of 3 bits (for octal) or
4 bits (for hex). The grouping must start at the binary point and go to
the left for the integer part of the number and to the right for the
fractional part. Add 0 bits as needed to the left end or right end of the
number.
3. Treat each group of bits as an octal (or hex) digit and rewrite it as a 0-7
(0-f).
(0 f).
Example: Convert 10110.010012 to octal and hex.

10110.010012 = 010 110  010 010
= 2 6  2 28
= 0001 0110  0100 1000
= 1 6  4 816
Representation of Signed Numbers

 How to represent positive and negative integers using 1’s and 0’s
of the binary notation ?
 IIn mathematics,
th ti there
th are infinitely
i fi it l many positive
iti andd negative
ti
integers. However, in a practical hardware system only a fixed
number of integers can be represented.
 In most modern computer systems, numbers are represented in

32 bits. If an arithmetic operation results in a number outside the
range, an overflow occurs.
 There are 4 popular schemes for representing signed numbers.

1. Sign Magnitude
2. Ones Complement
3. Twos Complement
4. Excess-B or Biased Representation
4
Sign Magnitude Representation
 Use MSB as a sign bit as follows,
 MSB = 0 for positive integers S Magnitude (n-1 bits)
 MSB = 1 for negative integers n bits
 Other bits encode magnitude of integer.
 Range of representation with n bits is:  2 n 1  X  2 n 1
 The range is symmetric around 0.
 There are two representations for 0, i.e., 0000 and 1000.
 Examples:
Assume a 4-bit representation, Convert the following sign magnitude

numbers to a 6-bit representation.
5 = 0101
-5 = 1101 0101 = 000101
3 = 0011
-7 = 1111 1010 = 100010
Ones Complement Representation

 Positive integers are represented “as is”. Negative integers are
represented by performing bit-wise complement of the integer. E.g.,
 5 = 0101
 -5 = 1010
 All positive integers have MSB=0; negative integers have MSB=1
 Range of representation with n bits is:  2 n 1  X  2 n 1
 The range is symmetric around 0.
 There are two representations for 0, i.e., 0000 and 1111.
 Examples:
Assume a 5-bit representation, Convertt the

C th following
f ll i signed
i d
01110 = 14 numbers to a 8-bit representation.
10111 = -8
15 = 01111 01011 = 00001011
16 = not with 5 bits
-16 = not with 5 bits 10111 = 11110111
5
Twos Complement Representation
 Positive integers are represented “as is”. Negative integers are
formed by subtracting magnitude of negative integer from 0;
borrowing from imaginary position to the left of MSB.
(Shortcut: bit-wise complement
p of the integer
g and add 1)).
 Example: 5 = 0101 -5 = 0000 – 0101 = 1011
 All positive integers have MSB=0; negative integers have MSB=1
 Range of representation with n bits is:  2 n 1  X  2 n 1
 The range is asymmetric around 0.
 There is only one representation for 0, i.e., 0000.
 Examples:
Assume a 5-bit representation, Convertt the
C th following
f ll i signed
i d
01110 = 14 numbers to a 8-bit representation.
10111 = -9
15 = 01111 01011 = 00001011
16 = not with 5 bits
-16 = 10000 10111 = 11110111
Excess--B (or Biased) Representation

Excess
 Integer representations are biased by B.
 A signed integer X is represented by the binary number X+B
 Range of representation with n bits is:  B  X  2 n  B
 Usually, B=2n-1  -2n-1 ≤ X < 2n-1
 There is only one representation for 0, i.e., binary representation for
bias B.
 Examples:
Assume a 5-bit representation and B = 24,
10001 = 17 – 24 = 1
01100 = 12 – 24 = -4
00000 = 0 – 24 = -16
0 = 0 + 24 = 10000
15 = 15 + 24 = 11111
6
Addition and Subtraction of Signed
Numbers
 Subtraction is performed by negating the number

( h
(changing
i sign)
i ) ffollowed
ll d by
b addition.
dditi
X  Y  X   Y 
 Subtraction requires 2 operations:

1
1. Negation, and
Negation
2. Addition
Addition/Subtraction in Sign
Magnitude Representation
 Negation is trivial – just invert the sign bit (MSB)
 Addition is relatively complex because sign bits and

relative magnitudes must be compared to perform
operation.
7
Addition/Subtraction in 1’s
Complement Representation
 Negation is trivial – just invert all bits
 Addition is performed in 2 steps:
1. Add all bits; any carry out of bit position i must be added into bit position
(i +1).
2. Add the result of first step with the carry out of the MSB position from
step 1. This carry is called the End Around Carry (EAC).
 Examples:
1111 (0) 0000 0000 (0)

+ 0010 (2) - 0011 + 1100 (
(-3)
3)
10001 01100
+ 1 + 0
0010 (2) 1100 (-3)
Addition/Subtraction in 2’s
Complement Representation
 Negation is expensive – first invert all bits; then add 1.
 Addition is performed by adding all bits; any carry out of bit position i
mustt be
b added
dd d iinto
t bit position
iti (i +1).
1) Ignore
I carry outt off MSB.
MSB
 Examples:
1111 (-1) 0000 0000 (0)

+ 0010 (2) - 0011 + 1101 (
(-3)
3)
10001 01101
0001 (1) 1101 (-3)

8
Overflow Detection
 Some additions and subtractions may produce results that cannot be
represented using the number of bits allocated for the result (i.e.,
precision).
 example, for an n-bit 2’s
For example 2 s complement represented number
number, if the
result is greater than (2n-1-1) it can’t be represented using n-bits.
 There is an overflow.
 How can overflow be detected?
 If (carry into the MSB) ≠ (carry out of the MSB) then overflow has occurred.
 Examples:
for 1’s comp. numbers
1011 (-4) for 2’s comp. numbers
+ 1010 (-5)
0100 0100 (4)
10101 - 1011 + 0101 (-5)
+ 1
0110 (6) OVFL 1001 (-7) OVFL
Adders and Subtracters

 The most basic arithmetic operation in a digital computer is
addition.
 Half Adder is a combination circuit that performs addition of 2
bits.
Inputs Outputs
a b Carry Sum
0 0 0 0
Sum  a b  a b  a  b
0 1 0 1
C
Carry  ab
1 0 0 1
1 1 1 0
9
Half Adder
Sum  a b  a b  a  b
y  ab
Carry
 Half adders cannot accept a carry input and hence it is not possible
to cascade them to construct an n-bit binary adder.
Full Adder
 Full Adder is a combinational circuit that forms the arithmetic sum of
three input bits. It is described by the following truth table:
Inputs Outputs
c b a Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Sum  a b c  a b c  a b c  a b c  a  b  c
C out  a b  a c  b c  a b  c a  b 
10
Full Adder Implementation - 1
Sum  a b c  a b c  a b c  a b c  a  b  c
C out  a b  a c  b c  a b  c a  b 
ai bi
ai
si bi
Full
Adder
ci+1 (FA) ci
ci+1
ci
Full Adder at bit i
si
Full Adder Implementation - 2

 A full adder can be implemented using 2 half adders and an OR gate
ai
si bi
ci+1 ci
ai bi
Full
Adder
ci+1 (FA) ci
si
11
Performance of a Full Adder
 Use a 2-input NAND gate implementation of a 1-bit full adder. Why ?
Ripple Carry Adder

 4-bit Binary Adder: ( Sum = A + B )
 A 4-bit binary adder can be implemented by cascading four 1-bit full
adders as follows:
 Inputs: A = (a3a2a1a0) Outputs: Sum = (s3s2s1s0)
B = (b3b2b1b0) Cout = c4
Cin = cin = c0
12
Performance of an n-bit Ripple Carry
Adder
 Carry ripples from input co to output cn

 Worst case propagation delay for sum in terms of 2-input NAND gate
delay (1 gd) is given by,
t sum  5  ni12 2  3  5  2n  2   3  2n  4
 Worst case propagation delay for carry output is given by,
t carry  delay for c n 1  2  5  ni12 2  2  2n  3
 Therefore, propagation delay for an n-bit Ripple Carry Adder is O(n).
Subtracter
 The subtraction of two binary numbers may be

accomplished by negating the subtrahend and adding it
t the
to th minuend.
i d
W  X Y
 X   Y 
 Negation should be done based on the number

representation scheme used in the system (i.e., 1’s
complement
l t or 2’s
2’ complement).
l t)
 Therefore, subtraction operation becomes an addition

operation requiring full adders for its hardware
implementation.
13
2’s Complement Subtracter
 Design a 4-bit subtracter using 2’s complement number representation.
Diff = A - B
 Inputs: A = (a3a2a1a0) Outputs: Diff = (s3s2s1s0)
B = (b3b2b1b0) Cout is ignored
A B
BCD Addition
 When we add two BCD digits, the sum may exceed 9
 we need to do appropriate correction.
 Let X = x3x2x1x0 and Y = y3y2y1y0 represent the two BCD digits and
S = s3s2s1s0 be their sum.
sum
Z  X Y
if  Z  9  then S  Z and cout  0
if  Z  9  then S  Z  6 and cout  1
X 0111 7 X 1000 8
+Y +0101 +5 +Y +1001 +9
Z 1100 1 2 Z 10001 1 7
+0110 +0110
1 0010 1 0111
cout=1 S=2 cout=1 S=7
14
1-Digit BCD Adder
X Y
x3 y3 x2 y2 x1 y1 x1 y1
4 bit Adder
4-bit Add cin FA FA FA FA cin
Z z3 z2 z1 z0
6 0
Z>9
?
yes MUX
FA HA
cout 4-bit Adder cout s3 s2 s1 s0
Other Adder based Arithmetic Circuits

 Design a 4-bit 2’s complement arithmetic circuit that can
work as an adder or subtracter based upon the value of a
control input
input. It should add if the control input is “0”
0 and
subtract if it is “1”.
 Design an n-bit absolute (ABS) value generator for 2’s

complement represented numbers, i.e., for an n-bit input,
X, the output is |X|
15
Bit--Serial Adder
Bit
Arithmetic and Logic Unit (ALU)

 An ALU is a combinational circuit that can perform any of
a number of different arithmetic and logical operation on a
pair of n-bit
n bit operands.
operands
 Operation to be performed is specified by a set of control
(function-select) inputs.
 ALUs are designed in a bit-slice fashion and slices can be
cascaded to form larger ALUs. Some ALUs are designed
as an m-bit group instead of a single bit slice.
 m-bit group enables us to improve carry propagation
within a group using carry lookahead or other similar
enhancements.
16
Unsigned Binary Multiplication
 Consider unsigned m- and n-bit integers, X and Y

m 1 n 1
X   xi 2i Y   yj2j
i 0 j 0
m  n 1  m 1   n 1  m 1 n  1
P  X Y   pk 2 k    x i 2 i     y j 2 j     x i y j  2 i  j
k 0  i 0   j 0  i 0 j 0
Array Multiplier
x3 x2 x1 x0
x3x2x1x0 y0
× y3y2y1y0
y0x3 y0x2 y0x1 y0x0
y1x3 y1x2 y1x1 y1x0 y1
y2x3 y2x2 y2x1 y2x0
y3x3 y3x2 y3x1 y3x0 HA FA FA HA
y2
FA FA FA HA
y3
FA FA FA HA
p7 p6 p5 p4 p3 p2 p1 p0
17
Performance of Array Multiplier
m
x3 x2 x1 x0
y0
y1
HA FA FA HA
n
y2
Critical path 1 FA FA FA HA
Critical path 2
y3
FA FA FA HA
p7 p6 p5 p4 p3 p2 p1 p0
t mult  t and  m  1  n  2  t carry  n  1  t sum
Array Multiplier using Carry Save Adders

x3 x2 x1 x0
y0
y1
HA HA HA
y2
FA FA FA
y3
FA FA FA
t mult  t and  n  1 t carry  t cpa

Carry propagate
Adder FA FA HA
p7 p6 p5 p4 p3 p2 p1 p0
18
Signed Multiplication
Positive Multiplicand Negative Multiplicand
01110 (+14) 10010 ( 14)

(-14)
x 01011 (+11) x 01011 (+11)
000001110 111110010
00001110 11110010
0000000 0000000
001110 110010
+ 00000 + 00000
0 1 0 0 1 1 0 1 0 (+154) 101100110 (-154)
Negative Multiplier: Negate multiplier and multiplicand and use

the above scheme for positive multiplier.
Combinational Shifter
 1-bit left/right shifter without using clocks

 Multi-bit shift operation on an n-bit input data word can be done by
performing the above operation repeatedly  too slow for large n.
19
Logarithmic Depth Shifter
Left Shifter Right Shifter
in[7:0]
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
shift right by 5
1 shift
f 0
0 shift1
1 shift2
1 shift3
7 6 5 4 3 2 1 0
Area = O(nlog2n) out[7:0]
Note: Interconnections are shown for
Time = O(log2n)
Arithmetic Shift operation
Comparator – Equality Check

 Iterative algorithm:  xn 1 ... x 2x1x 0    yn 1 ... y2y1y0  ?
1. i  0; EQ 0  1; xi yi
2. if  xi  y i    EQ i  1
then EQ i 1  1;
else EQ i 1  0; EQi+1 EQi
3. i  i  1;
4. if i  n
then go to step 2;
else end;
xn-1 yn-1 x2 y2 x1 y1 x0 y0
x y x y x y x y
EQn EQUIV EQ EQ3 EQUIV EQ2 EQUIV EQ1 EQUIV EQ0
n-1
EQO EQI EQO EQI EQO EQI EQO EQI
20
4-Bit Comparator
 Magnitude comparator for
n-bit unsigned binary numbers
 Inputs: a3a2a1a0
4 4
b3b2b1b0
altbin aeqbin agtbin b3-0 a3-0
 Outputs: altbout altbin
aeqboutCOMP4 aeqbin
altbout aeqbout agtbout agtbin
agtbout
 Logic Equations:
agtbout  a 3  0 >b3  0   a3  0 =b3  0   agtbin
aeqbout  a3  0 =b3  0   aeqbin
altbout  a3  0 <b3  0   a 3  0 =b3  0   altbin
a30  b30       
 a3b3  a3  b3 a2b2  a3  b3 a2  b2 a1b1  a3  b3 a2  b2 a1  b1 a0b0   
  
a30  b30   a3  b3 a2  b2 a1  b1 a0  b0  
a30  b30   a30  b30  a30  b30 
12--Bit Comparator (unsigned)

12
x11…0
y11…0
11 0
x11…8 y11…8 x7…4 y7…4 x3…0 y3…0
4 4 4 4 4 4
b
3-0 3-0 a XLTY8 b3-0 a3-0 b3-0 a3-0
XLTY XLTY4
altb altbin XEQY8 altbout altb altb altbin 0
XEQY out in XEQY4 out
aeqboutCOMP4 aeqbin aeqboutCOMP4 aeqbin aeqb COMP4 aeqb
in
1
XGTY agtb XGTY8 agtb XGTY4
out
agtbout in agtbout in agtbout agtbin 0
21
MIN/MAX Circuit
 Use a 4-bit comparator to design an 8-bit MIN/MAX circuit.
 Inputs: unsigned inputs, X ≡ x7..0 , Y ≡ y7..0
and a control signal MINMAX
 Output:  min  X ,Y  if MINMAX  1
Z  
 max  X ,Y  if MINMAX  0
MINMAX
X>Y MINMAX Z S
X 0 0 Y 1
12 COMP 0 1 X 0
X>Y
Y 1 0 X 0
12 S
1 1 Y 1
0
MUX Z
1 12
Floating--Point Number Representation

Floating
1 p bits m bits
S Exponent (E) Mantissa (M)
 Sign bit: S is the sign of the floating point number

 Exponent: p-bit exponent (E) in excess-B code.
 Mantissa: m-bit unsigned mantissa (M).
 Radix: R is the radix for the representation.
 Actual value of the number represented above is:

 F = (-1)S × 1.M × RE-B … (if normalized)
 F = (-1)S × M × RE-B … (if unnormalized)
22
IEEE Floating
Floating--Point Format
 Single Precision Format: (32 bits)
1 8 bits 23 bits
S Exponent (E) unsigned Mantissa (M)

31 30 23 22 0
 F = (-1)S × 1. M × 2E-127
 Special reserved values:
 E=0 with M = 0 represents ZERO
 E = 255 with M = 0 represents ± oo
 E = 255 with M ≠ 0 represents NaN
 Double Precision Format: (64 bits)
1 11 bits 52 bits
S Exponent (E) unsigned Mantissa (M)
 F = (-1)S × 1. M × 2E-1023
Examples
 Convert 4.62×102 to IEEE single precision format:
4.62×102 = 462 = 111001110.0 = 1.110011100 × 28
 Mantissa = 110011100 Exponent = 8+127 = 135 = 10000111
0 1000 0111 1100 1110 0000 0000 0000 000 = 0 87 CE0000
 Convert -0.456×2-3 to IEEE single precision format:

-0.456×2-3 = - 0.0111 0100 1011 1100 0110 1010 0111 1101 × 2-3
= -1.1101 0010 1111 0001 1010 101 × 2-5
 Exponent = -5+127 = 122 = 01111010
1 0111 1010 1101 0010 1111 0001 1010 101 = 1 7A D2F1AA
 Convert 1 81 99999A to decimal representation:

Mantissa = -1.1001 1001 1001 1001 1001 1010 Exponent = 8116 - 12710
= -1.1001 1001 1001 1001 1001 1010 × 22
= -0110.0110 0110 0110 0110 0110 1 = -6.4
23
Floating--Point Addition (unsigned)
Floating
 How to add two floating-point numbers?
(Ma,Ea) + (Mb,Eb)
1. Place number with larger exponent in register 1 and the other in 2.

2. d = E1 – E2
3. Right-shift mantissa M2 by d bits (i.e., left-shift radix point by d bits).
4. MSUM = M1 + M2; ESUM=E1
5. If (MSUM) ≥ 2, renormalize (post-normalization) by dividing by 2
(shifting right) and incrementing ESUM .
6. Rounding may be required to store the result in the same number of
bits (precision) as the inputs.
7. Result = (MSUM, ESUM).
Example: Addition
 Add (0 11000000, 011) to (0 10101100, 100) (input numbers are
positive and are in the normalized form with excess-4 exponent).
 That is, (1.11000000 × 2011-100) + (1.10101100 × 2100-100) = ?
 Since (100 > 011), M1 = 1.10101100 E1 = 100 and M2 = 1.11000000 E2 =

011
 d = E1 – E2 = 100 – 011 = 001
 Right-shift M2 by 001 (1) bits  M2 = 0.11100000 E2 = 100
 MSUM = 1.10101100 + 0.11100000 = 10.10001100 and ESUM= E1 =
100
 Post normalize: MSUM = 1.01000110
Post-normalize: 1 01000110 and ESUM= 101
 Therefore,
(1.11000000 × 2011-100) + (1.10101100 × 2100-100) = (1.01000110 × 2101-100)
 Or,
(11000000, 011) + (10101100, 100) = (0, 01000110, 101)
24
Floating--Point Multiplication
Floating
 How to multiply two floating-point numbers?
(Ma, Ea) × (Mb, Eb)
1. MPROD = M1 × M2
2. EPROD = E1 + E2- bias
3. Post-normalize MPROD by shifting by an appropriate amount
and then updating EPROD by the same amount.
4. Rounding may be required to store the result in the same
number
b off bits
bit ((precision)
i i ) as th
the iinputs.
t
5. If necessary, normalize and update EPROD
6. Result = (MPROD, EPROD).
Example: Multiplication
 Multiply (0 10101100, 0101) and (0 11000000, 0110) (input
numbers positive and are in the normalized form with
excess-8
excess 8 exponent).
 That is, (1.10101100 × 20101-1000) × (1.11000000 × 20110-1000) = ?
 MPROD = 1.10101100 × 1.11000000 = 10.1110110100000000 and

EPROD= E1 + E2 - 8 = 0011
 Post-normalize: MPROD = 1.01110110100000000 and
EPROD= 0100
 Roundingg : MPROD = 1.01110111
 Therefore,
(1.11000000 × 20101-1000) × (1.10101100 × 20110-1000) = (1.01110111 × 20100-1000)
 Or,
(11000000, 0101) × (10101100, 0110) = (0 01110111, 0100)
25
Example: Centigrade – Fahrenheit Converter
 Design a circuit that will convert 8-bit temperature input

from Centigrade to Fahrenheit scale.
F  C   9 5   32
 This is suppose to be an ultra low-cost (throwaway)
device and so to reduce the cost of this device we are
allowed to approximate computation
C
F  C   2   32
8
<<1 32 (00100000)
8 8
8-bit adder
How would you design 8
this adder efficiently?
F
Example: Running Average Filter

 Design a circuit performs 4-point running average filtering operation on
sampled data x[n]. Each sample has 4-bits.
1 3
y  n   x  n  k  assume x  n  0 for n  0
4 k 0
x[n-1] x[n-2] x[n-3]
x[n] D Q D Q D Q
4 4FF 4 4FF 4 4FF 4
Λ Λ Λ
clk
1 1 1 1
4 4 4 4
+ + + y[n]
y[n]
y[n]
x[n]
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
n 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
n n
Input Signal Output Signal (4-point avg.) Output Signal (8-point avg.)
26
Filter Implementation
 Since all samples get multiplied by ¼ we can do it once at the end.
 Multiply by ¼ (i.e. divide by 4) is done by shifting right by 2 bits.
x[n-1] x[n-2] x[n-3]

x[n] D Q D Q D Q
4 4FF 4 4FF 4 4FF 4
Λ Λ Λ
4 clk 4 4 4
+ + 6
+ 5 4
y[n]
5 6-bit 6 bit
6-bit
5-bit 4
add add add 3
2
1
0
27

Arithmetic Circuits

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Arithmetic Circuits

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Arithmetic Circuits

Poras T. Balsara & Dinesh K. Bhatia

Other common radices – binary (2), octal (8), hexadecimal/hex (16):

© ptb/dkb (November 19, 2010) Arithmetic Circuits 3

© ptb/dkb (November 19, 2010) Arithmetic Circuits 4

Convert Fractional part: Let Df be the fractional part of the number

© ptb/dkb (November 19, 2010) Arithmetic Circuits 5

D1  0.375 ; X  0.375  2  0.75

 The equivalent of 3.37510 is 11.0112

Example: Convert 10110.010012 to octal and hex.

© ptb/dkb (November 19, 2010) Arithmetic Circuits 7

Representation of Signed Numbers

 In most modern computer systems, numbers are represented in

 There are 4 popular schemes for representing signed numbers.

© ptb/dkb (November 19, 2010) Arithmetic Circuits 9

Assume a 4-bit representation, Convert the following sign magnitude

© ptb/dkb (November 19, 2010) Arithmetic Circuits 10

Ones Complement Representation

Assume a 5-bit representation, Convertt the

© ptb/dkb (November 19, 2010) Arithmetic Circuits 11

© ptb/dkb (November 19, 2010) Arithmetic Circuits 12

Excess--B (or Biased) Representation

Assume a 5-bit representation and B = 24,

© ptb/dkb (November 19, 2010) Arithmetic Circuits 13

 Subtraction is performed by negating the number

 Subtraction requires 2 operations:

© ptb/dkb (November 19, 2010) Arithmetic Circuits 14

 Negation is trivial – just invert the sign bit (MSB)

 Addition is relatively complex because sign bits and

© ptb/dkb (November 19, 2010) Arithmetic Circuits 15

1111 (0) 0000 0000 (0)

1111 (-1) 0000 0000 (0)

0001 (1) 1101 (-3)

© ptb/dkb (November 19, 2010) Arithmetic Circuits 18

Adders and Subtracters

© ptb/dkb (November 19, 2010) Arithmetic Circuits 19

© ptb/dkb (November 19, 2010) Arithmetic Circuits 20

© ptb/dkb (November 19, 2010) Arithmetic Circuits 21

© ptb/dkb (November 19, 2010) Arithmetic Circuits 22

Full Adder Implementation - 2

© ptb/dkb (November 19, 2010) Arithmetic Circuits 23

© ptb/dkb (November 19, 2010) Arithmetic Circuits 24

Ripple Carry Adder

© ptb/dkb (November 19, 2010) Arithmetic Circuits 25

 Carry ripples from input co to output cn

 Therefore, propagation delay for an n-bit Ripple Carry Adder is O(n).

© ptb/dkb (November 19, 2010) Arithmetic Circuits 26

 The subtraction of two binary numbers may be

 Negation should be done based on the number

 Therefore, subtraction operation becomes an addition

© ptb/dkb (November 19, 2010) Arithmetic Circuits 28

cout 4-bit Adder cout s3 s2 s1 s0

© ptb/dkb (November 19, 2010) Arithmetic Circuits 30

Other Adder based Arithmetic Circuits

 Design an n-bit absolute (ABS) value generator for 2’s

© ptb/dkb (November 19, 2010) Arithmetic Circuits 31

© ptb/dkb (November 19, 2010) Arithmetic Circuits 39

Arithmetic and Logic Unit (ALU)

© ptb/dkb (November 19, 2010) Arithmetic Circuits 40

 Consider unsigned m- and n-bit integers, X and Y

© ptb/dkb (November 19, 2010) Arithmetic Circuits 41

© ptb/dkb (November 19, 2010) Arithmetic Circuits 42

© ptb/dkb (November 19, 2010) Arithmetic Circuits 43