********************************************************************************

* Software License Agreement *

* *
* The software supplied herewith by Microchip Technology Incorporated (the *
* 'Company') is intended and supplied to you, the Company's customer, for use *
* solely and exclusively on Microchip products. *
* *
* The software is owned by the Company and/or its supplier, and is protected *
* under applicable copyright laws. All rights are reserved. Any use in *
* violation of the foregoing restrictions may subject the user to criminal *
* sanctions under applicable laws, as well as to civil liability for the *
* breach of the terms and conditions of this license. *
* *
* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *
********************************************************************************

.SUBCKT MCP6V51 1 2 3 4 5
* | | | | |
* | | | | Output
* | | | Negative Supply
* | | Positive Supply
* | Inverting Input
* Non-inverting Input
*
*
* The following op-amps are covered by this model:
* MCP6V51/1U
*
* Date of model creation: 7-5-2019_3:51:22_PM
* Level of Model Creator: 6.27S / 07-05-19
*
* Revision History:
* REV A: 30-Oct-18, Initial Input
* REV B: 04-Mar-19, Updated Noise Characteristics
* REV C: 16-Apr-19, Updated Output Impedance Matching
* REV D: 06-Jun-19, Updated Slew Rate and Gain/Phase based on VDD
* REV E: 26-Jun-19, Updated Support for Mindi/SIMetrix Normal Convergence
* REV F: 01-Jul-19, Updated Reverse recovery for sine wave inputs
* REV G: 05-Jul-19, Updated Slew rate clamps to resolve convergence issue
*
* Recommendations:
* Use PSPICE (or SPICE 2G6; other simulators may require translation)
* For a quick, effective design, use a combination of: data sheet
* specs, bench testing, and simulations with this macromodel
* For high impedance circuits, set GMIN=100F in the .OPTIONS statement
*
* Supported:
* Typical performance for temperature range (-40 to 125) degrees Celsius
* DC, AC, Transient, and Noise analyses.
* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
* open loop gain, voltage ranges, supply current, ... , etc.
* Temperature effects for Ibias, Iquiescent, Iout short circuit
* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
* Some Variation in specs vs. Power Supply Voltage
* Vos distribution, Ib distribution for Monte Carlo
* Distortion (detailed non-linear behavior)
* Some Temperature analysis
* Process variation
* Behavior outside normal operating region
*
*
*
*
* EMI Stage
*
RF1 1 1A 468
RF2 2 2A 468
RF3 1A 1B 468
RF4 2A 2B 468
CF1 1A 0 1.2p
CF2 0 2A 1.2p
CF3 1B 0 1.2p
CF4 0 2B 1.2p
*
* Input Stage
*
V10 3 10 1.9
R10 10 11 69.0K
R11 10 12 69.0K
G10 10 11 10 11 1.44M
G11 10 12 10 12 1.44M
C11 11 12 115E-15
C12 1B 0 12.0P
E12 71 14 VALUE { (-1.9U) + V(20) * 1.11 + V(21) * 1.11 + V(22) * 1.11 + V(23) *
1.11 }

* Generate Input Bias 1 and 2 and Input Offset

EG12 VIBIAS 0 62 0 1
EG13 VIBIOS 0 63 0 1

* Calculate IB1 and IB2 based on IOS

EIB1 VIB1 0 VALUE { (V(VIBIAS)+V(VIBIOS)) /2 }
EIB2 VIB2 0 VALUE { (V(VIBIAS)-V(VIBIOS)) /2 }

* Convert Voltage to Current on Pins 1 and 2

GIB1 1B 0 VIB1 0 1u
GIB2 2B 0 VIB2 0 1u

M12 11 14 15 15 NMI
M14 12 2B 15 15 NMI
C14 2B 0 12.0P
I15 15 4 500U
V16 16 4 -300M
GD16 16 1B TABLE { V(16,1) } ((-100,-100E-15)(0,0)(1m,1u)(2m,1m))
V13 3 13 2.1
GD13 2B 13 TABLE { V(2,13) } ((-100,-100E-15)(0,0)(1m,1u)(2m,1m))
R71 1B 0 10.0E12
R72 2B 0 10.0E12
R73 1B 2B 10.0E12
*C13 1B 2B 1.00E-15
*
* Noise
*
I20 21 20 4.23M
D20 20 0 DN1
D21 0 21 DN1
I22 22 23 1N
R22 22 0 1k
R23 0 23 1k
*
* Open Loop Gain, Slew Rate
*
* Gain dependent on VDD (VDD=45, 100% and VDD=4.5, 80%
E1001 1001 0 VALUE = {V(3) - V(4)}
E2001 2001 0 TABLE { V(1001,0) } ((4.5,0.0794)(45.0,1.0))
E3001 3001 0 TABLE { V(1001,0) } ((4.5,({14.4M*1E6*0.0892}))(45.0,{14.4M*1E6}))
G30 0 30 VALUE {V(2001,0) * (V(12) - V(11))}
R30 30 0 1.00K
G31 0 31 3 4 2.71
I31 0 31 DC -4.55
R31 31 0 1
E_VDDMAX VDE 0 3 4 1
V_VDD1 31VDD1 0 22.5
V_VDD2 31VDD2 0 2.25
G_ABMII2 0 31B VALUE { V(31)*(LIMIT(((V(31VDD1)-V(VDE))/(V(31VDD1)-V(31VDD2))), 0,
1))}
R_R3 31A 0 1 TC=444U, -6.01U
G_ABMII1 0 31A VALUE { V(31)*(LIMIT(((V(VDE)-V(31VDD2))/(V(31VDD1)-V(31VDD2))), 0,
1))}
G_G6 30 31C TABLE { V(30, 31C) } ((-100,-1n)(0,0)(1m,0.1)(101m,190.1))
E_ABM1 31C 0 VALUE { (V(31A) + V(31B)) }
R_R8 31B 0 1 TC=1.12M, 4.54U
G32 32 0 3 4 2.90
I32 32 0 DC -1.57
R32 32 0 1
G_ABMII22 32B 0 VALUE { V(32)*(LIMIT(((V(31VDD1)-V(VDE))/(V(31VDD1)-V(31VDD2))), 0,
1))}
R_R23 32A 0 1 TC=852U, 5.71U
G_ABMII21 32A 0 VALUE { V(32)*(LIMIT(((V(VDE)-V(31VDD2))/(V(31VDD1)-V(31VDD2))), 0,
1))}
G_G26 32C 30 TABLE { V(30, 32C) } ((-101m,190.1)(-1m,0.1)(0,0)(100,-1n))
E_ABM21 0 32C VALUE { (V(32A) + V(32B)) }
R_R28 32B 0 1 TC=1.21M, 408N
G6 0 33 30 0 1m
R6 33 0 1K
*
* 1st Order Pole
*
G34 0 34 33 0 177
R34 34 0 1K
R4001 34 4005 1E-6
VC 4005 4006 0
EC 4006 0 Value = {V(4007) / ( V(3001,0)*1E-6) }
G4001 0 4007 Value = {I(VC)}
C4001 4007 0 1
R4002 4007 0 1E9
*
* 2nd Order Pole
*
G37 0 37 34 0 1m
R37 37 0 1K
C37 37 0 26.5P
*
* Extra 2nd Pole
*
G37A 0 37A 37 0 1m
R37A 37A 0 1K
C37A 37A 0 26.5P
*
* 3rd Order Pole
*
G377A 0 377A 37A 0 1m
R377A 377A 0 1K
C377A 377A 0 26.5P
*
* 4th Order Pole
*
G378A 0 378A 377A 0 1m
R378A 378A 0 1K
C378A 378A 0 530N
*
* 1st Order Zero
*
G38 0 38 378A 0 1m
GR38 39 0 39 0 1m
RR38 39 0 100G
L38 38 39 53.0U
*
* 2nd Order Zero
*
G38A 0 38A 38 0 1m
GR38A 39A 0 39A 0 1m
RR38A 39A 0 100G
L38A 38A 39A 3.99M
E38 35 0 38A 0 1
*
* Output Stage
*
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57 96 0.50
R57 57 57A 300
LR14 57 57A 1.2M
RR14 57A 0 2.2
* PSRR / CMRR
G57 0 57 VALUE { V(35) * 454M + V(118) + V(127) + V(137) }
*
*
* PSRR Plus Gain and GBWP Pole Neutralization and Wave Shaping
*
* G30 THE DC GAIN FOR +PSRR
G110 0 110 3 0 906U
* ADD POLE TO NEUTRALIZE GBWP ZERO
R110 110 0 1G
GR110 110 0 110 0 1M
C110 110 0 14.4M
*
*
* PSRR Plus Pole
*
G111 0 111 110 0 1
L111 111 112 4.42M
R112 112 0 1G
GR112 112 0 112 0 1
*
* PSRR Plus Zero
*
G114 0 114 111 0 1
R114 114 0 1G
C114 114 0 530U
GR114 114 0 114 0 1
*
* PSRR Plus 2nd Pole
*
G115 0 115 114 0 1
L115 115 116 3.98M
R116 116 0 1G
GR116 116 0 116 0 1
*
* PSRR Plus 2nd Zero
*
G117 0 117 115 0 1
R117 117 0 1G
C117 117 0 2.27U
GR117 117 0 117 0 1
*
* PSRR Plus 3rd Pole
*
G118 0 118 117 0 1
L118 118 119 79.6N
R119 119 0 1G
GR119 119 0 119 0 1
*
* PSRR Minus Gain and GBWP Pole Neutralization and Wave Shaping
*
* G40 THE DC GAIN FOR -PSRR
G120 0 120 4 0 642U
* ADD POLE TO NEUTRALIZE GBWP ZERO
R120 120 0 1G
GR120 120 0 120 0 1M
C120 120 0 14.4M
*
*
* PSRR Minus Pole
*
G121 0 121 120 0 1
L121 121 122 15.9
R122 122 0 1G
GR122 122 0 122 0 1
*
* PSRR Minus Zero
*
G124 0 124 121 0 1
R124 124 0 1G
C124 124 0 530U
GR124 124 0 124 0 1
*
* PSRR Minus 2nd Pole
*
G125 0 125 124 0 1
L125 125 126 159P
R126 126 0 1G
GR126 126 0 126 0 1
*
* PSRR Minus 2nd Zero
*
G1217 0 127 125 0 1
R127 127 0 1G
C127 127 0 3.97U
GR127 127 0 127 0 1
*
* CMRR Gain and GBWP Pole Neutralization and Wave Shaping
*
* G50 THE DC GAIN FOR CMRR
G130 0 130 VALUE { ( V(15) ) * 2.03M}
* Add Zero To Neutralize GBWP Pole
R130 130 0 1G
GR130 130 0 130 0 1m
C130 130 0 11.0M
*
*
* CMRR Pole
*
G131 0 131 130 0 1
L131 131 132 796U
R132 132 0 1G
GR132 132 0 132 0 1
*
* CMRR Zero
*
G133 0 133 131 0 1
R133 133 0 1G
C133 133 0 159P
GR133 133 0 133 0 1
*
* CMRR 2nd Pole
*
G134 0 134 133 0 1
L134 134 135 159P
R135 135 0 1G
GR135 135 0 135 0 1
*
* CMRR 2nd Zero
*
G137 0 137 134 0 1
R137 137 0 1G
C137 137 0 159P
GR137 137 0 137 0 1
*
GD55 55 57 TABLE { V(55,57) } ((-0.2m,-400)(-0.1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE { V(57,56) } ((-0.2m,-400)(-0.1m,-1m)(0,0)(10,1n))
C555 55 57 1P
C557 57 56 1P
E55 55 0 VALUE { 0.00 + V(3) * 1 + V(51) * -49.8M }
E56 56 0 VALUE { 0.00 + V(4) * 1 + V(52) * -21.0M }
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE { V(50,51) } ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE { V(50,52) } ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
G53 3 0 VALUE { -500U + V(51) * 1M }
G54 0 4 VALUE { -500U + V(52) * -1M }
*
* Current Limit
*
G99 96 5 99 0 1
R98 0 98 1 TC=-2.81M,8.41U
G97 0 98 TABLE { V(96,5) } ((-90.0,-41.0M)(-1.00M,-40.5M)(0,0)(1.00M,52.4M)
(90.0,53.0M))
E97 99 0 VALUE { V(98) * LIMIT((( V(3) - V(4) ) * -3.63M + 1.02), 0.00, 1E6 ) *
LIMIT((( V(3) - V(4) ) * 196M + -470M), 0, 1) }
D98 4 5 DESD
D99 5 3 DESD
*
* Temperature / Voltage Sensitive IQuiscent
*
R61 0 61 1 TC=1.85M,-1.73U
G61 3 4 61 0 1
G60 0 61 TABLE { V(3, 4) } ((0, 0)(1.25,4.55U)(2.4,350U)(3.00,450U)(20.0,455U)
(30.0,455U)(45.0,460U))
*
* Temperature Sensitive offset voltage
*
I73 0 70 DC 1
R74 0 70 1 TC=6.00N
E75 1B 71 VALUE {V(70)-1}
*
* Temp Sensistive IBias
*
I62 0 62 DC 1uA
R62 622 62 REXP 28.33488
R622 0 622 REXP_2 230.76042M
*
* Temp Sensistive Offset IBias
*
I63 0 63 DC 1uA
R63 633 63 REXP2 145
R633 0 633 REXP_4 53.07311
*
*
G57X 0 57X VALUE { V(35) * 454M + V(118) + V(127) + V(137) }
R57X 57X 57AX 300
LR14X 57X 57AX 1.2M
RR14X 57AX 0 2.2
G35X 33 0 TABLE { V(57X,3) } ((-1,-1p)((0,0)(100M,1n))(1.00,1))
G36X 33 0 TABLE { V(57X,4) } ((-1.00,-1)((-100M,-1n)(0,0)(1,1p))
*
* Models
.MODEL NMI NMOS(L=2.00U W=42.0U KP=200U LEVEL=1 )
.MODEL DESD D N=1 IS=1.00E-15
.MODEL DN1 D IS=1P KF=16.9E-18 AF=1
.MODEL REXP RES TCE= 597.4256M
.MODEL REXP_2 RES TCE= 8.93274
.MODEL REXP2 RES TCE=0.00
.MODEL REXP_4 RES TCE= 1.74152
.ENDS MCP6V51