2010 IEEE Control and System Graduate Research Colloquium
VHDL Simulation of Reset Automatic Block, 64
Bit Latch Block, and Test Complete Blocks for
PD Detection Circuit System Using FPGA
Emilliano#1, Chandan Kumar Chakrabarty#2, Ahmad Basri Abdul Ghani#3, Agileswari K. Ramasamy#4
#
Department of Electronic and Communication Engineering, College of Engineering (COE), Universiti Tenaga Nasional, Km.7,
Jln. Kajang-Puchong,43009, Selangor Darul Ehsan, Malaysia
emilliano@uniten.edu.my, Chandan@uniten.edu.my
Abstract─This paper is purely a model to determine the design
circuit to implement Partial Discharge (PD) detection in FPGA
technology. The research shall involve ISE Simulator version
10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST)
using Very high integrated circuit Hardware Description
Language (VHDL) programming to evaluate the use of Field
Programming Gate Array (FPGA) for the detection and counting
of partial discharge signals in high voltage underground cable.
The impulse signals at the input data have very fast rise time in
the range of 1 ns to 2 ns. The output signals of peak detector
block, 64 bit BCD counter with reset block and reset automatic
block is processed using reset automatic block and 64 bit latch
block for keep output data in LCD to constant when the 64 bit
BCD counter block is reset and return to zero again until update
new data again. The combination of all blocks of PD detection
circuit system is tested by using ISE simulator. In the next stage,
this method will be implemented on a lab simulation scale for
testing and validation.
Keyword─ Partial Discharge Detection, FPGA Simulation, FPGA
Technology, ADC with Peak Detector Block, Real Time
Processing, Underground Cable, Counter with Reset Block,
VHDL Programming.
I. INTRODUCTION
Fig. 1 Block diagram partial discharge detection using gigahertz data
acquisition with FPGA technology
978-1-4244-7240-6/10/$26.00 ©2010 IEEE
PD detection system is an automatic system that can detect
and display PD signals from underground cable for easy
readout. PD detection system can work without oscilloscope,
computer or any other associated costly measuring equipment.
PD signal is detected by using magnetic probe sensor.[1] This
system can detect the PD signal in underground cable from
above the ground without shutdown the electricity that passed
through a very high voltage underground cable. The FPGA
compiler use (Test Bench) Xilinx ISE simulator and ISE
Xilinx Synthesis Technology (XST) to simulate and synthesis
real time data from output Analogue to Digital Converter
(ADC) block to PD detection circuit blocks in Xilinx FPGA
board. The impulse PD signals at the input data have very fast
rise time in the range of 1 ns to 2 ns. Figure1 shows the typical
block diagram for detecting and monitoring partial discharge
signal.
The work in this paper primarily involved modeling, which
comprises design, synthesis, simulation, test and analysis
deeply of reset automatic block and 64 bit latch block for keep
output data in LCD to constant when the 64 bit BCD counter
block is reset and return to zero again until update new data
again. In the next stage, this method will be implemented on a
lab simulation scale for testing and validation. With this
method of PD detection, real PD signals can be detected
although the PD signals from magnetic probe sensor are too
weak. The PD signals can also be counted and displayed
clearly even if the PD signals have too much distortion. The
PD detection circuit system can distinguish between PD pulse
signal and harmonic signal or other noise signal because the
invention PD detection circuit has a peak detector using
threshold value, if the amplitude of signal is more than
threshold value it can detect the signal and if the signal is less
than threshold value it can’t detect the signal. In the real
system, amplitude of PD signal is always more than amplitude
of noise. So it is very easy to distinguish which kind the PD
signal or harmonic signal or noise signal, but the first time, the
threshold value must be set between amplitude of PD signal
and amplitude of Noise signal.
14
2010 IEEE Control and System Graduate Research Colloquium
Fig. 2 Detail complete block diagram of partial discharge detection circuit using gigahertz data acquisition with FPGA technology
The functional approach of the reset automatic block, the 64
bit latch with reset and update block and the testing complete
blocks of PD detection circuit will be dealt in this paper. The
physics of PD generation and data acquisition system are very
extensive and broad. Thus, they are not dealt in this work. The
ADC and peak detector block, 64 bit BCD counter with reset
block and reset automatic block have been dealt in the other
paper, they are not also dealt in this paper.
II. THE PEAK DETECTOR BLOCK, THE 64 BIT BCD COUNTER
BLOCK AND THE RESET AUTOMATIC BLOCK FOR BCD
COUNTER
Figure 2 shows the complete block diagram of PD detection
circuit. The function of combination 3 blocks programming of
PD detection circuit as follows:
1. The ADC and Peak Detector Block in Hardware of
FPGA Board:
The function of this ADC and peak detector block is for
receiving very high speed data logic from ADC module after
the data is converted from analogue signal to digital signal and
then detect the amount of peak pulse signals in logic data
when processed by the peak detector in FPGA board. The
15
threshold value must be set firstly, so PD signal will be
detected if the input signal is higher than threshold value.[2]
2. The BCD Counter with reset block in hardware of FPGA
board:
The purpose of the BCD Counter and reset block is for
counting the amount of PD signals from the ADC signal and
peak detection block in the FPGA and then perform the
computation of the real time data using 64 bit digital output
data in VHDL Programming.[2]
3. The Reset Automatic block for BCD Counter in hardware
implementation of FPGA board:
The function of Reset Automatic Block is generating impulse
reset each 1s that will be supplied to counter block. It is very
important because data output from BCD counter block can’t
be reset without this signal. The differential between the reset
automatic for BCD counter and the reset automatic for latch
block is the reset automatic for latch block is faster 1 clock
pulse than the reset automatic for BCD counter. It means the
output data of latch block must be updated first before the
BCD counter is reset.[2]
2010 IEEE Control and System Graduate Research Colloquium
III. T HE RESET AUTOMATIC BLOCK FOR LATCH
The function of Reset Automatic Block is generating
impulse reset each 1s that will be supplied to Counter Block
and Latch Block. It is very important because data output from
Latch Block can’t be updated without this signal and also data
output from BCD counter block can’t be reset without this
signal.[3] The timing of impulse reset signal can be changed
using FPGA programming.[4] In real system the timing of
impulse reset signal is setting to 1 second. The figure 3 shows
design block diagram of reset automatic block.[5]
Fig. 3 Design block diagram of reset automatic block
There are 2 blocks inside the reset automatic block using 30
bit output data for calibrate the timing in 1 second.[6] The
reset automatic consists of 30 bit binary up counter block and
30 bit comparator equal block. The timer of the reset
automatic block can be changed using time setting in data
comparator 30 bit input data in VHDL programming.[7] The
reset automatic will generate impulse reset data in width pulse
is 1 clock (1ns if 1clk=1ns) and width impulse to another
impulse is 535 ns depend setting of timing data (setting can be
changed).[8] Input clock of the 30 bit binary up counter is
using positive edge clock for counting data.[9] It means
counter start to increase up counting by 1 level when the clock
change from low (logic 0) to high (logic 1).[10]
A. The Flowchart of Reset Automatic Block
Figure 4 shows how to design flow chart of reset automatic
block in VHDL programming for PD detection circuit
system. The first time the FPGA programming check the
output comparator is high or low, if the comparator is high
then the reset of 30 bit binary counter will active and the
output of 30 bit binary counter return to zero again and
counting again, if the comparator is low then the reset of 30
bit binary counter will not active and the output of 30 bit
binary counter increase by 1 level. The second time the
FPGA programming check the output of 30 bit binary
counter is equal by 389ACA00 hex or not. If the output
counter is the same than 389ACA00 hex then the output
comparator is high (active), If the output counter is not the
16
same than 389ACA00 hex then the output comparator is low
(not active) and then the VHDL program returns again from
the start programming. The value of 389ACA00 hex is setting
of the repetition timer in 1 second of reset automatic block if
the clock of FPGA is 1 ns or 1 GHz, but if the clock of FPGA
is 10 ns or 100 MHz then the repetition timer of reset
automatic block is setting in 10 second.
Fig. 4 Design flow chart diagram of reset automatic block
B. Design Timing for Impulse Reset Automatic Block
Design 1 second in the 30 bit counter of reset automatic
block is:
If 1 clock is 1 ns so 1 second is 1000,000,000 ns and then:
1000,000,000 dec = 3B9ACA00 hex
The repetition period of 30 bit binary counter is 1 second
when Hex data is counting from 0000 0000 hex to 3B9ACA00
hex. The repetition period of 30 bit binary counter is 1 second
when Binary data (30 bit data) is counting from:
000000000000000000000000000000 bin to
111011100110101100101000000000 bin
or 0000 0000 hex to 3B9A CA00 hex
The 30 bit binary counter data is maximum when counting
from:
000000000000000000000000000000 bin to
111111111111111111111111111111 bin
or 0000 0000 hex to 3FFF FFFF hex
or 0 dec to 1,073,741,823 dec
So the designing result of the reset automatic block in the
comparator for repetition period in 1 second if the clock
FPGA is 1 ns as follows:
If input = 3B9A CA00 hex
Output = ‘1’
2010 IEEE Control and System Graduate Research Colloquium

The reset automatic block is set to 0000 0014 hex in repetition Figure 6 shows the block diagram of 64 bit latch block of PD
period 120 ns when the simulation testing. detection circuit in VHDL programming.
C. Simulation Result of Reset Automatic Block This is the Flowchart of The 64 Bit Latch Block:
1) Graphic Result of Simulation Reset Automatic Block:

Fig. 5 Simulation result FPGA for reset automatic block

2) Analysis Graphic for Simulation Reset Automatic Block:

The reset automatic block has generated impulse signal in
period repetition 120 ns when the timing is set in 0000 0014
hex. The Reset Automatic Block has been successful to
synthesis, compile, simulate and run in FPGA Programming.
Reset Automatic Block programming can work successfully in
FPGA Compiler. Figure 5 shows simulation result of reset
automatic block. The different between the signal reset
automatic for reset the 64 bit BCD counter and the signal reset
automatic for update data to the 64 bit latch block is the signal
reset for the 64 bit latch block lead 1 clock pulse than the
signal reset for the 64 bit BCD counter.
IV. THE 64 BIT LATCH BLOCK
The function of the latch block programming in this
detection circuit system is holding data from the output
counter and reset block to display when the counter block is
running. This will ensure that the display will keep the data to
constant when the counter block is reset and return to zero
again and counting again to update new data.
After finishing the process of the latch block, the output
data in this block will be sent to the driver of the LCD 16x2
character module.
Fig. 7 The flow chart diagram for the 64 bit latch block
Figure 7 shows the flow chart diagram for the 64 bit latch
block. The first time the FPGA programming set to the initial
mode in positive edge. It means counter start to increase up
counting by 1 level when the clock change from low (logic 0)
to high (logic 1). The second time the FPGA programming
check the (E) Enable is active (logic high) or not. If the E is
active, the 64 bit output data in Latch block will be updated by
the new data from 64 bit input data. If the E is not active, the
64 bit output data in Latch block will be kept by the old data.
So the 64 bit latch block will keep the data to constant when
the counter block is reset and return to zero again and then the
VHDL program returns again from the start programming.
A. Simulation Result of The 64 Bit Latch Block

1) Design Input Simulation for The 64 Bit Latch Block:

Fig. 6 Block diagram for 64 bit latch block

Fig. 8 The input design for simulation of the 64 bit latch block

17
2010 IEEE Control and System Graduate Research Colloquium

Figure 8 shows the input design for simulation of the 64 bit

latch block in programming.
2) Simulation Result for The 64 Bit Latch Block:

Fig. 10 The flow chart diagram of the complete combination block of PD

detection circuit system

VI. THE SIMULATION RESULT

Fig. 9 The simulation result of the 64 bit latch block

Figure 9 shows the simulation result of the 64 bit latch

block. The simulation result shows that the output data of the
64 bit latch block is kept to constant value when the enable
signal is low (0 Volt). The simulation result show that the
output data of 64 bit latch block is updated to the new data
when the enable signal is high (5 Volt). So in the simulation
result, if the Enable value is logic high then the output data of
latch block will be updated to the new data, but if the Enable
value is logic low then the output data of latch block is
constant.

V.THE COMPLETE BLOCK TESTING OF THE PD DETECTION

CIRCUIT SYSTEM
A. Flow Chart Design for Complete Bock of PD Detection
Circuit System
Figure 10 shows the flow chart diagram of the complete
combination block of the PD detection circuit system using
FPGA programming. If the input ADC push button is high
then the LCD shows the real time input signal from ADC
Fig. 11 The simulation result of the complete combination block of PD
board, If the input push button ADC is low then the LCD detection circuit system
shows the real time of PD detection counting.

18
2010 IEEE Control and System Graduate Research Colloquium
A. Analysis of The Simulation Result
TABLE II
ANALYSIS GRAPHIC SIGNAL FOR PEAK DETECTOR, 64 BIT BCD UP
COUNTER BLOCK, RESET AUTOMATIC BLOCK, 64 BIT LATCH
BLOCK IN SIMULATION FPGA.
Figure 11 shows the simulation result of the complete
combination block of PD detection circuit system. Table 2
shows the analysis graphical signal for the peak detector
block, the 64 bit BCD counter block, the reset automatic and
the 64 bit latch block in VHDL programming using Xilinx ISE
simulator version 10.1. The timing of reset automatic block is
set in 210 ns. One clock before reset is activated by reset
automatic block, the Enable has been activated by signal from
reset automatic block.
The output peak detector is logic 1 if the input ADC is
more than 2.8 V or 8F hex and logic 0 if the input ADC is less
than 2.8 V or 8F hex. The output 64 bit BCD counter is
increase by 1 level if the output peak detector is logic 1 and
the output 64 bit BCD counter is not change when the output
peak detector is logic 0. The output 64 bit BCD counter is
reset to zero if reset signal is active or logic 1. The output 64
bit latch block is update the new data if the Enable signal is
active or logic 1and the output 64 bit latch block is holding the
last data if the Enable signal is not active or logic 0.
VII. CONCLUSSION
The Combination of ADC and Peak Detector Block,
Counter and Reset Block, Reset Automatic and Latch Block
has been successful to synthesis, compile, simulate and run in
FPGA Programming together. The complete combination
block programming of PD detection circuit system can work
successfully in FPGA Compiler. The PD detection circuit has
19
been successful to process, detect and counting PD signal
from ADC board using simulation in Xilinx ISE simulator.
The output 64 bit BCD counter is increase by 1 level if the
output peak detector is logic 1 and the output 64 bit BCD
counter is not change when the output peak detector is logic 0.
The output 64 bit latch block is update the new data if the
Enable signal is active or logic 1and the output 64 bit latch
block is holding the last data if the Enable signal is not active
or logic 0.
REFERENCES
[1] Ahmad Basri bin Abdul Ghani, “Detection of Partial Discharge in
Underground Cable Using Magnetic Probe,” in 2008 Doctoral Thesis in
University Tenaga Nasional, Malaysia, 2008.
[2] Emilliano, Chandan Kumar Chakrabarty, Ahmad Basri, Agileswari K.
Ramasamy,” VHDL SIMULATION OF PEAK DETECTOR, BCD
COUNTER 64 BIT, RESET AUTOMATIC BLOCK FOR PD
DETECTION CIRCUIT USING FPGA”, International Conference 2010
6th International Colloquium on Signal Processing & Its Applications
UiTM and IEEE Control Systems Chapter, Malaysia Section, in
Malacca, Malaysia, 21-23 May 2010.
[3] Bill Schwartz, Michael Carfore, and Dr. Robert Qiu, “Ultra Wideband
Transmitter & Receiver Design,” in The REU Program of Tennessee
Technological University, July 27, 2005.
[4] Benjamin Nicolle, Mourad Zarour, William Tatinian, Gilles Jacquemod,
“System Design Oriented Low Noise Amplifier Modeling” in IEEE
2007
[5] S. Braun, F. Krug, and P. Russer, “A novel automatic digital quasi-peak
60detector for a time domain measurement system,” in 2004 IEEE
InternationalSymposium On Electromagnetic Compatibility Digest,
August 9–14, Santa Clara, USA, 2004.
[6] CISPR16-1, Specification for radio disturbance and immunity
measuring apparatus and methods Part 1: Radio disturbance and
immunity measuring apparatus. International Electrotechnical
ommission, 1999.
[7] L. Cohen, “Time-Frequency Distributions - A Review,” in Proceeding
of the IEEE, vol. 77, no. 7, pp. 941–981, 1989.[4] A. V. Oppenheim
and R. W. Schafer, Discrete–Time Signal Processing.ISBN 0-13-
214107-8, Prentice-Hall, 1999.
[8] M. S. Chong, “Partial Discharge Mapping of Medium Voltage Cables –
TNB’s Experience”, CIRED 2001, 18-21 June 2001, Conference
Publication No. 482 © IEEE 2001
[9] F.H Kreuger, “Discharge Detection in High Voltage Equipment”, A
Heywood Book, Temple Press Book Ltd, London 1964.
[10] Xilinx Tutorial Documentation, “ISE 9.1i Quick Start Tutorial”,
Copyright © Xilinx, Inc. All rights reserved, 1995-2007