MULTIPLE CHOICE QUESTIONS ON “SIGNAL DESCRIPTIONS OF 8086”

1. The clock rate of microprocessor 8086 is _________.

a) 5 MHZ
b) 8 MHZ
c) 10 MHZ
d) All of the mentioned

Answer: d
Explanation: The microprocessor 8086 is a 16-bit CPU available in three clock rates i.e. 5, 8 and
10MHz.

2. In which T-state does the CPU sends the address to memory or I/O and the ALE signal for
demultiplexing ________.
a) T1
b) T2
c) T3
d) T4

Answer: a
Explanation: During the first clocking period in a bus cycle, which is called T1, the address of the
memory or I/O location is sent out and the control signals ALE, DT/R’ and IO/M’ are also output.

 3. BHE of 8086 microprocessor signal is used to interface the_____

a) I/O
b) DMA
c) Even bank memory
d) Odd bank memory
Answer: d
Explanation: If BHE’=0, then it indicates the transfer of data over the higher order data bus i.e. D 8-
D15.  The higher order bus is interfaced to odd address bank memory when BHE’ is enabled.

4. Ready pin of a microprocessor is used______

a) To indicate that processor is ready to receive inputs outputs
b) To indicate that processor is ready to receive inputs output
c) To introduce wait states
d) To provide direct memory access.

Answer: c
Explanation: This input is controlled to insert wait states into the timing of the microprocessor.

5. The pins of minimum mode AD0-AD15 have _____ address and ____ data bus.
a) 16, 8
b) 16, 16
c) 8, 16
d) 8, 8
Answer: b
Explanation: The microprocessor 8086 has 20 address lines and 16 data lines. Out of 20 address
lines, 16 address lines are time multiplexed with data lines AD0-AD15.

6. The function of pins from 24 to 31 depend on the mode in which ____ is operating.
a) 80386
b) 80387
c) 8085
d) 8086

Answer: d
Explanation: The 40 pins of 8086 are divided into 3 categories. i. Common mode
signals                          ii. Minimum mode signals and iii. Maximum mode signals. Pin no’s 24 to 31
are different in 8086 when it is operating in maximum mode or in minimum mode.

7.  The _______ input is examined by a ‘wait’ instruction.

a) K

b) TEST
c) LOC
d) KIT

Answer: b
Explanation: TEST’ input is examined by WAIT instruction. When TEST’ goes low, execution will
continue, else, the processor remains in an idle state.

8. After reset execution starts form _______.

a) 00000H
b) FFFF0H
c) FFFFFH
d) 003FFH

Answer: b
Explanation: After reset processor starts execution from FFFF0H location where the processor
initialization codes are available.

9.  If there is an edge triggered input at NMI Pin causes_____ Interrupt.

a)  Type-0
b)  Type-1
c) Type-2
d) Type-3
Answer: c
Explanation: 8086 microprocessor has 256 software interrupts. INT00 to INT FF or Type-0 to Type-
255. Non maskable interrupt is also called as INT 2 or TYPE-2 interrupt.

10.  If MN/MX is low, the 8086 operates in _____ mode.

a) Minimum mode
b)  Maximum mode
c)  Both A and B
d) Control mode

Answer: b
Explanation: If MN/MX’ is tied to Ground, the 8086 operates in maximum mode and MN/MX’ is
tied to Vcc, the processor 8086 operates in minimum mode.

11. The RD, WR, M/IO is the heart of control for a _______ mode.
a) Minimum mode
b)  Maximum mode
c)  Both A and B
d) Control mode

Answer: a
Explanation: The minimum mode signals are HOLD, HLDA, WR’, M/IO’, DT/R’, DEN’, ALE,
INTA’.

12. If S’2 =0, S’1 =1, S’0 =1, what is the status of the microprocessor?

a) Interrupt acknowledge
b) Read I/O port
c) Write I/O port
d) Halt

Answer: d
Explanation:  Based on the status lines we can examine the state of processor.

13. Which of the following processor supports pipelined architecture?

a) 8080
b) 8085
c) 8086
d) 8008
Answer: c
Explanation: 8086 microprocessor supports pipelined architecture because of its predecoded
instruction byte queue; it can fetch the next instruction while executing the current instruction. 

14. In order to initiate the fetch cycle by BIU atleast _______ bytes of the queue must be
empty.
a) 1
b) 2
c) 3
d) 4

Answer: b
Explanation: The queue is updated after every byte is read from the queue but fetch cycle is initiated
by BIU only if atleast 2 bytes of the queue are empty and the EU concurrently executing the fetched
instructions.

“GENERAL BUS OPERATION”,” I/O ADDRESSING CAPABILITY”, “SPECIAL PROCESSOR ACTIVITIES”

1. _______locations are reserved for operation including jump to initialization programme

and I/O processor initialization.
a) 00000-07FFFH
b) 00000-003FFH
c) 00000-FFFFFH
d) FFFF0-FFFFFH

Answer: d
Explanation: In the 1MB of memory certain locations are reserved for specific CPU operations. The
locations from FFFF0H-FFFFFH are reserved for operations including jump to initialization
programme and I/O processor initialization.

2. _______ locations are reserved for interrupt vector table.

a) 00000-07FFFH
b) 00000-003FFH
c) 00000-FFFFFH
d) FFFF0-FFFFFH

Answer: b
Explanation: In the 1MB of memory certain locations are reserved for specific CPU operations. The
locations from 00000H-003FFH are reserved for Interrupt vector table. 8086 has 256 vector
interrupts and each interrupt is allocated 4 bytes of memory, therefore 256*4= 1024bytes i.e. 003FF.

3. A Maximum of ______ I/O devices can be interfaced with the CPU.

a)  64 Kbytes
b) 32 Kbytes
c) 16 Kbytes
d) 1 M byte
Answer: a
Explanation: The 8086 processor can address up to 64KB I/O byte registers. This means that a
maximum of 64 KB I/O devices may be accessed by the CPU.

4. _________ register is used as 16-bit I/O address pointer.

a) AX
b) BX
c) CX
d) DX
Answer: d

Explanation: The 16-bit register DX is used as 16-bit I/O address pointer, with full capability to
address up to 64K devices. 
  
5. After RESET, What will be the contents of CS and IP registers?
a) 0000H and 0000H
b) F000H and FFF0H
c) FFF0H and F000H
d) FFFFH and FFFFH

Answer: b
Explanation: After RESET execution starts from FFFF0H. During this period, all the internal
register contents are set to 0000H except CS is set to value F000H and IP to value FFF0H.

6. For TEST signal to be accepted, it must be low for atleast______ clock cycles.
a) 3
b) 4
c) 5
d) 6

Answer: c
Explanation: For the TEST’ signal to be accepted, it must be low for atleast 5 clock cycles. If TEST’
is 0, then the processor is in running state.

7. Byte data with even address is transferred on _________ data bus lines.
a) D0-D7
b) D8-D15
c) D0-D15
d) All of the mentioned.

Answer: a
Explanation: Out of 16 data lines, the lower order data lines D0-D7 are interfaced to even address
memory bank and the higher order data lines D8-D15 are interfaced to odd address memory bank.
1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned

Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the
operation code field.

2. A machine language instruction format consists of

a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned

Answer: c
Explanation: Machine language instruction format has both the fields.

3. The length of the one-byte instruction is

a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes

Answer: b
Explanation: This format is only one byte long.

4. The instruction format ‘register to register’ has a length of

a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes

Answer: a
Explanation: this format is 2 byte long.

5. The R/M field in a machine instruction format specifies

a) another register
b) another memory location
c) other operand
d) all of the mentioned

Answer: d
Explanation: The LSBs (least significant bits) from 0 to 3 represent R/M field that specifies another
register or memory location i.e. the other operand.

6. In a machine instruction format, S-bit is the

a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned

Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of
operation.

7. The bit which is used by the ‘REP’ instruction is

a) W-bit
b) S-bit
c) V-bit
d) Z-bit

Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.

8. If W-bit value is ’1′ then the operand is of

a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits

Answer: c
Explanation: If W-bit is ’1′ then the operand is of 16-bits, and if it is ’0′ then the operand is of 8-bits.

9. The instructions which after execution transfer control to the next instruction in the
sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned

Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution .

10. The instructions that transfer the control to some predefined address or the address
specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
Answer: b
Explanation: the control transfer instructions transfer control to the specified address.

11. The instruction “JUMP” belongs to

a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions

Answer: d
Explanation: the JUMP instruction transfers the control to the address located in the
instruction.

1. Which statement is correct?

a. 8086 is a 16 bit processor with 16 bit data bus
b) 8088 is a 16 bit processor with 8 bit data bus.
c) 80C86 is a cmos version of 8086.
d) 80c86 draws very less current when compared to
8086
e) All are correct  

2. In 8086, in maximum mode, there can be more than

one microprocessor in the system configuration.
a) true (correct answer)  
b) false

3. AD0-AD15 pins will act as address bus when

a)ALE is set to 1(correct answer)
b)ALE is set to 0

4. Which is correct regarding INTR interrupt in 8086.

a) When INTR=1 and IF=1, processor sends out INTA
signal
b) On receipt of INTA signal, the device places Interrupt
vector on data bus
c)  Both are correct (correct answer)
d) Both are wrong

5. Power supply for 8086 and 8088 is

a) 5V (correct answer)
b) 3v
c)10v

6. Data bus bits D8-D15 are enabled only if

a)BHE pin is enabled(correct answer)
b) BHE pin is disabled

8.  In 8086, ______ pin is used to insert wait states

(controlled by memory and IO for reads/writes) into  the
microprocessor.
a) READY (correct answser)
b) RESET
C) HOLD
9. In 8086, which is correct regarding RESET pin?
a)Processor resets if this pin is held high for 4 clock
periods.
b) IF flag is cleared.

10.in 8086,  Maximum mode is designed to be used

when a coprocessor (8087) exists in the system
a)true (correct answer)
b)false

1.  ______ is a Serial Data Transfer Technique.

a) Synchronous Data Transfer b) Asynchronous Data
Transfer c) Both a and b  d) Both are incorrect
Hint: Correct Answer: c: Sync and Async both are Serial  data transfers.

2. In _______ Data transfer, each character that is

transmitted is preceded by a START bit and ended with
STOP bits.
a) Synchronous b) Asynchronous  c) in Both Sync and
Async d) none of the above.
Hint: Correct answer: b:  Asynchronous data transmission means, only one character is sent at a
time. Each character is preceded by a Start bit (zero) and ended by a stop bit (one).

3. In _______ data transfer,  the transmitter and receiver

uses  Separate Clock Signals.
a) Synchronous  b) Asynchronous  c) Both are correct d)
Both are wrong
int: Correct answer: b: In case of Sync data transfer, both ends uses same clock signal. In Async
data transfer, both transmitter and receiver use separate clock signals. Eventhough both
transmitter and receiver uses same frequency (for eg.9600cycles), there can be a slight variation
between  their frequencies. Hence only one character is sent at a time and then stopped for a
certain time before sending the next byte. In case of async data transfer, both ends should be
configured identically as shown in the following screenshot.

4. To send out the data over serial line, computer

converts  the data from parallel to serial form using ___.
a) UART b) USART c) CRT  d) both a and b are correct
Correct answer; a and b hint: UART stands for Universal Asynchronous Receiver Transmitter. It
deals only with the asynchronous serial data transfer. uSART means universal Synchronous
Asynchronous Receiver transmitter. its deals both sync and async seial data transfer.

6.   In a microprocessor, data transfer between

Registers or data transfer using DMA  happens using
______   data transfer.
a) Serial b) Parallel
Correct answer: b:Parallel.  hint; With in the computer, data bus is present.   hence the data
transfer between main memory to hard disk happens in parallel mode.

7._____ data transfer  means transferring data serially

bit by bit.
a) Serial b) Parallel c) both are correct d) Both are
wrong
Hint: Correct answer is a

8. In case of ________ data transfer, same clock signal

is used both by Transmitter and Receiver.
a) Synchronous  b) Asynchronous
Correct Answer; a

9.In Interrupt driven data transfer, ____initiates the data

transfer.
a) Device b) Processor
Hint:    In Interrupt driven data transfer (Interrupt Driven I/O) , the device initiates the data
transfer(for example,  a robot is moving. When it detects an obstacle, the sensor  initiates the
action by sending an interrupt signal to the processor and the processor handles this request.

10. In Program based data transfer, ________ initiates

the data transfer.
a) CPU b) I/O Device
hint: Take the example of moving robot. In program based data transfer (Programmed I/o), the
CPU  checks the sensor reading periodically. If the cpu senses an obstacle, it takes some action.
Otherwise loop back again and again continuously  and check the sensor reading.  As the CPU
checks a number of devices in this manner, it is also called as POLLING BASED data transfer.
11. In 8086  ______ number of software interrupts are
there.
a) 8 b) 256 c) 1  d) 2
hint: There are 256 software interrupts in 8086.  ie INT 00 to INT FF  ( in 8085 only 8 software
interrupts INT 0-7)

12. DMA stands for  _____________

  a) Dia Magnetic Array  b) Magnetic Disk Array c) Direct
Memory Access
hint: correct answer:c.
13. Direct Memory Access  is controlled by  __________
a) ALU  b) BC Register c) DMA Controller
correct answer: c

14. If the amount of data to be transferred is huge and at

the same time, the involvement of CPU should be less,
then  ______ method of  data transfer is most suitable?
a) DMA b) Interrupt Driven  c) Program based
Correct answer: a

15. When a device ( such as hard-disk) is able to

transfer data directly to memory   directly acting like a
DMA Controller (without the help of any DMAC, this
technique is called as___
a) self addressing b) Bus Mastering c) interrupt driven
Correct Answer: b:bus mastering ; hint: using DMA Controller is a old technology. The DMA
technique is inbuilt into the devices like harddisk,etc. and these devices behave like master of
bus. hence it is called as Bus mastering.

16.  Which is correcting regarding  memory mapped i/o

when compared to  i/o mapped i/o?
a) Faster b) Many instructions supporting memory
mapped i/o c) Require a bigger address decoder d) all of
the above
correct answer; d : all are correct.

16. In _______mode of data transfer , DMA take over

the bus for each byte of data to be transferred and
return the control to CPU.
a) burst mode  b) byte mode c) cycle stealing mode
Correct answer; c)cycle stealing mode. In case of burst mode, a block of data is transferred
before returning the bus control to CPU.

17.  When the  CPU and I/O device match in exactly

same speed, _____ data transfer technique can be
used.
a) Synchronous b) Asynchronous
Correct answer : a

18.  The IN instruction is used to read  data from an I/O

device to the CPU. For this instruction to work both the
CPU and the device are to be connected in
_________transfer mode.
a) Synchronous b) Asynchronous
Hint: IN and OUT instructions are used in synchronous mode of data transfer. But, for a sync
data transfer, both cpu and device should work in same speed. Normally,  I/O devices are much
slower than CPU. Hence this instruction ( ie IN and OUT) is rarely used.

19. IN and OUT instructions are used in ____ mapped

I/O devices.
a) I/O mapped  b) Memory mapped
correct answer: a

18.  In 8086 what is the instruction to read an ascii

character from keyboard (let keyboard i/o port no. be
20H)?
a) IN AL 20H  b) OUT AL 20H
Correct Answer : a

19. Interrupt Driven Data transfer is based on ______

concept.
a) on-demand b) off-demand
correct answer; a . Read the hints in question no. 9 .

20. ______ is used as Programmable DMA Controller. 

a) PIC 8259   b) 8257    c) 8086   d) 8088
correct answer: b. 8257 is a programmable DMA controller. It is able to transfer data  directly
between I/O devices and Memory. (Note 8257 is a programmable Interrupt Controller,  8255 is
programmable peripheral interface)

21. When DMA Controller needs the bus, it sends a

request to the processor through HOLD line. The
Processor may acknowledge this request through ____
line.
a) WR  b) RD  c) INTA d) HLDA
correct answer: d. HLDA means Hold Acknowledgement.

22. In 8086, _____ signal is sent out by the CPU to

prevent  Bus Masters  getting the System Bus.
a) LOCK(bar)   b) HOLD  c) HLDA
correct answer: a:lock(bar)

23. ______ signal received by the processor indicates

that a Bus master requests for the use of  System bus
(ie. address bus,control bus and data bus)
a) INTR b) INTA c) READY d)HOLD
correct answer; d.

24. When the speed of the processor does not match

with the speed of  I/O device, then ____ mode of data
transfer  is used. In this mode, the processor initiates the
data transfer (eg. IN 24H) and waits for the  READY
signal from the I/O and the data transfer is executed.
a) sync b) async
correct answer; async

25. In case of ____ data transfer mode, both processor

and the I/O device are synchronized with the same
clock. In this case, the CPU will not check whether the
device is ready or not for the data transfer.
a) sync  b) async
correct answer: sync

26. The advantage of memory mapped I/O over I/o

mapped I/O is
a)faster
b) Many instructions supporting memory mapped i/o
c) required a bigger address decoder
d) all the above
27. Which of the following is NOT an enhancement to
the Pentium that was unavailable in 8086/8088?
a) Pipelined Architecure
b)Expansion of cache memory
c) Inclusion of an internal math coprocessor
d) Data/address line multiplexing
correct answer: d. data/address line multiplexing
Note:8086,8088,80286,80386,80486 needs separate coprocessor. But
Pentium has inbuilt coprocessor
Pentium has two internal cache memory where as 8086 has not.
Both penitum and 8086 are of  pipelined architecture

28.Which of the following is not an element of

microprocessor?
a). Microcontroller
b) ALU
c) Register array
d) Control unit 
29. Which method bypasses the CPU for certain types
of data transfer?
a) Software interrupts
b) Interrupt-driven I/O
c) Polled I/O
d) Direct memory access (DMA)

correct answer d. dma

 30.  Pentium can address _____ memory locations
a) 1mb
b)1gb
c)2gb
d) 4gB
corect  answer: d. pentium has 32 bit address bus. 2^32
equals to 4 gB
31. Petium prcoessor has a data bus of _____
a) 18 bits
b) 32 bits
c) 64 bits
d( 128 bits

correct answer: c  64 bits.

32. In 8086 are of the following statements is true?

a) In 8086 , Co processor is interfaced in max mode
b) In 8086, Co processor is interfaced in min mode
c)  8086 Supports pipelining
d)  a and c are correct
Hint: Min Mode means Minimum mode. Which means other processors cannot be connected

33. How many buses are  there in 8085

microprocessor?
a)1
b)2
c)3
d)10
Hint: Address bus, data bus and controlled bus. collectively called as system bus .
33. Which bus is a bidrectional bus?
a) address bus 
b) data bus 
c) address bus and data bus 
d) none of the above
Hint: cpu will read as well as write on the data bus

34.Why 8085 processor is called an 8 bit processor?

a) Because it has 8 bit ALU
 b) Because it has 8 bit data bus 
c) both a&b 
d) none of the above

35. Which memroy has faster Acess time ?

a) ROM
b) SRAM 
c) DRAM 
d) EPROM
Hint.SRAM is faster because it does not have refresh cycle.  then DRAM, then ROM
Generally, sram is 5 nano sec, dram is 50 nano, flash is 65 nano, rom is 250 nano sec
Cache memories are made up of SRAM

36. BHE of 8086 microprocessor signal is used to

interface the
a) even bank memory 
b) odd bank memory 
c) I/O d) DMA
Hint: 0-bank=even bank=lower bank, 1-bank=odd bank=upper bank.
BHE interfaces the upper bank (aka odd bank) memory.

37. The advantage of memory mapped i/o over i/o

mapped i/o is
a) Memory mapped io is Faster 
b) Many instructions supporting memory mapped i/o 
c) Require a bigger address decoder 
d) all of the above
38. In 8086 microprocessor which interrupt has the
highest priority 
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW