PT2010 VSD530

M.S RAMAIAH SCHOOL OF ADVANCED STUDIES

POSTGRADUATE ENGINEERING AND MANAGEMENT PROGRAMME (PEMP)

Department : Electronics and Computer Engineering

Course : M.Sc.[Engg.] in VLSI System Design
Module Code : VSD530
Module Title : Reliable Power Aware ASICs
Module Leader : Selva Kumar R.

Assignment

INSTRUCTIONS TO CANDIDATES:

1. The assignment consists of three parts and all of them need to be answered
2. The weightage for the three parts are
• Part A : 30
• Part B : 30
• Part C : 30
• Others : 10
3. The assignment has to be word processed and submitted in the standard format specified by the ARO,
MSRSAS
4. The report should not exceed 35 pages
5. Submission Date : 7th January 2011
6. The industry standard simulation, synthesis, DFT and STA tools from Synopsys should be used for
solving the assignment. The demos for the tools will be given during the module
7. All the units of measurement wherever applicable should be SI Units only
8. Evaluation is based on comprehension of the question, style of presentation, originality, logical thinking
and justification of the results obtained
9. The assignment should be carried out individually and the report submitted and demonstration given
should reflect the individuals work and should be expressed completely in the student’s own words
10. All references must be indicated clearly and all figures referenced properly
11. All the necessary diagrams / schematics / simulation and synthesis reports are to be incorporated at
appropriate places with relevant explanation. The results, advantages and disadvantages should be clearly
mentioned

November 2010

Form – 43 Ver: 1 Date: 01-11-2007

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PT2010 VSD530

Introduction
The relevance, reach and capabilities of VLSI system have been quite obvious for some time now. With diverse
means of realizing VLSI chips such as FPGA, Full Custom, Semi-Custom available, engineers and engineering
companies have plenty of choices ahead of them. With rapid changes in lifestyles and technological advances the
problems today are pretty complex and require equally intricate and efficient solutions. As an answer to present-
day needs and with the percolation of VLSI systems into the Very Deep Sub Micron technologies today millions
of transistors are accommodated on a single chip to support complex applications, which were usually
implemented on general-purpose processors. The exponential raise in the number of transistors increases the
difficulty of implementing the solutions. FPGAs have come up short when dealing with millions of transistors
and Full Custom by virtue of being “Full” can at times be slow for implementing the designs and meeting today’s
rapid demand for instant results. In such a scenario semi-custom ASIC design solves almost all the problems and
is found to be capable to answer all technological demands efficiently and in time. Also with the advent of
competent EDA tools a major burden has been reduced from VLSI engineers’ in implementing any given device.
This module prepares the delegates to design and analyze reliable & power aware ASICs using industry practices
and methodologies. Salient features of logic optimization, shortcomings of HDL coding and solutions for
achieving optimal synthesis will be discussed with relevant case studies. Delegates will be taught Design for
Testability (DFT), Static Timing Analysis (STA) and low power synthesis. Delegates will be trained on the usage
of industry standard software tools – Design Compiler, PrimeTime, TetraMax and VCS – for synthesis, STA,
testing and simulation of digital designs
The assignment given tests the delegate’s understanding of the fundamental concepts of ASIC design, the
knowledge and skill developed during the module on synthesis of a given code and testability and timing analysis
of the generated netlist.
Part A will challenge the students’ inquisitiveness in learning new topics and keeping themselves updated with
latest trends in the world.
Part B & Part C improves the students understanding of the various steps involved in the ASIC front end design
process and usage of Synopsys Tools to implement any application based complex circuit. It also tests their
ability to design, develop and analyze complex digital circuits.

Part A : Will designing ASICs, using the Full Custom flow, still remain an enticing
option for digital designs?
Introduction:
Current VLSI Chips have over a billion Transistors. The complexity of the designs has been beyond
comprehension and expecting the designs to be done from scratch as in the golden days is no more an
enviable option. With a multitude of IP cores available to make the life of designers much easy,
designing a complex VLSI IC hardly is a matter of week’s jobs now when compared to the years of
effort in the day’s bygone. The IP cores which need to bought only once can then be reused any number
of times.

Problem Statement:
With the emphasis on IP reuse increasing in the current scenario, prepare a three-page report debating
on “Will designing ASICs, using the Full Custom flow, still remain an enticing option for digital
designs?” Justify your answer considering the following aspects Cost, Design Time, Power
consumption, Area, Man Power, Speed, Application, Resources required, Life cycle of the product,
Flexibility, Tool Support, Limitations, Development time, improving productivity, Advantages and
disadvantages of using full custom flow

Guidelines:
• The report should be expressed completely in the student’s own words
• The report should not exceed three A4 size pages

Form – 43 Ver: 1 Date: 01-11-2007

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PT2010 VSD530

Part B: ASIC Implementation of Multi-Channel UART

Introduction:

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of

the serial communications subsystem of a computer. The UART takes bytes of data and transmits the
individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into
complete bytes. Serial transmission of digital information (bits) through a single wire or other medium
is much more cost effective than parallel transmission through multiple wires. A UART is used to
convert the transmitted information between its sequential and parallel form at each end of the link.
Each UART contains a shift register which is the fundamental method of conversion between serial and
parallel forms.

The Multi-channel UART is a FPGA core that implements up to 16 UARTs in a single FPGA
device. These UARTs are completely independent in functionality, but share common logic to reduce
their overall size compared to individual instantiations. Each UART channel is similar to the industry
standard 16550 device and is an upward solution to standard UARTs by providing FIFOs in both
transmit and receive paths.
Problem Statement:
In this part of the assignment, the students need to identify the resourceful synthesis methodologies and
techniques for implementing Multi-channel UART (Verilog code from solution of Part B VSD529
module assignment). Using relevant scripts the Verilog model should be synthesized to meet the
targeted specifications. Static Timing Analysis should be carried out on the netlist to prove that it is
timing clean. The HDL should be simulated in an industry standard simulator and then synthesized to
meet the following specifications.
Specifications:
Frequency : Min 500 MHz
Leakage Power: 20μw
The 65nm multi VTH, multi VDD, TSMC process should be used for synthesis
Guidelines:
Find out the following and report the same in your assignment:
1. Modified Block diagram and explanation of Multi-channel UART.
2. Synthesis and analysis of results obtained along with relevant screen shots.
3. Synthesize the design using multiple threshold voltages to achieve minimum leakage power.
4. Critical analysis of the synthesis process and results obtained therein.
5. Explanation of constraints along with their significance to the design
6. Post-synthesis simulation of the design
7. Comparison of synthesis results obtained from ASIC tools with that obtained from FPGA synthesis
tools.
8. A demonstration should be given to the module leader
9. The synthesis process should be automated using script files.

Part C: Low Power Implementation and DFT for Multi-Channel UART :

Introduction:
With the current economic semiconductor companies are facing tough times due to lesser design start-
ups. With companies competing with each other to retain their market share the quality and reliability of their
products needs to be of the highest standards. The necessity for an IC to be thoroughly tested and hence the need
for Design For Testability (DFT) could not have been more acute than in such times.

Form – 43 Ver: 1 Date: 01-11-2007

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PT2010 VSD530

Also with the need for efficient usage of power becoming more of important, low power design
methodology has already become a part of the mainstream design process.

Problem Statement:
In this part of the assignment the student needs to identify the best possible DFT methodology with also
focus on low power for the Multi-channel UART designed in Part B. The design should be able to meet the
following specifications
Fault Coverage : 98.5%
Dynamic Power : <10μw

Guidelines:
The following should be performed and reported in the assignment
1. Low power analysis using VCD/SAIF files on the netlist obtained from Part B above
2. Analysis of low power methodologies and DFT techniques
3. Implementation of suitable low power methodology on the Multi-channel UART design
4. Analysis of power savings obtained due to the low power technique used
5. Implementation of suitable DFT technique on the design and analysis of Fault coverage
6. Power analysis of inserted Test logic
7. Highlight the effect of Low Power methodology on timing and testability of the design
8. A demonstration should be given to the module leader explaining the basic concepts of Low Power and DFT
techniques

Guidelines for Submission

• Your assignment should consist of three chapters only, each chapter/part should have the following:
Strictly follow the below guidelines:
o Introduction (written in your own words-the contents/words/sentences/paragraph should not
match with any web/book resources/other assignments)
o Literature review and Design details – should be original contribution, you can make suitable
changes with existing design available, need to mention the same in your assignment
o Simulation / Implementation results – should be explained in detail in your own words
o Discussion on results with proper recommendations – explain in your own words taking more
test results from the simulation or from other journals
o Conclusion (Every chapter/part should have separate conclusion)-explain in your own words
• You need to have one abstract for the entire assignment, highlighting the scope of the work done, results
obtained, major contributions
• References should be in proper format as specified in the student handbook
• Add acknowledgement wherever required
• Results obtained from simulation /synthesis tools needs to be included in your assignment with proper
formatting. The results should reflect your work done and the contribution
• Graphs, Tables and comparison results should be neatly plotted and compared. Discussion on the results
obtained would fetch maximum marks
• Results should be demonstrated to the module leader

Form – 43 Ver: 1 Date: 01-11-2007

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Marking Scheme
Question No Marks
1 Cost, Design Time 3
2 Power Consumption, Area and Speed 5
3 Application, Resources required, Life cycle of the 6
product and Flexibility
Part A (30 Marks) 4 Tool Support, Limitations, Development time and 6
improving productivity
5 Advantages and disadvantages of using / not using 5
full custom flow
6 Originality and Grammar 5
1 Explanation of Architecture 2
2 Simulation and Analysis 2
3 Synthesis and discussion of constraints 7
Part B (30 Marks)
4 Post Synthesis simulation and generation of VCD files 3
5 Static Timing Analysis 6
6 Documentation, Demonstration and Viva 10
1 Low power analysis using VCD/SAIF files 2
2 Discussion of low power & DFT techniques 4
3 Implementation of low power methodology 6
Part C (30 Marks) 4 Analysis and results of low power technique used 2
5 Implementation of DFT and analysis of Fault coverage 4
6 Power analysis of inserted Test logic 2
7 Documentation, Demonstration and Viva 10
Abstract, Conclusions, References, Formatting, Assessment of 10
Others
module learning outcomes

Form – 43 Ver: 1 Date: 01-11-2007

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