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Advances in Logic Device Scaling

Anil Kumar Bansal & Abhisek Dixit

To cite this article: Anil Kumar Bansal & Abhisek Dixit (2015) Advances in Logic Device Scaling,
IETE Technical Review, 32:4, 311-318, DOI: 10.1080/02564602.2015.1023372

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 Advances in Logic Device Scaling
Anil Kumar Bansal and Abhisek Dixit
Integrated Electronic Circuits Group, Department of Electrical Engineering, Indian Institute of Technology Delhi Hauz Khas,
New Delhi 110016, India

ABSTRACT
Major industry trends that have the potential to take logic device scaling to the next level are reviewed in this
article. Contemporary device designs competing for mainstream in future complementary metal oxide semi-
conductor (CMOS) nodes have been discussed. Recent advances in process modules such as gate, channel,
and source/drain are discussed. Impact of these advanced process modules on device performance and
short channel control has been briefly reviewed. Furthermore, status of variability in terms of known as well as
new sources is reviewed. We find the introduction of extreme ultraviolet lithography and 450-mm wafer size as
two upcoming challenges and gate-all-around architecture with Si and III V nanowires as the most natural
extension of existing technology for next CMOS node at 7 nm.
Keywords:
CMOS, FinFET, Logic, Nanowire, Scaling, Variability.

1. INTRODUCTION sub-193-nm optical lithography. As these next genera-

With increasing penetration of hand-held devices,
such as tablets and cell phones, standby leakage reduc-
tion is of utmost importance in integrated circuits (ICs)
designed for mobile applications. At the same time,
device designs for even high performance applica-
tions, such as servers, have to achieve standby leakage
reduction due to package maximum temperature
restrictions. While most of the recent mobile logic
designs are on 32- and 28-nm bulk complementary
metal oxide semiconductor (CMOS), majority of the
microprocessors are being fabricated in 22-nm bulk
and silicon on insulator (SOI)-CMOS. From current
industry trends, it is evident that a shift from planar
MOSFET device design to multigate FinFETs is near
complete at 22- and 14-nm nodes, with 14-nm FinFET-
based designs hitting the market as early as 2016. The
fin-type architecture is well known to have superior
gate control over the short channel, thereby achieving
low sub-threshold leakage at short channel lengths as
compared to planar MOSFETs. In this paper, logic
device scaling is reviewed and future challenges are
discussed. This review report is organized in the fol-
lowing sub-topics: (1) industry trends, (2) advanced
devices, (3) gate engineering, (4) source/drain engi-
neering, (5) channel engineering, and (6) variability.
2. INDUSTRY TRENDS
As CMOS device is scaled below 22-nm node, pattern-
ing for some of the process modules such as fin,
gate, and contact to active gets tougher. Primary
reason for this added complexity is requirement for
tion lithography tools are still under research and
development, industry is surviving with mostly dou-
ble and at times multiple patterning steps using 193-
nm high numerical aperture immersion lithography.
Requirement for cumbersome resolution enhancement
techniques and optical proximity corrections at these
nodes with 193-nm lithography adds to the process
complexity overhead and further shrinks profit mar-
gins. The extreme ultraviolet lithography (EUVL) is
generally considered as the technology to take over
from 193-nm immersion lithography, but has been
delayed due to a number of critical problems that
remain to be solved. Compared to 193-nm immersion
lithography, EUVL uses 13.5 nm as exposure wave-
length, requiring the optical path to change from clean
air (in case of 193-nm) to ultra-high vacuum [1].
Such 15£ reduction in wavelength (from 193 to 13.5 nm)
significantly extends resolution capability. Before
EUVL can be introduced as a manufacturable alterna-
tive to 193-nm immersion lithography, a number of
critical challenges still need to be resolved: (1) EUV
source power at wafer level needs to be increased by
an order to increase throughput for cost feasibility, (2)
the defect density on the reflective masks has to
become low enough to yield functional ICs, and (3) the
resist technology needs to further improve to allow
successful integration in advanced process flows,
delivering the expected resolution, line edge rough-
ness (LER), and productivity [1].
In addition to shifting from 193-nm to EUVL, a transi-
tion from 300-mm wafer size to 450-mm is also

IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015 311

 Bansal A K and Dixit A: Advances in Logic Device Scaling
probable due to cost feasibility. The 450-mm transition
is a great opportunity to reduce the die cost and stimu-
late another wave of equipment and manufacturing
innovations. There are many challenges ahead for the
450-mm transition including innovations for tool
productivity, uniformity, precision, cost-of-ownership
reduction, green concept designing tools, and advanced
manufacturing systems. According to the G450C indus-
trial roadmap, R&D tools will be ready in 2015. Tools
for IC maker pilot line will be ready in 2016 and tools
for high volume manufacturing ready in 2018 [2].
3. ADVANCED DEVICES
As the channel length shrinks, the gate loses control of
the short channel and a leakage current flows between
source and drain while the MOSFET is in off state.
Scaling of gate dielectric thickness using high-k dielec-
trics can control this short channel effect to some extent
but beyond 22-nm CMOS, it is not enough as the gate
cannot control leakage paths which are far from it.
Gate-all-around (GAA) FETs emerged out as a best
candidate for future high performance and low power
logic applications because they have excellent electro-
static control of the channel [3,4]. Room temperature
electron and hole transport in high performance short
channel silicon nanowire (NW) MOSFETs has been
studied. It has an interesting observation that NW-
PFETs have 25% higher saturation drain current (Ion)
than NW-NFETs. To investigate this, room tempera-
ture transport of electrons and holes in Si NW-MOS-
FETs with effective diameter and gate length down to
8 and 25 nm, respectively, has been analysed. The
result shows that holes in Si NW along the h110i direc-
tion have higher thermal velocity and lower conduc-
tivity effective mass than electrons [5].
Using stress memorization technique through a dis-
posable silicon nitride (SiN) on the gate in 10-nm NW
transistors, significant parasitic reduction and mobility
enhancement has been achieved. In addition, a thin
box in this structure offers sufficient body effect and
hence enable threshold voltage (Vt) tuning [6]. To fur-
ther improve the device performance, a high-mobility
semiconductor material is required, such as InGaAs
for n-type and Ge for p-type transistors. In a novel
architecture, Ge p-channel FinFETs were fabricated on
a Si bulk FinFET baseline using aspect-ratio-trapping
(ART) technique. In ART technique during heteroge-
neous epitaxial growth inside trenches, the height to
width ratio of the heterogeneous epitaxy region is
larger than 1.4. Due to this, threading dislocations in
narrow trenches originating from interface will termi-
nate at the shallow trench isolation sidewalls leaving
the top part defect free for device simulations. Results
show that Ge FinFET has the best ratio of
312
transconductance in low drain bias regime to sub-
threshold slope (SS) in high drain bias regime (gm
/SSsat) of relaxed Ge FinFET devices reported to date
[7]. Recently, transition metal dichalcogenides (TMD)
are emerging as an alternative to silicon material. It is
made up of a series of 2D semiconducting layers
arranged in hexagonal lattice and exhibits a band gap
of 1.1 1.2 eV. TMD could be a potential channel mate-
rial for low power digital applications [8]. A new
advanced device which uses polarity control techni-
ques to switch between PMOS and NMOS is as shown
in Figure 1. In this ambipolar device, two gates are
used: a control gate for switching the device on or off
and a polarity gate for switching the device polarity
dynamically between n- and p-type. As a result, this
device shows potential for logic design [9].
For CMOS logic applications, high performance and
low power are the two essentials requirements. The
tunnel FET (TFET) as shown in Figure 2 is emerging as
a promising choice for benchmarking beyond CMOS
devices. In a TFET, we arrange semiconducting mate-
rial in p i n and n i p configurations. The i stands
for “intrinsic”, and it corresponds to the maximum
resistivity that a semiconductor can have.
In the off state, a thick energy barrier is formed so that
charge carriers in the source are unlikely to traverse.
By applying a voltage to the transistor gate, it causes
the conduction band in the source and the valence
band in the channel to overlap and hence opening up a
tunnelling window for an electron from valence band
of source to the conduction band in the channel. TFETs
should be able to switch with a much smaller voltage
swing than MOSFETs because only enough voltage to
create or remove an overlap of the bands is to be
applied. Since carriers flow due to tunnel phenomenon
as compared to thermionic emission, SS below 60 mV/
decade can be achieved. TFET is particularly a poten-
tial device for replacing CMOS as it stands out in both
delay and power criteria in NAND and adder circuits
[10]. The drawbacks associated with TFET are low
Figure 1: Structure of ambipolar silicon NW device.
IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015
 Bansal A K and Dixit A: Advances in Logic Device Scaling
Figure 2: Structure of TFET along with energy band dia-
gram in off and on state.
on-state current due to low tunnelling efficiency and
randon variability in device performance due to ran-
dom dopant fluctuation (RDF). It has been reported
that dopingless TFET provides immunity to RDF due
to absence of dopant atoms and an increase in on-state
current by using strain, high-k dielectric, and narrow
band gap materials [11].
To take advantage of high intrinsic transconductance
in advanced devices, series resistance due to source
and drain (S/D) contacts must be low. With raised S/D
architecture and optimized silicides, specific contact
resistance can be reduced. However, reduction in the
sheet resistance due to S/D extensions seems more dif-
ficult to achieve. To have strong short channel control,
shallow extensions are required. Since a decrease in
junction depth causes increase in sheet resistance, an
increase in extension doping concentration is required
to keep the sheet resistance low. The ultimate goal of
this research has been to realize highly doped shallow
S/D extensions and hence the junction technology is
regarded as a critical issue. Junctionless- FET (JL-FET)
has been proposed as a solution to this problem.
JL-FET is considered a “gated resistor” that is identi-
fied by the absence of S/D p n junctions as shown in
Figure 3 [12]. The turn-on and -off process is accom-
plished by body depletion. Current flow in a JL-FET is
controlled by formation of depletion layer induced by
the gate voltage. In the on state, there is a large current
flow due to the high doping concentration of channel
region to which surface accumulation current can be
added. In the off state, there is no current flow because
of the depletion of charge carriers in the channel region
due to the work function difference between the gate
material and substrate material together with voltage
applied at the gate. Also, JL-FET has been reported as
IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015
Figure 3: Junctionless-FET structure (a) on state and (b) off
state.
an alternative to conventional MOSFETs due to poten-
tial advantages such as higher mobility and lower gate
capacitance. Along with these advantages, JL-FET has
the drawback of high variability in device performance
due to their intrinsic high bulk doping level. Recently,
a number of reports on modelling of the variability of
JL-FETs have been published [13].
4. GATE ENGINEERING
Replacement metal gate (RMG) process, essentially a
gate last process, has mostly replaced the gate-first
process since sub-22-nm node. The RMG flow uses
gate fill process with low resistance materials on top of
work function tuning metal. In these RMG processes,
Ti layer deposited by physical vapour deposition
served as a suitable wetting layer. A wetting layer is
needed for Al to flow into the open spaces to fill the
gates. But the Ti wetting layer should maintain a cer-
tain minimum thickness to provide feasible wettability
for Al reflow to occur. This minimum thickness pre-
vents the Ti layer to go below 25 nm. Therefore, for
extreme scaling, i.e. at 25 nm or below Lgate, a novel
Co Al based metal fill scheme was reported [14].
Lower resistance with much less variability than con-
ventional Ti Al fill was achieved with Co Al fill
option. In addition, it provides matched device charac-
teristics and less gate leakage variability than RMG
gates with Ti Al fill.
In advanced CMOS devices, reliability of high-k/
metal-gate (HK-MG) emerges out as a key issue.
313
 Bansal A K and Dixit A: Advances in Logic Device Scaling
Reported results show that when a 150-nm thick TaN
gate layer is deposited on HfO2 dielectric, a peak stress
of about 3.28 GPa is generated, resulting in significant
trap generation in the high-k layer. The graphene gate
electrodes could be an excellent alternative in improv-
ing reliability of the HK-MG stack [15].
Challenges in HK-MG devices are equivalent oxide
thickness scalability with controlled effective work-
function (EWF), gate leakage density (JG), and on the
variability and reliability of these scaled devices. In
RMG high-k last flow devices, a tight distribution of
low Vt NMOS for Lgate  35 nm is attained by con-
trolled EWF metal alloying. Also a low gate resistance
(Rgate) and small Rgate distribution down to 20 25 nm
critical dimension was achieved with tuned Al liner/
barrier [16].
Self-aligned contacts emerge as a key aspect to enable
scaling to go below 22-nm technology node. In self-
aligned contact process, gate material is recessed past
planarization. Then a silicon nitride etch stop layer is
deposited and planarized. This is followed by a cap-
ping layer deposition prior to contact patterning.
Finally, the contacts are etched selective to the silicon
nitride to avoid gate shorts [17].
5. SOURCE/DRAIN ENGINEERING
The on-state channel resistance of MOSFETs has been
continuously lowered with scaling and strain engi-
neering, which has led to external resistance (Rext) as
the dominant component of the series resistance that
limits MOSFET performance. Main contribution to
Rext is the S/D contact resistance. There are number of
ways through which this S/D resistance can be han-
dled. A new contact technology comprising shallow
co-implantation of Sb, As, and Ge has been proposed.
It greatly reduces the Schottky barrier height (SBH)
and parasitic series resistance for n-FinFET, which
resulted in an increased Ion [18].
The interface resistance (Rco) between the S/D region
and the metal silicide layer is also a critical contribu-
tion to Rext. For future FinFET transistor, metal-inter-
facial layer semiconductor contact technology scales
better than silicides. By inserting an ultra-thin dielec-
tric layer of TiO2 having low conduction band offset
and tunnelling mass (mTunnel) between the metal and
semiconductor interface, lowering of Rco can be
achieved. A record low specific contact resistivity of
9.1£10¡9 ohm-cm2 and low 
SBH of 0.15 eV is achieved
for Ti metal using 10 A thick TiO2-x interlayer [19].
For n-Ge, nC-ZnO interlayer greatly reduces the
specific contact resistance and gives highest current
density [20].
314
In FinFETs, a good sidewall doping is required in S/D
extensions for low resistance. This can be achieved by
conventional beamline ion implant (I/I) with large tilt
angles for isolated fins. In real technologies with multi-
fin devices, use of large tilt results in implant shadow-
ing by adjacent fins. To eliminate this problem, ion
assisted deposition and doping (IADD) is used which
uses simultaneous dopant deposition and knock in. In
one of the examples, AsC and AsxHyC ions, which are
extracted from plasma source, are directed to the
wafer. As shown in Figure 4, ion assisted deposition of
arsenic and the knock in of this deposited As by ener-
getic AsC are the two main processes of IADD through
which a superior sidewall doping can be achieved
even with low tilt implantation [21]. Another method
to boost performance of n-FinFETs is by P SiC epitax-
ial growth on S/D. It provides strain to boost n-FinFET
mobility and drive current. Due to small gate pitch in
14-nm CMOS and beyond, contact etch stop layer loses
stress efficiency but P-SiC S/D can still maintain
mobility enhancement. Laser annealing and low tem-
perature rapid thermal annealing is necessary to retain
stress of P SiC epitaxial layer [22].
6. CHANNEL ENGINEERING
The main emphasis of channel engineering is on
improving the channel mobility and quality of the MOS
interface. Among the techniques that are generally used
for improving the channel mobility are strain engineer-
ing and use of high mobility Ge/III V channel materi-
als. In the past decade, strain technology has played a
key role in improving transistor performance. A great
deal of work has already been done and reported in
this field. Using group IV (C, Si, Ge, and Sn) elements
for stress enhancement is more prevalent as it provides
Figure 4: (A) Deposition and (B) knock-in doping process
of IADD in fin sidewall.
IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015
 Bansal A K and Dixit A: Advances in Logic Device Scaling
low-cost and manufacturable solutions, e.g. FinFET on a
strain relaxed buffer (SRB). For Ge p-FinFET, it was
found that SiGe SRB and GeSn S/D could achieve com-
pressive longitudinal stress for mobility enhancement.
In addition, for Ge n-FinFET, mobility of electrons rela-
tive to Si is expected to be 1.1 times on the top surface
of the fin and 6 times along the fin sidewalls [23].
Hence, this results in the high mobility even for relaxed
Ge n-FinFET which can be further enhanced by stress-
ers, e.g. GeSn SRB and SiGe S/D.
It was also reported that strained Si1¡xGex tri-gate
PFET has excellent electrostatic control and hence can
be a promising candidate for future generations of
high performance logic applications [24]. Due to small
band gap of Ge and poor gate interface, the cut-off
characteristics are still not good. Inserting a GeOx layer
between high-k dielectric and strained Ge layers has
significantly improved both mobility and cut-off char-
acteristics of the Ge p-MOSFETs [25]. GeSn PFETs
have emerged out as a probable replacement for Ge
PFETs. GeSn PFETs offer higher hole mobility as com-
pared to Ge PFETs. This high mobility is attributed to
uniaxial compressive strain in GeSn channel, which
leads to a significant reduction of hole effective mass
[26]. For bulk FinFET, region underneath the fin should
be carefully engineered for scalability down to 7 nm
and beyond. Placing quantum barrier doped ground
plane under the fin can help improve electrostatics in
bulk FinFETs at 7-nm node and beyond [27]. Apart
from strain engineering, intrinsic channels formed by
III V material can achieve high mobility. InGaAs-based
channels are quite popular due to their high channel
mobility. But as body thickness decreases due to scal-
ing, mobility reduction may take place. To boost the
channel mobility, two boosters are introduced. First,
higher In content InAs channels and second, MOS inter-
face buffers where higher In content layer is sand-
wiched between lower In content layer, i.e. In0.3 Ga0.7
As (3 nm)/InAs (3 nm)/In0.3 Ga0.7 As (3 nm) [28].
7. VARIABILITY
With continuous scaling of CMOS devices, variability
due to process variations has substantially increased.
Primary source of variations are the fabrication pro-
cesses for fin and NWs, which mainly include fin pat-
terning and NW size reduction. Some of the dominant
sources of mismatch in these nano-devices are RDF,
LER, and metal gate EWF variability. All of these effects
lead to variations in the Vt and Ion. EWF variation
(EWFV) is the primary source of Vt variations in
undoped channel FinFET. EWFV arises due to poly-
crystalline metal grains having orientation-dependent
work function. Amorphous metal gates have been
reported which successfully suppress Vt variation by
IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015
removing EWFV. TaSiN has been reported as a suitable
amorphous metal gate due to its thermal stability and
suitability for gate-first process. Elimination of EWFV is
also effective in suppressing variations in gm [29].
Random discrete dopant (RDD) distribution seems to
be a major concern for nano-scaled MOSFETs as it
gave rise to fluctuations in device characteristics. Effect
of RDD in implanted and annealed As atoms on n-type
GAA silicon NW transistors have been reported. It was
found that As dopants which diffused into the central
region of the channel, strongly affect the Vt fluctuation
of Si NW transistor. Sidewall gate spacer technique is
used to suppress these fluctuations and it is found that
number of As dopants in the channel region is greatly
reduced with these spacers as compared to devices
without such spacers. As a result, it significantly sup-
pressed Vt variations and also reduced off-current
fluctuations [30]. Also, dependence of width of NW
(Wnw) and phonon scattering effect on Ion fluctuation
(sI/Ion) has been investigated. It is found that sI/Iave
for Wnw D 5nm is larger than that of Wnw D 3 nm
which can be attributed to the better gate control. For
phonon scattering two different effects are reported, i.
e. current enhancement in low-current state and reduc-
tion in high-current state which finally resulted in sup-
pression of Ion fluctuation [31].
In 14 nm SOI FinFETs, impact of low drain bias Vt
(Vtlin), gm, and Rext variation on the overall effective
current (Ieff) variability has been studied. As shown in
Figure 5, it is found that gm variability is the vital con-
tributor to Ieff variation. In nFETs, about 30% 40%
variation is from Vtlin which is independent of Nfin.
This variation can be reduced by improving fin surface
with methods such as H2 bake [32]. Variability in tran-
sistor performance as a function of number of parallel
NWs is also studied. The performance deteriorates for
multiple NWs devices because self-heating becomes
more at higher density of NWs, leading to increased off
current and SS. In multiple NWs, the transfer character-
istics are the summation of the individual NW which
resulted in the spread of Vt. This spread in transistor Vt
increases with the number of NWs, which is reflected in
the degradation of the overall SS of the transistor [33].
Apart from conventional variability sources, such as
RDF, EWFV, and LER, flicker (1/f) noise variability
has become a subject of attention and concern for low
power analog designs using smaller device geometry.
The effect of halo, bias, and oxide thickness on noise
variability has been reported. It is found that magni-
tude of noise variation is higher for strong halo as com-
pared to a weak halo. Higher noise variation in strong
halo is due to the effect of additional trap density
315
 Bansal A K and Dixit A: Advances in Logic Device Scaling
Figure 5: Relative contribution of the three parameters to
the overall Ieff variability.
which is also present at the S/D edges of the channel in
addition to channel area. At high gate bias, channel
non-uniformity reduces which minimizes inversion
carrier density variation along the channel and results
in lower noise variation. Also at low gate bias, thick
gate oxides are seen to show higher noise variations
than thin gate oxide devices [34].
8. CONCLUSION
Industry trends in advanced logic devices have been dis-
cussed. It was reported that introduction of EUVL and a
transition to 450-mm wafer size are the major leaps that
industry may be taking to keep up with economics of
scales. Among many contenders of mainstream device
for sub-10-nm CMOS nodes, Si and III V NWs-based
devices seem the most natural extension of Si FinFET
based 10-nm CMOS technology. However, ability of
TFETs to beat the 60-mV/decade minimum sub-thresh-
old swing barrier is promising and depending upon
manufacturing feasibility, TFETs could be a promising
device design for futuristic CMOS nodes. As discussed,
various innovations in gate, channel, and S/D engineer-
ing are required to ensure performance and short chan-
nel control. Variability appears to be the decisive factor
in selection of device architecture and process technolo-
gies, may ultimately limit further scaling of CMOS
beyond certain nodes.
Funding
This work is partially supported by Department of Science
and Technology, Government of India SERB [grant no. SB/
S3/EECE/037/2014].
316
ORCID
Anil Kumar Bansal http://orcid.org/0000-0002-6984-2877
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 Bansal A K and Dixit A: Advances in Logic Device Scaling

Authors
Anil Kumar Bansal received his MTech Abhisek Dixit is an assistant professor in the
degree from the National Institute of Technol- Department of Electrical Engineering at IIT
ogy Hamirpur, India in 2013. He has been a Delhi, India. He works on design, modelling,
PhD student at Indian Institute of Technology processing and characterization of CMOS and
(IIT) Delhi, India since January 2014. His solar cell devices. Prior to joining IIT Delhi, he
research interests include sub-10nm logic worked at IBM Semiconductor Research and
CMOS device design and characterization. Development Center (SRDC) for more than
6 years as a senior technical leader in enable-
E-mail: eez138521@ee.iitd.ac.in
ment and TCAD groups. Before IBM, he
worked at International Microelectronics Center (IMEC) Leuven in
CMOS device integration group for 5 years and got a PhD degree
from Katholieke University of Leuven, Belgium in 2007. He got an
MTech. from IIT Bombay in 2002. He has 6 US patents and more than
40 publications in apex international conferences and journals. He is
a senior member of IEEE.
E-mail: adixit@ee.iitd.ac.in

DOI: 10.1080/02564602.2015.1023372; Copyright © 2015 by the IETE

318 IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015