Code No: E415-EC415 OR

IV B.Tech.(CCC) Supplimentary Examinations, June 2009

IC ANALYSIS DESIGN AND APPLICATIONS
( Common to Electrical & Electronic Engineering and Electronics &
Communication Engineering)
Time: 3 hours Max Marks: 100
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) What are the fabrication steps of IC technology explain with some example?
(b) Draw and explain the cross-sectional view of the integrated circuit of the given
circuit as shown in figure 1b. [10+10]

Figure 1b
2. (a) Why is emitter resistor RE replaced by a constant current bias circuit in
differential amplifier stage of an OP-AMP?
(b) Explain why open loop configurations are not used in linear applications.
(c) For an OP-AMP, PSRR=70dB(min), CMRR=105 , differential mode gainAd =105 .
The output voltage changes by 20V in 4 microseconds. Calculate
i. numerical value of PSRR
ii. Common mode gain
iii. Slew rate of the OP-AMP. [8+4+8]

3. (a) What is a sample-and-hold circuit? Draw the circuit diagram and explain its
action?
(b) With reference to the sample-and-hold circuit define the following terms:[12+8]
i. Aperture time,
ii. Hold time, and
iii. Acquisition time

4. (a) Explain in detail the following terms with reference to PLL

i. Lock range
ii. Capture range
iii. Capture transient
iv. Pull-in-time.

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Code No: E415-EC415 OR
(b) i. Draw the internal functional diagram of NE 566 VCO and derive expres-
sion for free running frequency.
ii. From the given component values find the free running frequency Control
voltage VC = 10.9V , VCC = 12V , R1 =4.7k and C1 =1.1nF . [10+10]

5. (a) Define
i. Positive logic
ii. Negative logic
iii. Pulse logic.
(b) What is meant by AOI logic. Explain with help of an example.
(c) In the given circuit (figure 5c) silicon transistor is used. Find the out-put
levels for the given input levels of 0.2V and 12V, obtained from a preceding
stage. Assume hF E =30. [8+6+6]

Figure 5c
6. (a) Explain the following terms in connection with a flip-flop.
i. preset
ii. clear
iii. race conditions
iv. race-around condition.
(b) Draw the schematic circuit of Toggle-flip-flop (T) Give its truth-table. Justify
the entries in the truth-table. (NAND gates only) [10+10]

7. (a) Design 64 line output demultiplexer using lower order demultiplexer. Such as
4 to 16 and 2 to 4 Demultiplexers.
(b) Give the NAND gate realization of full-adder. [12+8]

8. (a) Explain how frequency can be measured in electronic circuits.

(b) What are precaution must be taken while measuring frequency of the signal.
[12+8]

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