Design Compiler Expert Quick Guide X-2005.

09
Introduction
This Quick Guide is designed to help you get started with Design Compiler Expert by showing you the most commonly used flows, commands, and variables. The command
options shown are only a sample of the many options that are available. For detailed information, see the man pages, user guides, and reference material, available through
Documentation on the Web at http://solvnet.synopsys.com/DocsOnWeb and Synopsys Online Documentation (SOLD), which can be downloaded by electronic software
transfer (EST) and is included with the software for CD users. Rev. 1.1

Flow .synopsys_dc.setup
set target_library core_slow.db
set symbol_library core_slow.sdb
set synthetic_library dw_foundation.sldb
set link_library “* $target_library $synthetic_library”
lappend search_path ./src ./libs
set designer "Your Name"
set company "Your Company"

set sh_enable_line_editing true

set gui_autostart 0
set default_report_significant_digits 4

define_design_lib WORK -path ./WORK # Puts temporary files in WORK dir

alias h history
alias page_on {set sh_enable_page_mode true}
alias page_off {set sh_enable_page_mode false}

history keep 200

Run Script
# Read in design
analyze –format verilog block.v
analyze –format verilog bigchip_top.v
elaborate bigchip_top

# Set current design & Link

current_design bigchip_top # Top of block or chip
link

# Source Constraints
source –echo -verbose constraints.tcl

# Checks Before Compiling

check_timing # Warns about possible timing issues
report_port –verbose # I/O delays, driving cell, load
check_design # Check the design for consistency
File Formats report_timing_requirements -ignored # Check for ignored exceptions
.ddc: Synopsys logical database format in XG mode -- Contains netlist plus
attributes and constraints
# Path Groups
SDC: Synopsys Design Constraints group_path –name in_paths –weight 0.5 \
Tcl: Tool command language –critical_range [expr 0.1*$least_clk_period] \
.db: Synopsys database format –from [all_inputs] –to [all_registers]
group_path –name out_paths –weight 0.5 \
–critical_range [expr 0.1*$least_clk_period] \
–from [all_registers] –to [all_outputs]
To run Design Compiler group_path –name reg_paths –weight 10.0 \
–critical_range [expr 0.1*$least_clk_period] \
Unix> dc_shell-xg-t –f run.tcl |& tee –i run.log # to run shell –from [all_ registers] –to [all_registers]
Unix> design_vision –xg – f run.tcl |& tee –i run.log # to run GUI group_path –name inout_paths –weight 0.5 \
–critical_range [expr 0.1*$least_clk_period] \
–from [all_inputs] –to [all_outputs]

# Compile
compile –scan
compile –inc –scan –map_effort high

# Analyze Results
check_design # Check the current design for consistency, and so on.

# Reports & Write

my_reports bigchip_top
my_write bigchip_top
More Commands for Scripts and Interactive Use Constraints and Environment
# Getting Help # Set Design Constraints (constraints.tcl)
help –verbose create*
man create_clock reset_design # Clear out all constraints
create_clock -help
printvar *_library # Design Optimization Constraints
create_clock –period 4 [get_ports clk]
# Object Retrieval – All of these commands create collections of set_clock_latency 3 –source [get_clocks clk] # External delay to port
objects set_clock_latency 2 [get_clocks clk] # Internal from port
get_cells set_clock_uncertainty –setup 0.5 [get_clocks clk] # Skew + Jitter
get_clocks set_clock_transition
get_designs
get_libs my_lib set_input_delay –min 0.5 –max 1.5 –clock clk [get_ports ain bin]
get_lib_cells -quiet $lib_name/* set_output_delay –min 0.5 –max 1.5 –clock clk [get_ports cin]
get_lib_pins -quiet $lib_name/$cell/* # Pins of cell in library
get_nets -of_objects [get_pins ff1/*] # Find all nets connected to cell set_max_area 0
get_ports
# Design Rule Constraints (Optional)
all_inputs set_max_transition
all_outputs set_max_fanout
all_clocks set_max_capacitance

# Looping Constructs # Define Design Environment

for {set i 0} {$i < 5} {incr i} {…$i… } set_operating_conditions WCCOM
foreach i $list {… $i… } set_wire_load_model “10x10”
foreach_in_collection in_prt [all_inputs] {… $in_prt… } set_wire_load_mode top
set_driving_cell –lib_cell FD1 –pin Q [all_inputs]
# Grouping set_load load_of(tech_lib/IV/Z) {input_1,input_2}
ungroup set_min_library
group

# Listing
list_libs

# Reporting
report_port
report_lib libname # Lists vendor supplied operating conditions
report_resources
report_cell [get_cells -hier *] # Report area of all cells in design
report_cell [get_cells -hier -filter "is_hierarchical==false"] # Leaf cells area Tips for Improving Results
report_hierarchy

# Procedures Useful SolvNet Articles:

proc my_reports { design } {
redirect –tee reports/$design.rpt { Synthesis ABC’s Part 1
report_constraints –all_violators https://solvnet.synopsys.com/retrieve/008662.html
report_timing – nets –input_pins
Synthesis ABC’s Part 2
report_area
https://solvnet.synopsys.com/retrieve/008663.html
report_qor
}
Coding Guidelines for Datapath Synthesis:
}
https://solvnet.synopsys.com/retrieve/015771.html
proc my_write { design } {
Improving Your Design Compiler Constraints:
change_names –rules verilog -heir
write_sdc -nosplit $design.sdc https://solvnet.synopsys.com/retrieve/006746.html
write –format ddc –hier –output $design.ddc
write –format verilog –hier –output $design_gates.v Improving Automated Chip Synthesis Results:
write_script –out $design.w-con https://solvnet.synopsys.com/retrieve/010246.html
}
Ungrouping the Hierarchy to Improve Timing:
https://solvnet.synopsys.com/retrieve/903085.html

Hierarchical Design Techniques White Paper:

Synopsys Implementation Tool Guide https://solvnet.synopsys.com/retrieve/015503.html

Design Compiler – Logic synthesis Optimization Techniques in Different Compile Options:

Physical Compiler – Physical synthesis https://solvnet.synopsys.com/retrieve/901881.html
JupiterXT – Floorplanning XG Mode Introduction:
Astro – Place and route for designs down to 65nm design rules https://solvnet.synopsys.com/retrieve/015440.html
IC Compiler – Next generation place and route
Power Compiler – Power optimizations for synthesis Benefits of Design Compiler XG Mode:
PrimePower – Power analysis https://solvnet.synopsys.com/retrieve/014798.html
PrimeRail – IR drop and electromigration analysis
DFT Compiler – Scan synthesis
TetraMAX – Scan compression Documentation
PrimeTime – Signoff timing analysis
PrimeTime-SI – Signoff timing analysis with signal integrity effects https://solvnet.synopsys.com/dow_search
Astro-Rail – Signoff reliability analysis
Hercules – Physical verification
Star-RCXT – Parasitic extraction
How to Get Support:
HSPICE – Circuit simulation
Web: Click “Enter-A-Call” at http://solvnet.synopsys.com/EnterACall
NanoSim – Mixed signal circuit simulation Email: support@synopsys.com