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Government Engineering
College, Dahod
Zalod Road, Dahod, Gujarat - 389151
Sequential Lighting Of A River Bridge
Kamlesh N. Dumaniya [06EE011]
Government Engineering
College, Dahod
Zalod Road, Dahod, Gujarat - 389151
Electrical Engineering
Department
Government Engineering
College, Dahod
Zalod Road, Dahod, Gujarat - 389151
Sequential Lighting Of A River Bridge
Sandip L. Vegad [07EE060]
Electrical Engineering
Department
Government Engineering
College, Dahod
Zalod Road, Dahod, Gujarat - 389151
Sequential Lighting Of A River Bridge
Government Engineering
College, Dahod
Zalod Road, Dahod, Gujarat - 389151
Project Report
on
Sequential Lighting Of A River Bridge
Kamlesh N. Dumaniya [06EE011]
Birju R. Darji [06EE009]
Sandip L. Vegad [07EE060]
Jayesh R. Sharma [07EE054]
Of
VIIth Semester B. E. (Electrical)
Electrical Engineering Department
Government Engineering College, Dahod
Guided by
On
At
Of
VIIth Semester B. E. (Electrical)
Electrical Engineering Department
Government Engineering College, Dahod
Guided by
On
At
Of
VIIth Semester B. E. (Electrical)
Electrical Engineering Department
Government Engineering College, Dahod
Guided by
On
At
Of
VIIth Semester B. E. (Electrical)
Electrical Engineering Department
Government Engineering College, Dahod
Guided by
On
At
Of
VIIth Semester B. E. (Electrical)
Electrical Engineering Department
Government Engineering College, Dahod
Guided by
On
At
It is my privilege to express my
indebtedness and deep sense of gratitude to my guiding
“Prof. N. D. RABARA”. His keen interest, constant
encouragement variable suggestion and dexterous guidance
resulted in the successful completion of my project work. I
greatly thankful to “Prof. N. D. RABARA” for there great
support in my project work and for keen interest in built up
our valuable future.
GOVERNMENT ENGINEERING
COLLEGE,
DAHOD
6.1 IC1-AT89C2051
6.2 LED
6.3 IC3-7805 REGULATOR & POWER SUPPLY
6.4 SWITCH
6.5 RELAY
6.6 T1-2N2222 TRANSISTOR
6.7 TRANSFORMER
6.8 CIRCUIT DIAGRAM OF POWER SUPPLY
6.9 PCB SPECIFICATION
6.10 MISCELLANEOUS
7. LIST OF PARTS
8. WORKING
9. PRICE LIST
10. APPLICATION
11. CONCLUSION
12. REFERENCES
12.1 BOOKS
12.2 WEB SITES
{1}
INTRODUCTION
BLOCK DIAGRAM
{3}
CIRCUIT DIAGRAM
{4}
WHAT IS CONVERSION?
GENERAL DESCRIPTION
6.1: AT89S52
Pin 31, EA
(External Access Enable)
must be tied high to
enable the device to fetch
code from internal
memory like flash or
ROM. Tying EA to GND
will enable external code execution, used when code is
stored in an external EEPROM or other non-volatile memory.
8052 SCHEMATIC
6.2: LIGHT
EMITTING
DIODE:-
Vout=VR+VL
Where VL=IL*RL
The minimum input voltage required is given by the
equation
NOTE:-
BRIDGE RECTIFIER:-
FILTER:-
6.4: SWITCH:-
Selecting switch:-
Switch contacts:-
For Example:-
6.5: RELAY:-
CHOOSING A RELAY:-
Coil voltage:-
Coil resistance:-
For example:-
Advantages of Relays:-
Disadvantages of Relays:-
6.8: TRANSFORMER:-
ADVANTAGES OF P.C.B.:-
FABRICATION ON PCB:-
SEMICONDUCTORS:
RESISTORS:-
1. R1,R2 10k-ohm/4w
2. R3-R6 820-ohm/4w
3. R7-R8 10k-ohm 9 pin pair
Notes:- for all resistors have 4- watt, +or-5v carbon
CAPACITORS:-
1. C1,C2 33pf
2. C3,C4 10m/63vF
3. C5 1000mf/35v
MISCELLANEOUS:-
Features
Description
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and
must be cleared by software. TF2 will not be set
when either RCLK = 1 or TCLK =1.
EXF2 Timer 2 external flag set when either a capture or
reload is caused by a negative transition on T2EX
and EXEN2 = 1. When
Timer 2 interrupt is enabled, EXF2 = 1will cause
the CPU to vector to the Timer 2 interrupt routine.
EXF2 must be cleared software. EXF2 does not
cause an interrupt in up/down counter mode
(DCEN = 1)
RCLK Receive clock enable. When set, causes the serial
port to use Timer 2 overflow pulses for its receive
clock in serial port Modes 1 and 3. RCLK = 0
causes Timer 1 overflow to be used for the receive
clock.
TCLK Transmit clock enable. When set, causes the serial
port to use Timer 2 overflow pulses for its transmit
clock in serial port Modes 1 and 3. TCLK = 0
causes Timer 1 overflow to be used for the transmit
clock.
EXEN2 Timer 2 external enable. When set, allows a
capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the
timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for
timer function. C/T2 = 1 for external event counter
(falling edge triggerd).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes
captures to occur on negative transitions at T2EX if
EXEN2 = 1. CP/RL2 = 0 causes automatic reloads
to occur when Timer 2 overflows on negative
transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and
the timer is forced to auto – reload on Timer 2
overflow.
{9}
PRICE LIST
{10}
APPLICATION:
ENERGY SAVER :
AUTOMATIC LIFT:
SECURITY SYSTEM:
{12}
REFERENCES:
12.1 Books:-
12.2 Websites:-
http://www.google.com
http://www.keil.com
http://www.rockhounding.net
http://www.atmel.co.in
http://www.geocities.com
http://www.8052microcontroller.com
http://www.futurlec.com