Debouncing a Switch

A Design Example

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Background and Motivation

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 When you throw a switch
(button or two-pole switch)…
• It often bounces…

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 Another switch…

switch

after
inversion

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Yet Another…

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Still Yet Another…

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 Causes

• Switches and buttons are mechanical

– Spring loaded
• Contacts literally bounce
– Not an instant, once-only, on↔off change

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 Source of Errors
• Consider a 100 MHz system clock, which has a 10 ns period
• Each ms would be 100,000 system clock cycles
• Downstream circuitry will see every bounce as an input change!

1 ms = 100,000 clock
cycles at 100 MHz

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FSM-Based Solution

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 Solutions

• Single-output switch
– Since all you see is bouncing value, timing-
based solution can be employed

• There are other solutions but they require a

different kind of switch

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 Timing-Based Solution

• Only declare an input change after signal has been

stable for at least 5ms

5ms

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 FSM Solution

• Simple enough that an FSM might not be

required
– Easy to concoct a sequential circuit to do this
with a counter and a single FF

• Let’s do it with an FSM

– If solution requires only a counter and a single
FF, we will find that solution

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 Draw a Simplified Timing Diagram

5ms 5ms

noisy

debounced

time

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 Draw a System Block Diagram

noisy debounced
Finite Timer
State clrTimer
timerDone (5ms)
Machine

clk reset clk

Very reminiscent of our car wash controller…

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The Design of the FSM

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 Draw a State Graph
noisy’

clrTimer
S0
noisy’•timerDone noisy

noisy’

noisy’•timerDone’ S3 debounced S1 noisy•timerDone’

noisy
noisy•timerDone
noisy’
S2 debounced
clrTimer

noisy

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 Draw a State Graph
noisy’
Debounced output
is low…

clrTimer
S0
noisy’•timerDone noisy

noisy’

noisy’•timerDone’ S3 debounced S1 noisy•timerDone’

noisy
noisy•timerDone
noisy’
S2 debounced
clrTimer

noisy

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 Draw a State Graph
noisy’
Debounced output
is high…

clrTimer
S0
noisy’•timerDone noisy

noisy’

noisy’•timerDone’ S3 debounced S1 noisy•timerDone’

noisy
noisy•timerDone
noisy’
S2 debounced
clrTimer

noisy

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 An Improved State Graph
noisy’/clrTimer
Do you see why there is no
need for a reset input?
S0
Looks like the FSM
can be implemented
with just a single FF
noisy•timerDone’

noisy•timerDone
noisy’•timerDone

debounced
noisy’•timerDone’ S1
As mentioned, Mealy
noisy/clrTimer machines often require
fewer states…
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 Reduce FSM to Logic

S0 = CS’ S1 = CS noisy = N timerDone = T

NT
CS 00 01 11 10
0 1
1 1 1 1

NS = noisy•timerDone + CS•timerDone’

clrTimer = noisy’•CS’ + noisy•CS

debounced = CS

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 Reduce FSM to Logic

NS = noisy•timerDone + CS•timerDone’

clrTimer = noisy’•CS’ + noisy•CS

debounced = CS

noisy
timerDone D Q debounced

CS clrTimer

noisy

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 Input “noisy” is Asynchronous

If pulse shorter than period, FSM may not see it

• Very small pulses may be missed by FSM

– This is not a real problem so we will live with it
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 More on Asynchronous “noisy” Input

noisy debounced
Finite Timer
State clrTimer
timerDone (5ms)
Machine

clk reset clk

• This is the classic asynchronous input problem:

– FSM may see input change and change state
– Timer may not see input change and not clear timer
• Or vice versa
• Will this cause incorrect operation?

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 Asynchronous Input Problem
noisy’/clrTimer

noisy•timerDone’
S0 Look at the transitions. Will
previous slide’s problem
noisy•timerDone cause a malfunction?

noisy’•timerDone
If you determine that a
problem may result, that is
easiest way to solve the
problem?

debounced
noisy’•timerDone’ S1

noisy/clrTimer

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 More on Asynchronous “noisy” Input

• What about metastability?

– Most buttons aren’t pushed very often
– Chance of metastability is very low

• We could eliminate all our asynchronous

problems by adding flip flops in series
– Avoid detailed analysis
– Play it safe and avoid possibility of mistakes

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Design of the Timer

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 Timer Calculations

• Assume system runs at 50 MHz (20 ns period)

• 5ms/20ns = 250,000 system clock cycles
• We could design a MOD-250,000 counter
• A simple 18-bit counter will work
– 218 is a bit longer than 250,000 (262,144)
– It is close enough to 5 ms for our purposes

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 Design the Timer

• 19 input state machine

– 18 CS bits + 1 clrTimer bit
– Very, very large truth table

• A better approach:
– Register that selects between CS+1 and 0
– This is the technique of Chapter 12 (registers)

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 Timer Structure

18

18
+1 0 18 18 18-input
timerDone
18 D Q AND
0 1

clrTimer clk

What can we do to simplify this circuit?

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 Timer Structure

18

18
+1 0 18 18 18-input
timerDone
18 D Q AND
0 1

clrTimer clk

What can we do to simplify this circuit?

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 Improved Timer Structure

18

18
+1 18 18 18-input
timerDone
18 D Q AND
clrTimer

clk

This is a simpler way to A synthesis tool likely would have

conditionally generate zeroes. generated this from Verilog or
VHDL code containing a MUX

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 Timer Structure

18

18
+1 0 18 18 18-input
timerDone
18 D Q AND
0 1

clrTimer clk

What can we do to simplify this circuit?

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 Improved Timer Structure
18

18
+1 18
18 D Q
clrTimer
Cout

clk
timerDone

Use the carry out of the adder to detect rollover.

Output timerDone is delayed by one cycle, but this is

not a problem in our system.

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Building the +1 Circuit – Version #1

count[17:0]

“000000000000000001” output

The adder could be built as outlined back in

Chapter 8 using full adder blocks.

However, half the full adder inputs will be ‘0’.

There ought to be a better way!

Hint: Any time a circuit has constant inputs

(0 or 1) then the circuit can be simplified!

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 A Full-Adder with ‘0’ Inputs

Full Adder Half Adder

A A
‘0’ S S
Cin Cin

A ‘0’
‘0’
‘0’ ‘0’ A Cout
Cout
Cin Cin
A
Cin “Half Adder” adds two
bits instead of three

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Building the +1 Circuit - Version #2

A2 A1 A0

C2 Half C1 Half C0 Half ‘1’

Adder Adder Adder

S2 S1 S0 Carry-in of ‘1’
gives us the +1

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Building an 18-Bit AND

This is one way… CAD tools are good at building

structures like this from lower-
level building blocks.

Just describe the AND in Verilog

or VHDL and CAD tools will make a
good choice.

If target technology has special

structures for wide logic, CAD
tools likely will use it

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 Debouncer Summary

• Structure is timer + FSM

• 2-state FSM makes NS logic trivial
• Asynchronous input “noisy” means we must be sure
our system works with any input timing
– If desired/needed, synchronize “noisy” input using one
or more flip flops
• Counter too large for conventional techniques
– Use MUX + register technique of Chapter 12
• Systems can usually be greatly simplified beyond the
obvious design by using careful analysis

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