1/2 HC139 7

31000 - E LECTRONICS . T UTORIAL

6
31000
Y3
3 6
B Y2
2
A Y1
ELEKTRONIK
5
Structural VHDL
4
Y0
G1

Purpose Acquire practical skills in developing structural VHDL models.

Assignment Develop structural VHDL models of the digital circuits specified in the exercise.
Contents
• Structural model of a 2-bit adder.
• Structural model of a comparator with registers at the input.

Before you start the exercise answer the following questions:

• What is the difference between a full adder and a half adder.
• How do we compare two numbers when having only an adder/subtractor ?

Structural model of a 2-bit adder

The model of a 2 bit adder will consist of two full adders (see Fig. 1). The input operands of the adder are the 2-bit
numbers A and B, and an input carry CIN. The result is a 2-bit sum SUM and an output carry bit COUT.
This example illustrates the use of a structural VHDL description for creating a hierarchical description. Components
which are treated as ”black boxes” are used at the top level of the hierarchy. The behaviour of these components is
described at the lower level of the hierarchy.
A schematic of a full adder is given in Fig. 2. The VHDL model of this adder is given in Fig. 3.
The structural model of the 2-bit adder is given in Fig. 4.
Write down the truth table for the 2-bit adder. Simulate the correct behaviour of the model.

Structural model of a comparator with registers at the inputs

• Develop a structural VHDL model of an 8-bit comparator with registers at the data inputs as shown in Fig. 5.
• In order to make the structural model, use the VHDL models for a register and a comparator from the previous
exercises.
• Simulate the developed model and check its correctness.

1
31000 - Electronics. Tutorial Structural VHDL

Figure 1: Hierarchical schematic of a 2-bit adder.

Figure 2: Schematic of a full adder.

Ørsted•DTU/31000 Svetoslav Nikolov 2

31000 - Electronics. Tutorial Structural VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity adder1 is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end adder1;

architecture rtl of adder1 is

begin
sum <= (a xor b) xor cin;
cout <= (a and b) or (cin and a) or (cin and b);
end rtl;

Figure 3: Dataflow model of a full adder.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ADDER2 is port(

A, B: in std_logic_vector(1 downto 0);
CIN: in std_logic;
SUM: out std_logic_vector(1 downto 0);
COUT: out std_logic);
end ADDER2;

architecture STRUCTURAL of ADDER2 is

component ADDER1
port (A, B, CIN: in std_logic; SUM, COUT: out std_logic);
end component;

signal T: std_logic;

begin

U1: ADDER1 port map (A=>A(0), B=>B(0), CIN=>CIN, SUM=>SUM(0), COUT=>T);

U2: ADDER1 port map (A=>A(1), B=>B(1), CIN=>T, SUM=>SUM(1), COUT=>COUT);

end STRUCTURAL;

Figure 4: Structural VHDL model for a 2 bit full adder.

Ørsted•DTU/31000 Svetoslav Nikolov 3

31000 - Electronics. Tutorial Structural VHDL

Figure 5: Hierarchical scheme of a 2-bit comparator.

Ørsted•DTU/31000 Svetoslav Nikolov 4