Digital Electronics Theory For GATE EXAM

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Chapter-1 Number Systems

The study of number systems is important from the viewpoint of understanding how data
are represented before they can be processed by any digital system including a digital
computer. It is one of the most basic topics in digital electronics.
Data Representation
• There are basically three types of data:
– Integer
– Floating-Point
– Character
• The Integer type is simple.
• The Floating-Point type is bit complicated (IEEE 754representation)
• The characters are generally encoded (e.g. ASCII encoded)
Types of number systems:

1. Decimal Number System, radix-10 number system 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
2. Binary Number System, radix-2 number system (1, 0)
3. Octal number system,radix-8,(0,1,2,3,4,5,6,7)
4. Hexa decimal number system.radix-16(0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F)
Binary number system: it is a base-2 system with two digits: 0 and 1.
• Most popular representation in digital systems.
• The digits are called bits and the radix point is called the binary point.
• kilo or K –210, mega or M – 220, and Giga or G – 230
• There are three ways of representing binary numbers:
 Sign-and-Magnitude
 1’s Complement
 2’s Complement
Octal number system:
• Used for compact representation of binary numbers.
• More convenient to people than using a bit strings in binary.
• The octal number system has radix or base of 8 and uses digits 0, 1, 2, 3, 4, 5, 6, 7.
• Example: (127.4)8 = 1 x 82 + 2 x 81 + 7 x 80 + 4 x 8-1 = (87.5)10.
• Note: The digits 8 and 9 are forbidden.
Hexadecimal number system
• More compact representation of binary numbers.
• More convenient to people than using a bit strings in binary.
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• The hexadecimal number system has radix or base of 16 and uses digits 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, 10, 11, 12, 13, 14, 15.
• The letters A, B, C, D, E, and F are used for 10, 11, 12, 13, 14, and 15, respectively.
• Example: (B65F) 16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160
= (46687)10.
Conversion among Different Number Systems:

Binary number system is used in computers, but people are more comfortable with
decimal system. So, there has to be back and forth conversion between decimal and
binary system. The computation is done in binary and human understanding is in
decimal. This needs a method to store decimals (and characters) in a computer that can be
converted to binary.
 Sign Extension of a Binary Number
 Binary to Octal and vice versa
 Binary to Hexadecimal and vice versa
 Decimal Integer to Binary
 Decimal Integer to Octal
 Decimal fraction to Binary
 Decimal fraction to Octal
•The conversion of a number in base r to a decimal is done by expanding the number in a
power series of r and adding all the terms.
•The reverse process, i.e. conversion of decimal integer to any base r is bit complicated.
•In the number contains a decimal point, then the number has to be divided into integer
part and fraction part, and the conversion of the two parts should be done separately.
•The conversion of decimal integer to base r is done by dividing the number and the
successive coefficients by r, and accumulating the remainders.
•The conversion of the decimal fraction to base r is done by multiplying the number and
the fraction part of the successive products, and accumulating the integer part of the
successive products.
Sign Extension of a Binary Number: Sign extension is conversion of a binary
number in n bits to a number with more than n bits.
Take the MSB from the smaller quantity and replicate it to the new bits of the larger
quantity, and then copy the old bits of the smaller quantity into the right portion of the
new word.
Hexa to decimal:
•Partition the binary number into groups of four each starting from the binary point and
proceed to the left and to the right.
•Assign hexadecimal digit to each group.
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•The above process can be reversed to convert from the hexadecimal numbers to binary
numbers.
•Binary Octal: Partition the binary number into groups of three each starting from the
binary point and proceeds to the left and to the right.
Floating Point Numbers

• We need a way to represent
• numbers with fractions, e.g., 3.1416
• very small numbers, e.g., .000000001
• very large numbers, e.g., 3.15576 ´ 109
• Representation:
• sign, exponent, significand: (–1)sign x significand x 2exponent
• more bits for significand gives more accuracy
• more bits for exponent increases range
• IEEE 754 floating point standard:
• single precision: 8 bit exponent, 23 bit significand
• double precision: 11 bit exponent, 52 bit significand
• Leading “1” bit of significand is implicit.
• Exponent is “biased” to make sorting easier
• all 0s is smallest exponent all 1s is largest
• bias of 127 for single precision and 1023 for double precision
• summary: (–1)sign x (1+significand) x 2exponent – bias
• Example:
• decimal: -.75 = -3/4 = -3/22
• binary: -.11 = -1.1 x 2-1
• floating point: exponent = 126 = 01111110
• IEEE single precision:10111111010000000000000000000000
Signed number representation:

1. Sign and magnitude method, range:
2.1’s complement method, range:
3.2’s complement method, range

• Both positive and negative numbers can be represented using any of the above three
ways.
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• In all three methods positive number has identical representations.
• The negative values have different representations.
• In all three ways, if the left most bit is “0”, then the number is positive, whereas if the
left most bit is “1”, then number is negative.
1. Sign and magnitude method: It is simply an ordinary binary number with one extra digit
placed in front to represent the sign. If this extra digit is a “1”, it means that the rest of the
digits represent a negative number. If the extra digit is a “0”, it means that the number is a
positive one.
2)1’s complement method: The negative values are obtained by complementing each bit of
the corresponding positive number.
CODES:
Coding and encoding is the process of assigning a group of binary digits, commonly
referred to as ‘bits’. By assigning each item of information a unique combination of bits
(1’s and 0’s), a code is a symbolic representation of an information transform. The bit
combination is referred to as ‘CODEWORDS’.
There are many different coding schemes, each having some particular advantages and
characteristics. One of the main efforts in coding is to standardize a set of universal codes
that can be used by all.
In a broad sense we can classify the codes into five groups:
(i) Weighted Binary codes
(ii) Non-weighted codes
(iii) Error–detecting codes
(iv) Error–correcting codes
(v) Alphanumeric codes.
Weighted Binary Codes
In weighted binary codes, each position of a number represents a specific weight. The
bits are multiplied by the weights indicated; and the sum of these weighted bits gives the
equivalent decimal digit.
The best approach is to evaluate how many code words can be derived from a
combination of n bits.
Example: Let n = no. of bits in the codeword and x = no. of unique words
If n = 1, then x = 2 (0, 1)
n = 2, then x = 4 (00, 01, 10, 11)
n = 3, then x = 8 (000, 001, …111)
and in general, n = j, then x = 2 j
if we have available j no. of bits in the code word, we can uniquely encode max 2 j
distinct elements of information.
x<2j
or j > log2X
or j > 3.32 log10 X Where j = number of bits in code word.
Binary Codes Decimal Codes (BCD codes)
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In BCD codes, individual decimal digits are coded in binary notation .Thus binary codes
representing 0 to 9 decimal digits are allowed. Therefore all BCD codes have at least four
bits (Q min. no. of bits required to encode to decimal digits = 4)
But with 4 bits, total 16 combinations are possible (0000, 0001, ..., 11 11) but only 10 are
used (0 to 9). The remaining 6 combinations are invalid and commonly referred to as
‘UNUSED CODES’.There are many binary coded decimal codes (BCD) all of which are
used to represent decimal digits. BCD codes have at least 4 bits and at least 6 unassigned
or unused code words.
Examples:
(a) 8421 BCD code, sometimes referred to as the Natural Binary Coded Decimal Code
(NBCD);
(b)* Excess-3 code (ES-3);
(c)** 84 –2 –1 code (+8, +4, –2, –1);
(d) 2 4 2 1 code
Self complementing BCD codes
The excess 3, 8 4–2–1 and 2421 BCD codes are also known as self complementing
codes.
Self complementing property– 9’s complement of the decimal number is easily obtained
by changing 1’0 to 0’s and 0’s to 1’s in corresponding codeword or the 9’s complement
of self complementing code word is the same as its logical complement.
Ex: The decimal digit 3 in 8.4–2–1 code is coded as 0101. The 9’s complement of 3 is 6.
The decimal digit 6 is coded as 1010 that is 1’s complement of the code for 3. This is
termed as self complementing property.
Non Weighted Codes
These codes are not positionally weighted. This means that each position within a binary
number is not assigned a fixed value. Excess-3 codes and Gray codes are examples of
nonweighted codes.
Gray code (Unit Distance code or Reflective code)
There are applications in which it is desirable to represent numerical as well as other
information with a code that changes in only one bit position from one code word to the
next adjacent word. This class of code is called a unit distance code (UDC). These are
sometimes also called as ‘cyclic’, ‘reflective’ or ‘gray’ code. These codes find great
applications in Boolean function minimization using Karnaugh map.
Binary to Gray conversion
(1) Place a leading zero before the most significant bit (MSB) in the binary number.
(2) Exclusive-OR (EXOR) adjacent bits together starting from the left of this number will
result in the Gray code equivalent of the binary number.
Gray to Binary conversion
Scan the gray code word from left to right. The first 1 encountered is copied exactly as it
stands. From then on, 1’s will be written until the next 1 is encountered, in which case a 0
is written. Then 0’s are written until the next 1 is encountered, in which case a 1 is
written, and so on.
EX:Convert Gray code word 1111011 into binary.

1111011
↓ ↓ ↓ ↓ ↓ ↓ ↓ ⇒ (1111011) Gray = (1010010)2.
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1010010
Example 2. Convert Gray code word 10001011 into binary.
10001011
↓↓↓↓ ↓ ↓ ↓ ↓
11110010
⇒ (10001011) Gray = (11110010)2.
Error Detecting Codes:
In a single bit error, a 0 is changed to a 1 or a 1 is changed to a 0.
In a burst error, multiple (two or more) bits are changed.
The purpose of error detection code is to detect such bit reversal errors. Error detection
uses the concept of redundancy which means adding extra bits for detecting errors at the
destination.
For single bit error detection, the most common way to achieve error detection is by
means of a parity bit.
Checksums–The checksum method is used to detect double errors in bits. Since the
double error will not change the parity of the bits, the parity checker will not indicate any
error.
Error Correcting Codes
Block codes: [(n, k) codes] in block codes, each block of k message bits is encoded into a
larger block of n bits (n > k), as shown. These are also known as (n, k) codes.
Hamming distance and minimum distance
The weight of a code word is defined as the number of nonzero components in it. For
example,
Code word Weight
010110 3
101000 2
000000 0
The ‘Hamming distance’ between two code words is defined as the number of
components in which they differ.
For example, Let U = 1010
V = 0111
W = 1001
Then, D (U, V) = distance between U and V = 3
Similarly, D (V, W) = 3 and D (U, W) = 2
The ‘minimum distance’ (Dmin) of a block code is defined is the smallest distance
between any pair of codewords in the code.
From Hamming’s analysis of code distances, a minimum distance (Dmin) of at least 3 to
correct single error and with this minimum. distance we can detect upto 2 errors.
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Chapter-2 LOGIC GATES

 A gate is an electronic circuit with one and one or more inputs. the output always
depends on the input combinations
 AND,OR and NOT gates are called Basic gates
 NAND and NOR gates are called universal gate, because, by using only NAND
gates or by using only NOR gates we can realize any gate or any circuit
 Special gates are Exclusive-OR gate and exclusive –NOR gate
 Exclusive-NPR(X-NOR) gate is also called inclusive-OR gate of equivalence
 Three are two types of logic systems:
a )positive level logic system
b) Negative level logic system
 Positive level logic system(PLLS):out of the given two voltage levels, the more
positive value is assumed as logic ‘1’ and the other as logic ‘0’.
Logic ‘0’ Logic ‘1’

0V 5V
-2V +3V
-7V -2v
+2V +7
 Negative level logic system (NLLS): Out of the given two voltage levels, the
more negative value is assumed as logic ‘1’ & the other as logic ‘0’.
Logic ‘1’ Logic ‘0’

0V 5V
-2V +3V
-7V -2V
+2V +7V
 NOT gate: It is also called inverter. “The output of a NOT gate is always
compliment of the input”.
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Truth Table:
A Y
0 1
1 0
 And -gate: the output of AND gate is high if all the inputs are high. Or the output
of and gate is low if any one input is low or all the inputs are low.
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Internal circuit diagram of AND gate with positive level logic system.
 OR-gate: the output of an OR gate is high if any one input is high or all inputs are
high. The output of an OR gate is zero if all the inputs are zeros
Internal circuit diagram of OR gate with positive level logic system.
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
 The circuit, which is working as OR gate with positive level logic system, will
work as AND gate with negative level logic system.
 Truth table is also called table of combinations.
 The number of rows in the truth table is given by 2n where ‘n’ is the number of
inputs to the gate.
Universal Gates: NAND and NOR gates are called Universal gates.
 NAND gate: this is nothing but AND gate followed by NOT gate. “The output of
NAND gate is high if any one input or all inputs are low.
Truth Table:
A B Y
0 0 1
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1
1 0 1
1 1 0
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Realization of basic gates using NAND gates:
Gate Equivalent in NAND gates
NOT
AND
OR
NOR
 NOR gate: it is nothing but OR gate followed by NOT gate. ”the output of NOR
gate is high if all the inputs are low”.
The output of NOR gate is low if any one input is high or all inputs are high.
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A B Y
0 0 1
0 1 1
1 0 1
1 1 0
The circuit which is behaving as NAND gate with positive level logic system will
behave as NOR gate with negative level logic system and vice-versa.
Realization of basic gates using NOR gates:
Exclusive-OR gate(X-OR): the output of n X-OR gate is high for odd number of high
inputs”
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
 Realization of X-OR gates using NAND and NOR gates:
The Exclusive NOR gate: The Exclusive NOR gate is sometimes reffered to as the
‘COINCIDENCE’ or ‘EQUIVALENCE’ gate. This is often shortened as ‘XNOR’
gate. ‘The unique output of the XNOR gate is a LOW only when an odd number of
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inputs are HIGH’. It is X-OR followed by NOT. The output is high for odd number of
low inputs. The output is high for even number of high inputs.
Truth table Logic Symbol
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Realization of X-OR gates using NAND and NOR gate
 Realization of basic gates using NAND and NOR gates:


 The minimum number of NAND gates required to realize X-OR gate if four.
 The minimum number o NOR gates required to realize X-OR gate is five.
 Realization of x-nor gate using NAND and NOR gates:
 The minimum number of NAND gates required to realize X-NOR gate is 5
 The minimum number of NOR gates required to realize X-NOR gate is 4.
 Alternate logic gate symbols: the alternate logic gate symbols for the standard
gate symbols are obtain by interchanging AND & OR symbols, and by inverting
all inputs and outputs.
 A bubbled NAND gate is equivalent to OR gate.
 A bubbled NOR gate is equivalent to AND gate.
 A bubbled AND gate is an equivalent to NOR gate.
 A bubbled OR gate is equivalent to NAND gate.
 The alternate logic gate symbols for the standard gates are obtained based on
Demorgn’s laws only.
1) What Gates to be used in design??
• OR, AND, NOT are basic gates and can implement all logic functions.
NAND and NOR are universal gates and can also implement all types of logic functions.
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2) What is a good choice??
The deciding factors are:
– Cost
– Possibility of extending the gate to more than two inputs
• NAND and NOR are more popular choices.
Chapter-3 Boolean algebra
Points to Remember
 Boolean algebra works with binary variables
 A Boolean algebra is an algebraic system consisting of the set [0, 1] the binary
operations called OR, AND, or NOT denoted by the symbols”+”,”.” and “prime”.
 Boolean algebra enables the logic designer to simplify the circuit used, achieving
economy of construction and reliability of operation.
 Boolean algebra suggests the economic and straightforward way of describing the
circuitry used in any computer system
 Boolean algebra is unique in the way that; it takes only two different values either
0 or 1.
 It does not have negative number. It does not have fraction number.
 The basic Boolean postulates:
Logical Multiplication s based on AND functions.
0.0=0
0.1=0
1.0=0
1.1=1
Logical Additions based on OR function
0+0=0
0+1=1
1+0=1
1+1=1
Complement based on NOT function
0’=1
1’=0
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 Boolean properties:
A) Properties of AND function
X.0 =0
0. X =0
X.1 =X
1. X =X
B) Properties of OR function
X+0=X
0+X=X
X+1=X
1+X=1
C) Combining a variable with itself or its complement

X.X’=0
X.X=X
X+X=X
X+X’=1
(X’)’=X
D) Cumulative laws:
X.Y=Y. X
X+Y=Y+X
E) Distributive laws:
X(Y+Z) =X.Y+X.Z
X+(Y+Z) =(X+Y) +Z
G) Absorption laws:
X+XY=X
X(X+Y)
X+X’Y=X+Y
X (X’+Y) =XY
H) Demorgan’s laws:
(X+Y)’=X’.Y’
(X.Y)’=X’+Y’
 In Boolean algebra’1’ is called multiplicative identity and ‘0’ is called additive
identity.
 Literal a primed or unprimed Boolean variable called literal. Each variable can
have maximum of two literals. Example :X is a variable which can have two
literals X and X’
Proof for some important properties:
X+YZ=(X+Y) (X+Z)
(X+Y)(X+Z)=X.X+X.Z+X.Y+YZ
=X+XZ+XY+YZ
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=X (1+Z) + X.Y+Y.Z
=X+X.Y+YZ
= X (1+Y) +YZ=X+YZ
X+X’Y=X+Y
= (X+X’) (X+Y) =X+Y
X (X’+Y) =XY
X (X’+Y) =XX’+XY=0+XY=XY
BOOLEAN FUNCTION MINIMIZATION TECHNIQUES

Logic circuit can be simplified by simplifying the Boolean equation using any one of the
following methods:
1) Minimization using Postulates and Theorems of Boolean algebra
2) Using K-Map technique
3) Using Tabulation method
MINIMIZATION USING POSTULATES & THEOREM OF BOOLEAN ALGEBRA:
Boolean properties can be applied successively to minimize the given Boolean equations
 But there is no guarantee that always we get minimal equation in this method.
 2,3 and 4 variable equation can be simplified to minimal value quickly using k-
map method
 Tabulation method is used to minimize the equations with high order variables
 The properties of Boolean algebra are useful for the simplification of Boolean
equation leading to minimal gate structure.
 Simplify the Boolean equation
Z=XY+X’(X+Y)
=XY+X’(X+Y) =XY+X’.X+X’Y=XY+X’Y
= (X+X’) Y=Y.
 Duality Principle: the important of Boolean algebra is the duality principle.” It
states that every algebraic expression deducible from theorems of Boolean algebra
remains valid if the operations and identify elements are interchanged.
Examples:
X+X=X X.X=X by duality
X+1=1 X.0=0 by duality
X+XY=X X(X+Y) =X by duality
X+Y=Y+X XY=YX by duality
X+(Y+Z) =(X+Y) +Z X (YZ) = (XY) Z by duality
 The dual of the exclusive-OR is equal to its complement
 A simple procedure to find the complement of a function is to take the dual of the
function and complement each literal
Standard Forms of Boolean Functions:
1) Standard forms help in simplifying the Boolean expressions and frequently results in
more desirable logic circuits.
2) Standard forms contain product terms and sum terms.
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• Product terms (example X’YZ)
• Sum terms (example X+Y+Z’)
3) In Boolean algebra, product means logical AND operation and sum means logical OR
operation.
4) Two standard forms Standard forms of Boolean functions are:
• Sum-of-Products (SOP)
• Product-of-Sums (POS)
5) Product terms are called minterms and sum terms are called maxterm
MINTERM: A product term in which all the variables appear exactly once, either
complemented or uncomplemented is called a minterm.
• Property: It represents exactly one combination of the binary variables in a truth table. It
has the value ‘1’ for that combination and ‘0’ for all others.
• For n variables there are 2n distinct minterms.
• Example: Given two variables X, Y, the four minterms are X’Y’, X’Y, XY’ and XY.
• The symbol for a minterm is mj, where j denotes the decimal equivalent for which the
minterm has the value of 1.
 Standard product or a minterm (m): consider two binary variables x and y
combined with an AND operation. Since each variable appears in different form
or in its complement form there are four possible combinations. X’Y’, X’Y, XY’
and XY. Each of these four AND terms is called a minterm or a standard product
term.
2-Variable: X Y Minterm (m)
0 0 X’.Y’ m0
0 1 X’.Y m1
1 0 X.Y’ m2
1 1 X.Y m3
Standard sum or Maxterm(M): A sum term that contains all the variables in
complemented or uncomplemented form is called a maxterm.
• For n variables there are 2n distinct maxterms.
• Each maxterm is the logical sum of the variables, with each variable being
complemented if the corresponding bit of the binary number is 1 and uncomplemented if
it is 0.
• The symbol for a maxterm is Mj where j denotes the decimal equivalent of the binary
combination for which the maxterm has the value 0.
• Example: Given two variables X, Y, the four maxterms are (X+Y), (X+Y’), (X’+Y),
and (X’+Y’). Each of these four OR terms is called a maxterm or a standard sum term.
X Y Maxterm (M)
0 0 X+Y M0
0 1 X+Y’ M1
1 0 X’+Y M2
1 1 X’+Y’ M3
3-Variable:
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 Maxterm is the complement of its corresponding Minterm and vise versa.

Eg:XY=minterm. The complement of minterm= (XY)’=X’+Y’=maxterm
Sum-of-Products (SOP) is the simplified form of the Sum-of-Minterms. An SOP

expression is equal to 1 only if one or more of the product terms in the expression is
equal to one.
Product-of-Sums (POS) is the simplified form of Product-of-Maxterms. A POS

expression is equal to 0 only if one or more of the sum terms in the expression is equal to
zero.
 Conical form: Expressing the Boolean function in standard sum of product form
(SSOP) or Standard product Sums form (SPOS) is called Canonical form.
 A Boolean function may be expressed algebraically from a given truth table by
forming a minterm for each combination of the variables which produces a 1 in
the function, and then taking the OR of all those terms.
X Y F
0 0 0
0 1 1
1 0 1
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1 1 0
F=(X+Y) (X’+Y’) =ПM (0, 3)

This representation is called SPOS form.
 A Boolean function may be expressed algebraically from a given truth table by

forming the maxterms for each combination of the variables which produces
zero’0’ in the function ,and then taking the AND of all those terms.
X Y F
0 0 0
0 1 1
1 0 1
1 1 1
 If one canonical form is given it is possible to express other canonical form

Example: the other canonical from of the equation F(X, Y, Z) = ПM (0, 2, 3, 6) is
F(X, Y, Z) =∑m (1, 4, 5, 7)
 Sum of all the minterms of a given Boolean function is equal to 1
Example:(X,Y,Z)=∑m(0,1,2,3,4,5,6,7)=1
 Product of all the maxterms of a given Boolean function is equal to 0
Ex: F(X,Y,Z)= ПM (0,1,2,3,4,5,6,7)=0
 Boolean functions expressed as a sum of minterms or product of maxterms are
said to be in canonical form
 Sum of product form can be implemented by using 2-level NAND- NAND logic.
 NAND-NAND realization is same as AND-OR
 Product of sum terms form can be implemented by using 2-level NOR-NOR logic
 NOR-NOR realization is same as OR-AND
 If the signals are propagating through two stages of gates, then it is called two-
level gate network.
 Degenerative Form: a two level gate network is said to be degenerative if it
degenerates to a single operation
Ex: AND-AND is equivalent to AND
 The following 2-level gate networks are Degenerative forms:
AND-AND AND
OR-OR OR
OR-NOR NOR
AND-NAND NAND
NOR-NAND OR
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NAND-NOR AND
2) K-Map technique:KARNAUGH MAPS (K-maps): A K-map is a diagram made up of
sequence represents either a minterm or a maxterms
 The number of square in the k-map is given by 2n.where n= number of variable.
 2variable k-map consists of 4-cells or squares
 3variablek- map consists of 8 squares or 8-cells
 4 variable k- maps consists of 16-squares or 16 cells
 to maintain adjacency property gray code sequence is used in k-maps(any two
adjacent cells will differ by only one bit)
Authorised By
2, 3, 4 & 5 Variable K-maps:
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Construct the K-map:

1. Enter 1 in those squares corresponding to the minterms for which function value is 1.
Leave empty the remaining squares.
2. Examine the map for squares that can not be combined with any other squares and
from group of such signal squares.
3. Now, look for squares which are adjacent to only one other square and form groups
containing only two squares and which are not part of any group of 4 or 8 squares. A
group of two squares is called a pair.
4. Next, Group the squares which result in groups of 4 squares but are not part of an 8-
squares group. A group of 4 squares is called a quad.
5. Group the squares which result in groups of 8 squares. A group of 8 squares is called
octet.
6. Form more pairs, quads and outlets to include those squares that have not yet been
grouped, and use only a minimum no. of groups. There can be overlapping of groups if
they include common squares.
7. Omit any redundant group.
8. Form the logical sum of all the terms generated by each group.
Using Logic Adjacency Theorem we can conclude that,
— a group of two squares eliminates one variable,
— a group of four squares. Eliminates two variable and a group of eight squares
eliminates three variables.
Rules to simplify K-maps:
1. At the time of grouping the adjacent cells containing 1’s always use maximum possible
group.
2. All the cells containing 1’s must be covered at least once m any group.
3. At the time of grouping don’t cares (X) values can be taken as 1’s
4. All don’t care values need not be covered.
 Tabulation method is used to simplify Boolean expressions when there are more
than 5 variables
 In an n- variable k-map combining 8 adjacent cells containing 1’s as a group will
result a term of (n-3)literals
 In an n- variable k-map combining 8 adjacent cells containing 1’s as a group will
eliminate 3 variables.
 Sum of number of variables eliminates and number of literals present in the
resulting term is always equal to the number of variables in the k-map.
Number of No. Of Cells No. of No of literals

variables containing 1’s variables present in the
grouped eliminated resulting term
2 4 2 0
2 1 1
1 0 2
3 8 3 0
4 2 1
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2 1 2
1 0 3
4 16 4 0
8 3 1
4 2 2
2 1 3
1 0 4
• While combining the squares in K-maps it is necessary to ensure that all the minterms
are included.
• To minimize the number of terms in the simplified function any redundant term has to
be avoided. So, the procedures of merging the squares need to be systematic.
• Three terms introduced to systematize the combining procedure are listed below.
 Implicant
 Prime Implicant
 Essential Prime Implicant
• An implicant is a product term (product of one or more literals) that could be used to
cover minterms of the function. All the rectangles on a map made up of squares
containing 1’s correspond to implicants.
• A prime implicant is an implicant that is not a part of any other implicant of the
function. Equivalently, prime implicant is a set of squares that is not a subset of any set
containing larger number of squares.
• An essential prime implicant is a prime implicant that covers at least one minterm that
is not covered by any other prime implicant.
MINIMIZATION USING QUINE-MCCLUSKEY (TABULAR) METHOD:
The K-map method is suitable for simplification of Boolean functions up to 5 or 6
variables. As the number of variables increases beyond this, the visualization of adjacent
squares is difficult as the geometry is more involved.The ‘Quine-McCluskey’ or
‘Tabular’ method is employed in such cases. This it a systematic step by step procedure
for minimizing a Boolean expression in standard form.
Procedure for Finding the Minimal Expression:
 Arrange all minterms in groups, such that all terms in the same group have same
number of 1’s in their binary representation.
 Start with the least number of 1’s and continue with grouping of increasing
number of 1’s. the number of 1’s in each term is called the index of that term i.e.,
all the minterms of some index are placed in a some group. The lowest of value
index is zero.
 Separate each group by a thick line. This constitutes the I stage.
 Compare every term of the lowest index (say i) group with each term in the
successive group of index (say, i + 1).
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 If two minterms differ only one variable, that variable removed and a dash (–) is
placed at the position, thus a new term with only less literal is formed. If such a
situation occurs, check marks is placed next to both minterms.
 After all pairs of terms with indices i and (i + 1) have been considered, a thick
line is drawn under the last terms.When the above process has been repeated for
all the groups of I stage, one stage of elimination have been completed. This
constitutes the II stage.
 The III stage of elimination should be repeated of the nearly formed groups of
second stage. In this stage, two terms can be compared only than they have dashes
in some positions.
 The process continues to next higher stages until no further comparisons are
possible. (i.e., no further elimination of literals).
 All terms which remain unchecked (No sign) during the process are
considered to be prime implicants (PIs). Thus, a set of all PIs of the function is
obtained.
 From the set of all prime implicates, a set of essential prime implicants (EPIs)
must be determined by preparing prime implicant chart as follow.
 The PIs should be represented m rows and each minterm of the function in a
column.
 Crosses should be placed in each row to show white composition of minterms that
makes the PIs.
 A complete PIs chart should be inspected for columns containing only a single
cross. PIs that cover minterms with a single cross in their column are called EPIs.
 The minterms which are not covered by the EPIs are taken into consideration and
a minimum cover is obtained form the remaining PIs.
Chapter-4 LOGIC GATE FAMILIES
 Digital IC gates are classified not only by their logic operation, but also by the
specific logic circuit family to which they belong. Each logic family has its own
basic electronic circuit upon which more complex digital circuit and functions are
developed.
 Different types of logic gate families:
RTL: Resister transistor logic gate family.
DCTL: Direct coupled transistor Logic gate family
RCTL: resistor capacitor transistor logic
DTL: Diode Transistor logic gate family
TTL: Transistor Logic gate family
IIL: Integrated injection logic
HTL: High threshold Logic
ECL: Emitter coupled logic
MOs: Metal Oxide Semi conductor
CMOS: Complementary Metal Oxide Semi-conductor
Some Common 74xx gates
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• 7404 - inverter
• 7400 (2-input NAND), 7402 (2 Input Nor)
• 7408 (2-input AND), 7432 (2-input OR)
• 7410 (3-input NAND)
• 7486 (2-input XOR)
• 7420 (4 input NOR)
 HTL is a modified from of DTL and IIL is a modified form of DCTL
 Because of high package density MOS and I2L logic gate families are used for
Large Scale integration (LSI) functions.
 TTL, ELC and CMOS are used for medium Scale Integration (MSI) or Small
Scale Integration (SSI).
 Each logic gate family is identified with a series number. For example TTL
family ICs are variable in 74/54 series.CMOS IC’s usually designed with 4000
series and ECL family with 10000 series.
 RTL, DTL, ECL, and I2L Logic families use bipolar transistors. Hence these
families are called bipolar logic gate families.
 MOS and CMOS families’ uses unipolar transistors called Metal-Oxide
Semiconductor Filed effect Transistor. Hence these families are called unipolar
logic gate families.
 Fan-out: the number of standard loads that the output of the gate can drive without
disturbing its normal operation
 Fad-in: the maximum number of inputs that can be applied to the logic gate.
 Power dissipation: the power consumed per gate.
 Propagation delay: the average transition delay time for the signal to propagate
from input to output when the signals change in value.
 Noise Margin: it is the limit of a noise voltage which may be present without
impairing the proper operation of the circuit.
 Figure of merit: the product of propagation delay time and power dissipation is
known as figure of merit of performance of a gate. Normally minimum value is
desired.
 Logic Swing: the difference between the two output voltages(VoH-VoL) is known
as the logic swing of the circuit
 Noise Immunity: the ability to with stand variation in they input levels
 Saturation logic: a form of logic gates in which one output state is the saturation
voltage level of the transistor. Ex: RTL, DTL, TTL.
 Unsaturated logic or Current Mode Logic: a form at logic with transistor operated
outside the saturation region. Ex: CML or ECL.
 ECL has ultra-fast switching speed and low logic swing.
 The temperature range of 74-series of TTL logic gate family is 00C to 700C.this
series of IC’s is used for commercial applications
 The temperature range of 54-series of TTL logic gate family is -550C to
1250C.this series of IC’s is used for Military l applications
 Voltage parameters of the digital ICS:
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 High level input voltage,V1H:this is the minimum input voltage which is
recognized by the gate as logic 1
 Low level input voltage,V1L:this is the maximum input voltage which is
recognized by the gate as logic 0
 High level output voltage,V0H:this is the minimum voltage available at the output
corresponding to logic 1
 Low level output voltage, VOL: this is the maximum voltage available at the output
corresponding to logic 0.
 The number of various functions available in a logic family is known as the
breadth of logic family.
 When the output of logic gates is connected together additional logic functions are
performed. This is known as wired logic.
 When the output is available in complemented as well as un complemented form
it is referred to as complementary outputs. This eliminates the need of using
additional inverters.
 Passive pull-up: in a bipolar logic circuit, a resistance Rc used in the collector
circuit of the output transistor is known as passive pull-up.
 Active pull-up: in a bipolar circuit a BJT and diode circuit used in the collector
circuit of the output transistor instead of Rc is known as active pull-up. this
facility is available is TTL
 The advantages of active pull-up over passive pull up are increased speed of
operation and reduced power dissipation
 Open collector output: in a bipolar logic circuit if nothing is connected at the
collector of the output transistor and this collector terminal is available as IC pin,
it is known as open collector output.
 Tri-state logic: in the tri-state logic, in addition to low impedance 0 and 1 there is
a third state known as the high-impedance state. When the gate is disabled it is in
the third state.
 In TTL logic gate family three different types of output, configurations are
available: they are open collector output type, totem-pole output type and tri-state
output type.
 The advantages of open-collector output type are wired-logic can be performed
and loads other than the normal gate can be used.
 The tri-state logic devices are used in bus oriented systems.
 If any input of TTL circuit is left floating, it will function as if it is connected to
logic 1 level.
 The supply voltage range of 74-series is 5±0.25V and for 54-series is 5 ±0.5 V
 Negative supply is performed in ECL family because, the effect of noise present
in the supply line is reduced considerably and any accidental short-circuiting of
output to ground will not damage the gate.
 MOS logic is mainly used for LSI and VLSI applications because the silicon chip
area required for fabrication of a MOS device is very small.
 The fan-out of MOS logic gates is very high because of their high input
impedance.
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 If any unused input terminal of a MOS gate is left unconnected, a large voltage
may get induced at the unconnected input which may damage the gate.
 Different versions available in TTL logic gate family
74/54L: Low-power
74/54H: High-power/high-speed
74/54LS: Low-power Schottky
74/54S: Schottky
74/54 LS: Low power Schottky
74/54 AS: Advanced Schottky
74/54 ALS: Advanced Low-Power Schottky
 The supply voltage required for ECL logic family is -5.2V±10%
 Comparison of Different Logic Gate families:
DTL TTL ECL CMOS PMOS

Fan-out 8 10 25 50 20
Propagation Delay 30nsec 10nsec 4nsec 70nsec 300nsec
Power Dissipation 8mW 10mW 40mW 0.01mW 0.2-10mW
Noise Margin (min) 700mV 400mV 200mV 300mV 150mV
 Faster logic gate family is ECL. it is also called current model Logic
 Slowest Logic gate family is CMOS
 The logic gate family, which consumes less power CMOS
 The logic gate family, which consumes more power ECL
 The logic gate family, which is having highest fan out CMOS
 In CMOS circuit, nMOS transistor conducts if the gate to source voltage is more
positive where as pMOS conducts if gate to source voltage is more negative.
 NMOS is faster than PMOS
 In tristate logic in addition to two low impedance outputs 0 and 1, there is third
state known as high impedance state.
TTL Logic Circuits: If the diodes of DTL gate are replaced by transistor. The
modified circuit, called TTL.
 TTL standard Inverter
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 Standard 2 input TTL NAND gate
 2-input NAND gate with Totem-pole output configuration.
 The diode “D1” is used to keep the transistors Q4 in OFF stats when Q# is in ON
state.
 2-input NAND gate with open-collector output configuration.
 Gates with open collector output can be used for wired-AND operation
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. =
 Wired-AND operation is equivalent to AND –OR-INVERT

Emitter Coupled Logic:
 OR/NOR is the fundamental logic gate of the ECL family.
 ECL is another NON Saturated LOGIC FAMILY in which transistors are driven
into cutoff and active region.
 The ECL family offers improved noise performance and is fastest of all logic
families. Infact propagation delays as low as 1 n sec is possible with ECL.
 The circuit in essence comprises a differential amplifier input circuit with one side
of the differential pair having multiple transistors depending upon the number of
inputs to the gate, a voltage- and temperature-compensated bias network and
emitter follower outputs.
 Infact the basic TTL, DTL, RTL etc. all have limits on their speed because they
are based saturation region operation of transistors.
 If transistors are driven in active region, then the speed can be dramatically
improved. But active region spans to a small voltage width and small temperature
variations, component drift can shift the transistors to saturation.
 Thus stable operation in active region is difficult.
 A high emitter resistance can solve this problem, but poses another problem. It
makes difficult to turn the transistor in active region from cutoff region with small
voltage change at input.
 The problem can be solved if current drawn by the transistors from supply is not
switched OFF and ON.
 The difference amplifier is a circuit in which current drawn from supply is never
switched OFF; rather it is shifted from one transistor to another.
 Also note that using difference amplifier offers high CMRR means there is
effective rejection of noise.
Symbol of ECL OR/NOR

gate:
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ECL OR/NOR Gate
 Similar to open collector output in TTL, open emitter outputs are available in
ECL. The outputs of two or more ECL gates can be connected to get
additional logic without using additional hardware. Wired-OR operation is
possible with ECL ckts
Authorised By
Wired –OR operation is equivalent to OR-AND-Inevrt

If any input of an ECL gate is left unconnected, the corresponding E-B junction will not
be conducting. Hence it acts as if a logical 0 level voltage is applied to that input. i.e In
ECL ICs, all unconnected/floating inputs are treated as logical OS.
MOS LOGIC:
MOS Logic have become popular logic because of their high packing density however
have larger propagation delays and thus have slower speed than the bipolar logic families.
MOS devices can be fabricated even in much smaller areas, which implies that
propagation delays will be low. Another advantage of MOS is, can use only MOS devices
without using any resistor. A MOS device itself can be configured as resistance either
enhance mode or Depletion mode devices can be as load, preferred are depletion mode
load. It is because the depletion mode MOS have maximum current when gate voltage is
O. It is good to use MOS as load resistance because a normal resistor takes area 20 times
of area taken by a MOS device.
NMOS Gate Circuits
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PMOS GATE circuits:
CMOS Gate circuits: A logic circuit that combines p-channel and n-channel MOS
transistors on the same chip is known as complementary MOS or CMOS circuit. Major
advantage of CMOS is very low power dissipation. Since technology has improved such
that a very small chip area is required to fabricate MOS devices the CMOS can now
operate on faster speed. Indeed the CMOS circuits have already replaced TTL in many
practical applications. CMOS can operate over a supply range of 3.3 V to 15V. But lower
power supply reduces the noise immunity.
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Transistor Counts (CMOS)
Inverter: 2 transistors
Two input NAND: 4 transistors
Two input AND: 6 transistors
Two input NOR: 4 transistors
Two input OR: 6 transistors
Three input NAND: 6 transistors
Three input AND: 8 transistors
Three input NOR: 6 transistors
Three input OR: 8 transistors
NAND, NOR gates are better than AND, OR gates because they take less transistors.
NAND gates better than NOR gates because they are faster (we won’t discuss why, you
will find out in
Three State Logic (TSL)
 In a logic circuit we have two output states LOW and HIGH.

 Logic circuits have been designed in which output can assume another state called
High impedance state or High. Z
 Logics with three states of output are called tristate logic (TSL) or three state
logic.
 When the output is in third state, the output is said to be disabled i.e., neither
HIGH nor LOW.
 In a microprocessor based system outputs of many logic devices has to be
connected to a common bus which in turns may be driving number of other logic
devices.
Such connections cause a number of problems–
1. If the output is not in HIGH state it does not necessarily mean LOW state output.
2. Accidentally more than one logic device may drive the bus and can cause bus
contention, which may damage the bus.
3. Active pullup outputs cannot be directly connected, because it introduces very high
current spike. This causes overheating of IC and consequently IC may be damaged
4. Connecting open collector output through a common external resistor causes problem
of loading and speed.
To overcome such problems TSL are used, in which outputs are in High-Z, and they
deliver a HIGH or LOW to bus only when they are made to come out of 3rd state through
a control input.
The basic TSL circuit is an inverter called TSL inverter. A close inspection of circuit
reveals that it is a TTL NAND gate with some modification.
TSL INVERTER:
CONTROL INPUT A Y
0 X Z
1 0 1
1 1 0
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(a)Logic Symbol of TSL Inverter (b) TTL TSL Inverter
Chapter-5 Combinational digital Circuits
 Digital circuits can be classified into two types:

1. Combinational digital circuits
2. Sequential digital circuits
Combinational digital circuit:
Combinational logic circuits are circuits in which the output at any time depends upon the
combination of input signals present at that instant only, and does not depend on any past
conditions. The block diagram of a combinational circuit with m inputs and n outputs is
shown in Fig.
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 For the design of combinational digital circuits basic gate (AND, OR, NOT) or
universal gates (NAND, NOR) are used.
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Block Diagram of combinational Logic circuit.
Combinational circuit Design Procedure: It involves following steps:

Step 1: From the word description of the problem, identify the inputs and outputs and
draw a block diagram.
Step 2: Make a truth table based on problem statement which completely describes the
operations of circuit for different combinations of inputs.
Step 3: Simplified output functions are obtained by algebraic manipulation, k-map
method or tabular method.
Step 4: Implement the simplified expression using logicgentis.
Some of CLCs:
1. Adders 2. Subractors 3. Multipliers 4. Comparators 5. Code Converters
6. Encoders 7. Decoders 8. Multiplexers 10. De-multiplexers
11. Parity generators & Parity checkers
ADDERS: They are CLCs, which are used to add the binary numbers.
 1. Half-Adder: It is a combinational circuit that performs the addition of two bits
is called a half-adder. it consists of two inputs and two outputs
S = A ⊕B
C = A.B
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 2. Full-Adder: a combinational circuit that performs the addition of three bits is
called a full-adder .it consists of three inputs and two outputs
Inputs Outputs
AB C S C0
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum= ∑(1,2,4,7) Carry= ∑(3,5,6,7)

S= A ⊕ B ⊕ C Co= A.B +C ( A ⊕B )
SUBTRACTORS: They are CLCs, which are used to subtract the binary numbers
1. Half Subtractor
2. Full Subtractor
 Half subs tractor: it is a combinational; circuit that subtracts two bits and produces
their difference. It also has an output to specify is a ‘1’ has been borrowed.
Difference, D= A ⊕ B
Borrow, Bo= AB
Inputs Outputs
A B D Bo  Half adder can be
1 0 0 0 converted into half
subtract or with an
0 1 1 1 additional inverter.
1 0 1 0  Full Subtractor: Full
1 1 0 0 subtractor subtracts
one bit from the other by taking previous borrow into account and generates
difference and borrow.
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Inputs Outputs
A B C D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
Difference, 1 0 1 0 0
D= ∑(1,2,4,7) D= 1 1 0 0 0
A ⊕ B ⊕C 1 1 1 1 1
Borrow, Bo= ∑ (1, 2,3,7 )
Bo= A.B +C ( A ⊕B )
 Quarter adder/subs tractor: the sum output of half adder is called Quarter adder.
The difference output of half substarctor is called Quarter subtract or. quarter
adder/subtract or is a same as two input XOR gate
 Four bit binary parallel adder can be constructed by using three full adders and
one half adder or by using four adders with input carry for least significant bit full
adder is zero.
Four bit binary parallel adder shown in figure is also called Ripple carry adder.
4-bit Look-ahead Carry Generator:

The look-ahead carry generator is based on the principle of looking at the lower order bits
of addend and augend if a higher order carry is generated. This reduces the carry delay by
reducing the number of gates through which a carry signal must propagate. It can be
explain with the logic diagram of a full adder circuit.
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Authorised By
Where, Pi = Ai ⊕ Bi; called carry propagate, & Gi = Ai. Bi, called carry generate.
Boolean function for the carry output of each stage and substitute for each Ci its value
from the previous equations:
C1 = G 0 + P 0 C0
C2 = G1 + P1 C1 = G1 + P1 (G0 + P0 C0) = G1 + P1 G0 + P1 P0 C0.
C3 = G2 + P2 C2 = G2 + P2 (G1 + P1 G0 + P1 P0 C0)
= G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0.
 Carry look-ahead adder is faster than ripple carry adder
4-bit binary parallel adder with a look-ahead carry generator (FAST ADDER):
In the 4-bit look ahead carry generator. The carry outputs are generated simultaneously
with the application of Augend word, addend word and the input carry. What is
remaining are the sum outputs.
The sum output Si = Pi ⊕ Ci.
S0 = P0 ⊕ C0 = A0 ⊕ B0 ⊕ C0
S1 = P1 ⊕ C1 = A1 ⊕ B1 ⊕ C1
S2 = P2 ⊕ C2 = A2 ⊕ B2 ⊕ C2
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S3 = P3 ⊕ C3 = A3 ⊕ B3 ⊕ C3.
Similarly carry output Ci+1 = G1 + Pi Ci
⇒ Final o/p carry ⇒ C4 = G3 + P3 C3.
Using the above equations, the 4-bit binary parallel adder with a look ahead carry
generator can be realized as shown in Fig.
From the diagram, the addition of two 4 bit numbers can be done by a look ahead carry
generator in a 4 gate propagation time.
Also, to realize that the addition of n-bit binary numbers takes the same 4-stage
propagation delay.
Comparator: It is a CLC used to compare two binary numbers. And produces 3 outputs
Ex: 1- Bit comparator
4-Bit Comparator:
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Code Converters
A code converter is a combinational logic circuit that changes data presented in one type
of binary code to another type of binary code. A general block diagram of a code
converter is shown in Fig.
Code converter
Binary to gray code converter: If has
four inputs (B3 B2 B1 B0) representing 4-bit binary numbers and four outputs (G3 G2
G1 G0) representing 4-bit gray code.
G3 = Σ (8, 9, 10, 11, 12, 13, 14, 15)

G2 = Σ (4, 5, 6, 7, 8, 9, 10, 11)
G1 = Σ (2, 3, 4, 5, 10, 11, 12, 13)
G0 = Σ (1, 2, 5, 6, 9, 10, 13, 14).
G3 = B3
G2= B3 ⊕ B2
G1= B2 ⊕ B1
G0= B1 ⊕ B0
EXCESS-3 to BCD code converter:
It has four inputs (E3, E2, E1, E0) representing 4 bit EXCESS-3 number and four outputs
(B3B2 B1 B0) representing 4-bit BCD code.
B3 = Σ (m11, m12), d (m0, m1, m2, m13, m14, m15)

B2 = Σ (m7, m8, m9, m10), d (m0, m1, m2, m13, m14, m15)
B1 = Σ (m5, m6, m9, m10), d (m0, m1, m2, m13, m14, m15)
B0 = Σ (m4, m6, m8, m10, m12), d (m0, m1, m2, m13, m14, m15).
⇒ B3 = E3 E2 + E3E1E0
⇒ B2 = E2' E0' + E2 E1 E0
B1 = E1 ⊕ E0
B0 = E0'
Parity Generators and Checkers:
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 When digital date is transmitted from Transmitter to receiver, to know at the
receiving end, whether the received data is free of error.
 To make the transmission accurate, special error detection methods are used.
 To detect errors, keep a constant check on the data being transmitted.
 To check accuracy we can generate and transmit an extra bit along with the
message (data).
 This extra bit is known as the parity bit and it decides whether the data
transmitted is error free or not.
 There are two types of parity bits, namely even parity and odd parity.
In a 3-bit even parity generator, the parity bit generated is such that it makes total
member of 1s even
Data bits Parity

A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
P=A ⊕ B ⊕ C
1 1 1 1
Parity Checker: The parity checker for the above 3-bit even parity is
E= (A ⊕ B) ⊕ (C ⊕ P)
Decoder: a decoder is a logic circuit the converts an n-binary input code into M (2n)
output line will be activated for only one of the possible combinations of inputs.
 A decoder is a combinational circuit that converts binary information from ‘n’
input lines to a maximum of 2n unique output lines.
Eg: 2x4 line decoder
 Decoder are available in two different types of output forms:
1) Active high output type decoder
2) Active low output type of decoders
 Active high output type of decoders are constructed with AND gates and active
low output type of decoders are constructed with NAND gates
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Examples of decoders:
 BCD-to-7-segement decoder
 BCD-7Segment decoder
 Binary decoder
 Truth table of active high output type of decoder
X Y D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
 Active low output type of decoders will give the output low for given input
combination and all other outputs are high.
 Truth table of active low output type of decoder
X Y D0 D1 D2 D3
1 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1
 3 to-8 line decoder is also called binary to octal decoder or converter. It is also
called 1-of 8 decoder because only one of the 8 outputs is activated at a time.
 Decoder are widely used in the memory system of a computer, where they
response to the address code input from the CPU to activate the memory storage
location specified by the address code.
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 Decoders are also used to convert binary data to a form suitable for displaying on
decimal read outs.
 Decoders can be used to implement combinational circuits, Boolean functions etc.
Demultiplexier: A decoder with enable inputs acts as a demultiplexer. ”a
demultiplexer is a circuit that receives information on a single line and transmit that
information on one of 2n possible output lines. The selection of specific output line is
controlled by the bit values of ‘n’ selection lines.
Multiplexer:
Multiplexing means transmitting a large number of information units over a smaller
number of channels are lines. ”a digital multiplexer is a combinational circuit that
selects binary information from one of many inputs lines and direct it a single output
line. The selection of a particular line is controlled by a set of selection lines.
Normally, there are 2n input lines and ‘n’ selection lines whose bit combinations
determine which input is selected.
 Multiplexers can be used for the implementation of Boolean functions,
combinational circuits. They can also used for parallel to serial conversion.
 Multiplexers is also called data selector or universal element
 All three variable Boolean equations can be implemented by using 8x1
multiplexer without using any additional gates. Some but not all three variable
Boolean equations can also be implemented with 4x1 mux without using any
additional gates.
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
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Encoder: a decoder identifies a particular code present at the input terminals of the
circuit. The inverse process is called encoding. ”an encoder has number of inputs (2n)
one and only one of which is in the high state or active, and an n-bit code is generated
upon which of the inputs is excited.
 A priority encoder is a practical form of an encoder. In this type of encoder, a
priority is assigned to each input so that, when more than one input is
simultaneously active, the input with the highest priority is encoded.
ROM (Read Only Memory): ROM is nothing but the combination of decoder and
encoder. It is a semi-conductor memory and which is a permanent memory, ROM can
also be defined as a simple code conversion unit. It has N no.of inputs and M no.of
out puts
2NXM
ROM can be viewed as a combinational circuit with AND gates connected as a decoder
and number of OR gates equal to the number of outputs. Internally a ROM contains a
decoder and a storage array.
 The memory which is constructed by using only gates is ROM.
Example: 5X32 ROM
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Programmable logic devices (PLDs):The function to be performed by a programmable

logic device is undefined at the time of its manufacture. These devices are programmed
by the user to perform a range of functions depending upon the logic capacity and other
features offered by the device...
Chapter-6 SEQUENTIAL LOGIC CIRCUITS
 Sequential Digital circuits: the output at any instant of time not only depends on
the present inputs but also on the previous inputs or outputs. For the design of
these circuits in addition to gates we need one more element flip-flop.
Examples for sequential digital circuits are Registers, shift register, counters etc.
 Two cross coupled inverters will form a basic latch which can store one bit of
information
Flip-flop: Flip-flop is also called bistable multivibrator or binary. It can store one bit
of information
 In a flip-flop one output is always complement of the other out
 Flip-flop has two stable states.
Types of FFs: a) S-R FF b) J-K FF c) Master-Slave J-K FF d) T-FF e) D-FF
Clocked S-R Flip-flop: it is called set-reset Flip-Flop.
Truth table:
S R Qt Qt+1
0 0 0 0
1 1
_______
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CLK PR’ CLR’ Qt Resulting state
0 1 0 0 0 1 0 0 clear
1 0 0 1 1 1 preset or clear
_______ 0 0 0 ? intermediate
1 0 0 1 1 1 1 Qt+1 Normal FF next state is
1 1 determined by S&R
_______
1 1 0 1
1 1
 N1 and N2 from a basic latch.N3 and N4 are called steering gates or Control
gates, because they are use to control the outputs
 S and R inputs are called synchronous inputs Preset (Pr) and clear (Cr) inputs are
called direct inputs or asynchronous inputs.
 The output of the flip-flop changes only during the pulse. In between clock pulses
the output of the flip-flop does not change.
 `During normal operation of the flip-flop, preset and clear inputs must be always
high.
J-K Flip-Flop: The disadvantages of S-R flip-flop is S=1, R=1 output cannot be
determined. This can be eliminated in J-K flip-flop.
 S-R flip-flop can be converted to j-k flip-flop by using the two equation S=JQ’
and R=KQ
Truth Table:
J K Qt Qt+1
0 0 0 0
1 1
________
0 1 0 0
1 0
________
1 0 0 1
1 1
________
1 1 0 1
1 0
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 Race around problem is present in the j-k flip-flop, when both J=K=1
 Toggling the output more than once during the clock pulse is called Race around
problem
 The race around problem in J-K flip-flop can be eliminated by using edge
triggered flip-flop or master slave J-K flip-flop or by using the clock signal whose
pulse width is less than or equal to the propagation delay of fip-flop
 Master slave flip-flop is a cascading of two J-K flip-flop positive or direct clock
pulses are applied to master and these are inverted and applied to the slave flip-
flop.
D flip-flop: it is also called a delay flip-flop.by connecting an inverter in between J
and K input terminals (or) connecting an inverter in between S and R input terminals
D flip-flop is obtained. K always receives the compliment of J.
D Qt+1
0 0
1 1
 D flip-flop is a binary used to provide delay. The bit on the D line is transferred to
the output at the next clock pulse.
Transparent D-FF +ve edge triggered D-FF -ve edge tried FF +ve edge trid JK-FF
T flip-flop: JK flip-flop can be converted into T flip-flop by connecting J and K input

terminals to a common point. If T=1, then Qn+1=Qn. this unit changes state of the output
with each clock pulse and hence it acts as a toggle switch.
Truth table
T Qt Qt+1
0 0 0
0 1 0
1 0 1
1 1 0
 If XkHz clock signal is applied to a T flip-flop when T=1, then the output Q
signal frequency is given by X/2 thus it acts as a frequency divider.
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EXITATION TABLES
S-R
PS NS Inputs
PS NS Inputs Qt Qt+1 J K
Qt Qt+1 S R 0 0 0 X
1 0 0 X 0 1 1 X
0 1 1 0 1 0 X 1
1 0 0 1 1 1 X 0
1 1 X 0
T-FF D-FF
PS NS Inputs
Qt Qt+1 T PS NS Inputs
0 0 0 Qt Qt+1 D
0 1 1 0 0 0
1 0 1 0 1 1
1 1 0 1 0 0
1 1 1
 Setup Time (ts): time interval immediately preceding the active transition of clock
signal during which the control input must be maintained at the proper level.
 Hold Time (tH): the time interval I immediately following the active transition of
the clock signal during which the synchronous control input must be maintained
at the proper level.
Propagation Delay:
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• Tplh -- time between a change in an input and a low to high change on the output.
Measured from 50% point on input signal to 50% point on the output signal. The ‘lh’ part
(low to high) refers to OUTPUT change, NOT input change
• Tphl -- time between a change in an input and a high to low change on the output.
Measured from 50% point on input signal to 50% point on the output signal. The ‘hl’ part
(high to low) refers to
OUTPUT change, NOT input change
Chapter-7 Counters and Registers
Counters and registers belong to the category of MSI sequential logic circuits. counters
are mainly used in counting applications, where they either measure the time interval
between two unknown time instants or measure the frequency of a given signal, registers
are primarily used for the temporary storage of data present at the output of a digital
circuit before they are fed to another digital circuit.
Ripple (Asynchronous) Counter:
A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop
drives the clock input of the following flip-flop.
In a ripple counter, also called an asynchronous counter or a serial counter, the clock
input is applied only to the first flip-flop, also called the input flip-flop, in the cascaded
arrangement. The clock input to any subsequent flip-flop comes from the output of its
immediately preceding flip-flop.
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Propagation Delay in Ripple Counters: the effective propagation delay in a ripple counter
is equal to the sum of propagation delays due to different flip-flops.
Increased propagation delay puts a limit on the maximum frequency used as clock input
to the counter. The clock signal time period must be equal to or greater than the total
propagation delay.
The maximum clock frequency corresponds to a time period that equals the total
propagation delay.
If tpd is the propagation delay in each flip-flop, then, in a counter with N flip-flops
having a modulus of less than or equal to 2N, the maximum usable clock frequency is
given by
fmax = 1/(N X tpd).
Two propagation delay times are specified in the case of flip-flops, at the output
1) LOW-to-HIGH transition (tpLH)
2) HIGH-to-LOW transition (tpHL).
In such a case, the larger of the two should be considered for computing the maximum
clock frequency. A 3-bit counter divide the clock input frequency by 8
Count Capability of Ripple Counters:
Maximum count capability: N = 2n – 1
Where N is the maximum count number and n is the number of flip-flops.
Ex: if n = 12, the maximum count capability is, N = 212 – 1 = 4095
The number of flip-flops required to have a certain count capability: n = 3.32 log10 N
Ex: count capability is 5000
n = 3.32 log10 5000 = 12.28=13 FFs required.
Counting Speed of Ripple Counters
For reliable operation of the counter, the upper limit of the clock pulses of the counter
can be calculated from f =1/nt (109) where n is the number of flip-flops and t is the
propagation delay of each flip-flop.
Synchronous Counter
In a synchronous counter, also known as a parallel counter, all the flip-flops in the
counter change state at the same time in synchronism with the input clock signal. The
clock signal in this case is simultaneously applied to the clock inputs of all the flip-flops.
The delay involved in this case is equal to the propagation delay of one flip-flop only,
irrespective of the number of flip-flops used to construct the counter. In other words, the
delay is independent of the size of the counter.
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1. Flip-flop A toggles on negative clock edge.

2. Flip-flop B toggles when QA is 1
3. Flip-flop C toggles when QA and QB are 1
4. Flip-flop D toggles when QA, QB are QC are 1
This means that a flip-flop will toggle only if all flip-flops preceding it are at binary 1
level.
Presetting (Up-Counting Mode)
The counter can be preset to any 4-bit binary number, which is first fed into the parallel
inputs and the load input is held low momentarily, which shifts the number into the
counter. It is not necessary to reset the counter before presetting it. Let us suppose that
the number shifted into the counter 1 0 1 0 and the counter is made to count up. The
counter output will be stepped up after each input pulse and after the 6th pulse the output
will be 0 0 0 0. The counting up begins from the number preset in the counter and the 6th
pulse resets the counter and then it starts counting up from this point.
Presetting (Down-Counting Mode)
The counter is set up in the down-counting mode and, as before, suppose the number fed
into the counter is 1 0 1 0 and the counter is made to count down. The 10th, input pulse
will reset the counter to 0 0 0 0 and the 11th, pulse will show a count of 1 1 1 1 and then
it will begin to count down from this number.
Presetting (Using Counter Output)
The counter can also be preset by connecting its feedback The desired number, say 1 0 1
0 is fed into the A B C D inputs and the counter input is connected to a 1 Hz clock signal
when the counter reaches the maximum, count, 1 1 1 1, the NAND gate output will go
low and the binary number 1 0 1 0 will be shifted into the counter. The counter will now
begin to count up from this preset number and when the count again reaches 1 1 1 1, the
counter will return to the preset number 1 0 1 0 and will again begin to count up as
before. You will notice that as soon as the counter reaches the maximum count 1 1 1 1 (or
decimal 15), it is immediately preset to 1 0 1 0 (or decimal 10). Since state 15 is being
used to preset the counter, it is no longer a stable state. The stable states in this counting
operation will be 10, 11, 12, 13 and 14, and the modulus (number of discrete states) of
the counter will be 5.
The counter modulus in the up-counting mode for any preset number n is given by
Modulus = 16 – n – 1
In this case Modulus = 16 – 10 – 1 = 5
In the down-counting mode, the counter will count down from the preset number, 1010
(or decimal 10). As before the counter will count down as follows; 9, 8, 7, 6, 5, 4, 3, 2,
1,0.
In this case the counter modulus will be as follows:
Modulus = n + 1
In this case Modulus = 10 + 1 = 11
When the counter is preset in this manner, it should never be preset to number 15 as this
is not a stable state, and it is likely to get latched up in this state
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Modulus of a Counter
The modulus (MOD number) of a counter is the number of different logic states it goes
through before it comes back to the initial state to repeat the count sequence. An n-bit
counter that counts through all its natural states and does not skip any of the states has a
modulus of 2n.
We can see that such counters have a modulus that is an integral power of 2, that is, 2, 4,
8, 16 and so on. These can be modified with the help of additional combinational logic to
get a modulus of less than 2n.
To determine the number of flip-flops required to build a counter having a given
modulus, identify the smallest integer m that is either equal to or greater than the desired
modulus and is also equal to an integral power of 2. For instance, if the desired modulus
is 10, which is the case in a decade counter, the smallest integer greater than or equal to
10 and which is also an integral power of 2 is
16. The number of flip-flops in this case would be 4, as 16 = 24. On the same lines, the
number of flip-flops required to construct counters with MOD numbers of 3, 6, 14, 28
and 63 would be 2, 3, 4, 5 and 6 respectively. In general, the arrangement of a minimum
number of N flip-flops can be used to construct any counter with a modulus given by the
equation
Many methods have been developed for designing such counters.

(1) Counter Reset Method (Asynchronous)
In this method the counter is reset after the desired count has been reached and the count
cycle starts all over again from the reset state.
(2) Logic Gating Method (Synchronous)
This method provides the exact count sequence required without any need to reset the
counter at some stage.
(3) Counter Coupling Method
This method is used to implement counters of the required modulus. For instance we can
interconnect mod-2 and mod-3 counters to implement a modulus 3 × 2 or mod-6 counter.
 Registers and shift registers:

 A register is a group of flip-flops used to store binary information. a n n-bit
register can store n-bit information.
 A register which is able to shift the information either from left to right or from
left to right is called a shift register.
 Shift register can perform four different operations.
1) Serial input-parallel output
2) Serial input-serial output
3) Parallel input-parallel output
4) Parallel input-serial output
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 Universal shift register: a register which is able to shift the information from left
to right or from right to left and when can perform all four operations is called
universal shift register
 Applications of shift registers:
Serial to parallel conversion (it is also called spatial to temporal code
conversion)
Parallel to serial conversion (it is also called temporal to spatial code
conversion)
Sequence generator
Multiplication and division
Ring counter and twisted ring counter
Digital delay line (serial input and serial out operations)
 Left shift operation is nothing but multi[lied by 2
Shift left by n- position is equivalent to multiplication by 2n.

 If least significant bit =0,then right shift operation by one position is same as
division by 2
If L.S.B=1 then right shift operation gives integer division by 2
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 Ring counter: shift register can be used as ring counter when Q0 output terminal
is connected to serial input terminal
 An n-bit ring counter can have “n” different output states. it can count n-clock
pulses.
 Twisted ring Counter: it is also called Johnson’s Ring counter. it is formed when
Q0 output terminal is connected to the serial input terminal of the shift register
 An n-bit twisted ring counter can have maximum of 2n different output state.
 Counters:
 The counter is driven by a clock signal and can be used to count the number of
clock cycles. Counter is nothing but a frequency divider circuit.
 Two types of counters are available:1synchronous 2.asynchronous
 Synchronous counters are also called parallel counters .in these types of counters
the clock pulses are simultaneously applied to all the filp-flops.
 Asynchronous counters are also called Ripple or serial counters. In this type of
counters the output of one flip-flop is connected to the clock input of n next flip-
flop and so on.
 A counter having n-flip-flops a can have 2n output states i.e. it can count 2nclcok
pulses
 The largest binary number that can be represented by an n-bit counter has a
decimal equivalent of 2n-1.
 A counter can be made to count either in the up mode or in the down mode.
 Synchronous counters are faster than asynchronous counters
 The modules of a counter are the total number of states through which the counter
can progress. For example mod-8 counter is having 8 different states (000 to111).
 The output signal frequency of Mod-n counter is (1/n)th of the input clock
frequency. Hence that counter is also called ÷n counter.
 The number of flip-flops(n) required to construct Mod N counter can be obtained
from the following formula
2n-1<N≤2n
 A decade counter is also called MOD-10 or ÷10 counters requires 4 flip-flops
 Any binary counter can be a modules counter where as the modules counter need
not be a binary counter.
 Six flip-flops are required to construct mod-60 counter
 Two types of synchronous counters are available.
1. Series carry
2. Parallel
Ring Counter
The ring counter is the simplest form of shift register counter. In such a counter the
flipflops are coupled as in a shift register and the last flip-flop is coupled back to the first,
which gives the array of flip-flops the shape of a ring.
 ‘n’ bit Ring counter counts n states.
Johnson Counter
In modified ring counter is known as a switch tail ring counter or Johnson counter. The
modified ring counter can be implemented with only half the number of flip-flops.
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 ‘n’ bit Johnson Ring counter counts 2n states.
Ring Counter Applications
(1) Frequency dividers
(2) Counters
(3) Code generators and
(4) Period and sequence generators
a shift register connected as a ring counter can be used as a frequency divider.
Chapter-8 Semiconductors memories

 The digital computer memory can be classified into two types: primary memory
or main memory and secondary memory or auxiliary memory
 Primary memory or main memory: the memory, which is directly accessible to
the CPU, is called main memory EX:ROM,RAM
 Secondary memory or auxiliary memory the memory, which is not directly
accessible to the CPU ,is called secondary memory ex: hard disk, floppy disk,
magnetic tape etc
 Primary memories are semiconductor memories: they are available in the form of
integrated circuits with different memory capacities.
 The capacity of the memory IC is represented by 2nxm.where 2n represents
number of memory locations available and ‘m’ represents number of bits stored in
each memory location
 The number of address bits required to identify 2n memory locations are “n”.
 Assigning address for different memory locations of a memory IC is called
memory mapping.
 To increase the bit capacity or length of each memory location, the memory ICs
are connected in parallel and the corresponding memory location of each IC must
be selected simultaneously.
 To increase the number of memory locations the memory ICS are connected such
that at any time only one memory IC must be selected.
 The number of memory ICs of capacity 1kx4 required to construct a memory of
capacity 8kx8 are 16.
 memory device parameters or characteristics:
 Access time: the access time of a memory is defined as the time required to access
a memory location for reading or writing
 The access time of a magnitude drum is defined as the sum of seek time and
transfer time.
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 Access rate: it is defined as the reciprocal; of access time. it is measured in words
per seconds
 Access time depends on the physical characteristics of the storage medium. And
also on the type of access mechanism used.
 Access modules: an important property of memory device is the order or sequence
in which information can be accessed.
 Random access: it the access time is independent of position of the memory
location, then it is called random-access mode, i.e the access time of every
memory location is same.
 Sequential access: a memory in which the location can be accessed in a sequence
only is referred to as a sequential memory. Ex: Magnetic tape, magnetic bubble.
 Some memory devices such as magnetic disks or drums contain a large number of
independent rotating tracks. If each track has its own read-write head, the tracks
may be access randomly, although access within each track is serial. in such cases
the access mode is same time s called semi-random or direct access
 Alterability: the method used to write information into a memory may not be
irreversible, in that once information has been written, it can not be alterable
while the memory is in use i.e on-line
 Memory whose contents can not be altered on-line are called ROM’s
 ROMs whose contents cam be changed are called PROMs.
 Memories in which reading or writing can be done on-line are called R/W
memories.
 Volatile memory: in this type if memory, the stored information is dependent on
power supply i.e. the stored information will remains as it is as long as power is
applied
eg: RAM
 Non-Volatile memory: in this type of memory, the stored information is
independent of power supply, i.e the stored information will present as it is even if
the power fails.
Eg: ROM, PROM, EPROM, EEPROM etc.
 PROM: Programmable read Only memory
 EPROM: erasable Programmable Read only memory
 EPROM :electrically erasable programmable red only memory
 EAPROM: electrically alterable programmable read only memory.
 Static RAM (SRAM): in this type of memory binary information is stored in
terms of voltage. SRAM stores ones and zeros using conventional Flip-flops.
 Dynamic RAM (DRAM): in this type of memory, binary information is stored in
terms of charge on the capacitor. The memory cells of DRAMS are basically
charge storage capacitors with driver transistors. the presence or absence of
charge in a capacitor is interpreted as logical 1 or 0
 Because of the leakage property of the capacitor, DRAMS require periodic charge
refreshing to maintain data storage.
 The package density is more in the case of DRAMs. but additional hardware is
required for memory refresh operation.
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 SRAMS consume more poor when compared to RAMs, SRAMs a faster than
DRAMs.
 Destructive Read Out memory: the memory is known as destructive read out
memory if the reading method destroys its contents. For such memories each read
operation must be followed by write operation to restore the contents .Ex
magnetic core.
 Non-extractive read out: it is called NDRO if the reading operation does not
change its contents. Ex: magnetic tapes, disks, RAM, ROMs etc.
 Semiconductor technologies used for fabrication of memories are
 a)Bipolar b)unipolar
 CCD (Charge coupled device) is a volatile memory and sequential access-type.
 Low cost and high access rate are describe memory characteristics
 By changing the hardware logic used for the chip selection of memory IC, it is
possible to change the memory mapping.
Chapter-9 A/D&D/A CONVERTERS
 digital to analog conversions needed in digital data processing requires insulation

of digital information to an equivalent analog information
 Digital to analog converters, any be used to translate the output of a digital system
into an analog from for the purpose of driving a pen recorder or for a cathode ray
oscilloscope.
 The D/A converter is commonly referred to as a decoding device, since it is used
to decode the digital signal into proportional voltage or current signals for an
entry into n analog system
 D/A converter convert digital information into corresponding analog signals.
 There are two types of DAC are available
a) Binary weighted resistors type of DAC
b) R-2R ladder type of DAC
 the R-2R ladder type of DAC is superior of DAC
 binary weighted resistors type of DAC has many drawbacks
 when the number of input bits is large, the resistors used for LSB has to be very
large value
 each resistor required in the network is of different value, as, such the resistors
used re to be chosen from wide range of values
 if each higher bits resistors is not exactly half of the previous bit resistors, the step
size will change
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 the advantage of R-2R ladder type of DAC over Binary weighted resistors type of
DAC
a) Better linearity
b) It requires only two different types of resistors with values R and 2R
 A linearity: a d/a converter is said to be ideally or perfectly linear, if it gives equal
increments in the analog output voltage for equal increments in the numerical
value of the digital value.
 D/A resolution: it is defined as the smallest change in the analog output voltage
corresponding to a change of one bit in the digital input. the percentages
resolution of an n-bit DAC is given by 1/2n-1*100
 the resolution of an n-bit DAc with a range of output voltage from 0 to Volts is
given by V/2n-1 V
 Settling time of DAC: it is defined as the time required for the analog output
voltage to reach and stay within a specified limit, after application of a digital
input.
 Monotonicity: a DAC is said to be monotonic if its output voltage increases
regularly as its binary digital input signals is increased from one value to the next
value. output wave form should be perfectly staircase with no downwards steps,
as input is increased for a proper monotonic DAC
 The accuracy of D/A converter is a measure of the difference between the actual
analog output voltage and what the output should be in the ideal case.
 An analog to digital converter ADC converts analog voltages onto the
corresponding digital code.
 An ADC usually considered as an encoder
 The conversion time ADC is the time required for conversion of one analog
sample to corresponding digital code
 Different types of ADC’s are available:
 Simultaneous ADC or Parallel comparator of flash type of ADC
 Counter type of ADC or Pulse width type of ADC
 Integrator type of ADC or single slop of ADC
 Dual slope integrator ADC
 Succeive approximation type ADC etc
 Flash type of ADC is the fastest type of ADC
 An n-bit flash type of ADC requires 2n-1 comparators
 Counter type of ADC uses linear search and succive approximation type of ADC
usesu binary search.
 Ring counter is used in successive approximation type of ADC
 ADC Resolution: it is defined as the change in the input voltage require for a one
–bit change in the output.
 An ADC having an analog range of –V/2 to +V/2 and n-bit digital output has a
resolution of V/ (2n-1) volts.
 Dual slope AC is more accurate
 Flash type of ADC require no counters
 Counter type of ADC and successive approximation type of ADC used DAC
Bharadwaj
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Chapter-1 Number Systems

Types of number systems:

Conversion among Different Number Systems:

Floating Point Numbers

Signed number representation:

3.2’s complement method, range

EX:Convert Gray code word 1111011 into binary.

Chapter-2 LOGIC GATES

Logic ‘0’ Logic ‘1’

Logic ‘1’ Logic ‘0’

Gate Equivalent in NAND gates

Realization of X-OR gates using NAND and NOR gate

 Realization of basic gates using NAND and NOR gates:

Chapter-3 Boolean algebra

Logical Additions based on OR function

Complement based on NOT function

C) Combining a variable with itself or its complement

BOOLEAN FUNCTION MINIMIZATION TECHNIQUES

 Maxterm is the complement of its corresponding Minterm and vise versa.

Sum-of-Products (SOP) is the simplified form of the Sum-of-Minterms. An SOP

Product-of-Sums (POS) is the simplified form of Product-of-Maxterms. A POS

F=(X+Y) (X’+Y’) =ПM (0, 3)

 A Boolean function may be expressed algebraically from a given truth table by

 If one canonical form is given it is possible to express other canonical form

2, 3, 4 & 5 Variable K-maps:

Construct the K-map:

Number of No. Of Cells No. of No of literals

Chapter-4 LOGIC GATE FAMILIES

DTL TTL ECL CMOS PMOS

 2-input NAND gate with Totem-pole output configuration.

 Wired-AND operation is equivalent to AND –OR-INVERT

Symbol of ECL OR/NOR

ECL OR/NOR Gate

Wired –OR operation is equivalent to OR-AND-Inevrt

PMOS GATE circuits:

Three State Logic (TSL)

 In a logic circuit we have two output states LOW and HIGH.

(a)Logic Symbol of TSL Inverter (b) TTL TSL Inverter

Chapter-5 Combinational digital Circuits

 Digital circuits can be classified into two types:

Combinational circuit Design Procedure: It involves following steps:

Sum= ∑(1,2,4,7) Carry= ∑(3,5,6,7)

4-bit Look-ahead Carry Generator:

G3 = Σ (8, 9, 10, 11, 12, 13, 14, 15)

B3 = Σ (m11, m12), d (m0, m1, m2, m13, m14, m15)

Data bits Parity

Programmable logic devices (PLDs):The function to be performed by a programmable

Chapter-6 SEQUENTIAL LOGIC CIRCUITS

T flip-flop: JK flip-flop can be converted into T flip-flop by connecting J and K input

Chapter-7 Counters and Registers

1. Flip-flop A toggles on negative clock edge.

Many methods have been developed for designing such counters.

 Registers and shift registers:

Shift left by n- position is equivalent to multiplication by 2n.

If L.S.B=1 then right shift operation gives integer division by 2

Chapter-8 Semiconductors memories

Chapter-9 A/D&D/A CONVERTERS

 digital to analog conversions needed in digital data processing requires insulation

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