Documente Academic
Documente Profesional
Documente Cultură
K H A R T O U M , S U D A N
A Proposed Program
for
Prepared by:
TABLE OF CONTENTS
Rationale ..............
...........................................................................
....................... 1
Philosophy of the Program
ram ....................................................................
....................... 2
Program Learning Outcomes
omes ...............................................................
....................... 2
Objectives of the Program
am ...
...................................................................
...................... 4
Entry Requirements ............
..........................................................................
....................... 4
Career Opportunities: MSc
Sc in Computer Engineering
Networking Trackk ......
.......................................................................
...................... 4
VLSI Design Track
ck ...
....................................................................
...................... 4
Embedded System
em Tra
Track ..........................................................
...................... 5
Curricular Structure .............
...........................................................................
...................... 5
Proposed Curriculum: MSc
Sc in Computer Engineering
Networking Trackk ......
.......................................................................
...................... 6
VLSI Design Track
ck ...
....................................................................
...................... 6
Embedded System
em Tra
Track ..........................................................
...................... 7
Distribution of Courses ........
.........................................................................
...................... 7
Description of Courses ........
.........................................................................
...................... 8
Course Syllabi .....................
...........................................................................
...................... 12
Proposed Laboratories
Digital Signal Processi
ocessing ...........................................................
...................... 32
VHDL Programming
ing ...................................................................
...................... 33
VLSI Design .............
..........................................................................
..................... 34
Networking ...............
..........................................................................
..................... 35
Embedded System ...
....................................................................
..................... 36
Robotics ...................
..........................................................................
.................... 37
Proposed Library Holdings
ngs ..
...................................................................
.................... 38
Appendix
References ...............
...........................................................................
.................... 40
I. RATIONALE
cal and international are finding their ways onto the global
Businesses both local
web and are in need of professionals capable of providing their needs. The
globalization and internalization trend in all aspects had made individuals and
companies ever more reliant to network communications. In response, firms in the
telecommunication industries spend billions of dollars in research and development to
address the growing demand of network telecommunications. Developing countries, to
be able to keep pace with the rest of the w world
orld must not only invest in these
technologies but also must provide human resources capable in the design,
development, operation and maintenance of these technologies.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
1. Develop, construct and analyze complex network system systemss , processes and
products using scientific and engineering principles;
2. Demonstrate the ability to innovate designs of network systems including new
processes and products;
3. Understand the capabilities of experimental methods for problem solving;
4. Integrate knowledge in mathematics, science, information technology, design,
management principles and engineering principles to solve a variety of
problems in networking;
5. Have a thorough understanding and knowledge of management practices and
ethical issues on the field of networking and their limitations;
6. Design sustainable, efficient and cost effective network systems, processes
and products;
7. Effectively use available resources in the conduct of project development and
research;
8. Work effectively as an individual, member of a group and can take on
leadership roles;
9. Employ a systematic process in gathering, analyzing, interpreting, and
communicating knowledge; and
10. Generate ideas that contribute to the advancement of network engineering.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
The objectives of the program are to provide opportunities for suitably qualified
qualifie
persons to acquire skills and expertise necessary to undertake research and
development nt in the field of network engineering. The courses in the MSc Computer
Engineering with specialization in Networking (MSc CpE-N) enable students to acquire
expertise, and
nd enhance their communication skills to elucidate complex technical
problems, and solutions in network engineering. This program prepares the graduate
student to successfully handle problems requiring in in-depth
depth knowledge principles and
processes in the fieldld of networking encompassing both wire and wireless
communication systems.
V. ENTRY REQUIREMENT
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
The first term which is composed of 9 credit hours (3 core courses) which will
give the students
nts the preliminary direction of the masters program.
The second and third term allows the student to choose any 18 credit hours from
the list of professional courses. These courses intend to develop the graduate students
expertise in the different tracks
acks of networking, VLSI Design and Embedded System.
The fourth term (6 credit hours) will be devoted to project development and
documentation or research writing. This capstone activity will showcase the totality of
learning of the graduate student. T The
he student at this point is expected to show mastery
in the area where he/she is expected to conduct research (Thesis) or project
development.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Core Courses:
These courses are re required
quired for the students enrolled in MSc Computer
Engineering program.
TITLE CREDIT
HOURS
MCpE01 Computer System and Architecture 3
MCpE02 Project Management Principles 3
MCpE03 Digital Machine Design using VHDL 3
NETWORKING TRACK
TITLE CREDIT
Specialization
Required Courses: HOURS
MCpE-04 Applied Digital Signal Processing 3
MCpE-N01 Design and Analysis of Data Networks 3
MCpE-N02 Advanced Wireless Networks 3
MCpE-N03 Network Mana
Management 3
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Master’s Project:
The graduate student
udent is required to go into a supervised project study:
TITLE CREDIT
UNITS
MCpE-13 Master’s Project 6
Core (Common to
the three (3) tracks,
Required 27.27%
36.36%
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
X. DESCRIPTION OF COURSES
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Fundamentals of Computer Design
2. Pipelining Basic and Intermediate Concepts
3. Memory Hierarchy
4. Inside the Processor
Instruction Set Principles
Instruction Level Parallelism
Exploiting
ing Software Level Parallelism with Software Approaches
5. Multiprocessors
6. Storage
7. Networks
Course Text/Reference:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
Course Text/Reference:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. CIRCUIT DESIGN
Introduction: About VHDL; Design Flow; EDA Tools; Translation of VHDL Code
into a Circuit; Design Examples
Code Structure: Fundamental VHDL Units; LIBRARY Declarations; ENTITY;
ARCHITECTURE; Introductory Examples
Data Types: Pre Pre-Defined Data Types; User-Defined Defined Data Types;
Subtypes;Arrays; Port Array; Records; Signed and Unsigned Data Types; Data
Conversion;
Operators
ors and Attributes:
Attributes Operators; Attributes; User--Defined Attributes;
Operator Overloading; GENERIC
Concurrent Code: Concurrent versus Sequential; Using Operators; WHEN;
GENERATE; BLOCK;
Sequential Code: PROCESS; Signals and Variables; IF; WAIT; CASE; LOOP;
CASE versus IF; CASE versus WHEN; Bad Clocking; Using Sequential Code to
Design Combinational Circuits.
Signals and Variables: CONSTANT, SIGNAL, VARIABLE, SIGNAL versus
VARIABLE, Number of Registers,
State Machines 159
8.1 Introduction:: Design Style #1; De Design
sign Style #2 (Stored Output); Encoding
Style: From Binary to OneHot;
Additional Circuit Designs
Designs:: 9.1 Barrel Shifter, Signed and Unsigned
Comparators, Carry Ripple and Carry Look Ahead Adders, Fixed Fixed-Point Division,
Vending-Machine
Machine Controller, Serial Data Receiver, Parallel-to to-Serial Converter,
Playing with a Seven
Seven-Segment
Segment Display, Signal Generators, Memory Design.
2. SYSTEM DESIGN
Packages and Components; Functions and Procedures; Additional System
Designs; Serial-Parallel
Parallel Multiplier; Parallel Multiplier; Mu
Multiply--Accumulate Circuits
Digital Filters; Neural Networks
Course Text/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Concepts in Networking;
2. Example Networks and Network Components;
3. Introduction to Network Analys
Analysis, Architecture, and Design;
4. Network Requirements Analysis: Concepts;
5. Network Requirements Analysis: Process;
6. Flow Analysis;
7. Network Architecture;
8. Addressing and Routing Architecture;
9. Network Management Architecture;
10. Performance Architecture;
11. Security and Privacy Architecture;
12. Selecting Technology for the Network Design;
13. Interconnecting Technologies with the Network Design
Course Text/Reference:
McCabe, J.D. (2003). Network Analysis, Architecture, and Design, (2nd Edition).
Morgan Kaufmann Publishers.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. DSP implementation:
precedence graph, DSP structure verification and simulation; Goertzel’s
algorithm, FFT; fixed-point
fixed and float-point
point representation and operations,
overflow.
2. Finite Wordlength Effects:
quantization
tion of fixed
fixed-point and floating-point point numbers, analysis of coefficient
quantization effects, A/D conversion and noise analysis, analysis of round round-off
errors, dynamic range scaling, SNR in low low-order
order IIR filters, low-sensitivity
low digital
filters, limit cycles,
s, limit
limit-cycle free structures.
3. Multirate DSP:
sampler and down
up-sampler down-sampler,
sampler, filters in sampling rate alternation systems; multi-
multi
stage design of decimator and interpolator, polyphase decomposition; arbitrary
sampling rate converter, Lagrange interpolation, digital filter banks, uniform DFT
filter banks, Nyquist filters, quadrature
quadrature-mirror
mirror filter banks, perfect reconstruction
two-channel
channel FIR filter banks, multi
multi-level filter banks.
4. DSP Applications:
spectral analysis of sinusoidal signals, spectral analysis o off non-stationary
non signals,
short-time
time Fourier transform, speech signal analysis, and others
Course Text/Reference:
Mitra, S.K. (2006). Digital Signal Proces sing: A Computer Based Approach (3rd Edition).
Processing:
McGraw Hill.
Dutuit, T. & Marques, F. (2009). Applied
ed Signal Processing: A MATLAB
MATLAB-Based Proof of
Concept (Signals and Communication Technology)
Deziel, P. (2000). Applied Introduction to Digital Signal Processing
Processing.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Fundamentals;
2. Opportunistic Communications
Communications;
3. Relaying and Mesh Networks
Networks;
4. Topology Control;
5. Adaptive Medium Access Control
Control;
6. Teletraffic Modelling
ling and Analysis
Analysis;
7. Adaptive Network Layer
Layer;
8. Effective Capacity;
9. Adaptive TCP Layer;;
10. Network Optimization Theory
Theory;
11. Mobility Management
ement;
12. Cognitive Radio Resource Mana
Management;
13. Ad Hoc Networks;
14. Sensor Networks;
15. Security;
16. Active Networks;
17. Network Deployment;
Deployment
18. Network Management;
Management
19. Network Information Theory
Theory;
20. Quality of Service Management
Course Text/Reference:
Glisic, S. & Lorenzo, B. (2009).
09). Advanced Wireless Networks:
etworks: Cognitive, Cooperative
and Opportunistic 4G. Wiley.
Wysocki, T., et al. (2004). Advanced Wired and Wireless Networks (Multimedia
(Mult
Systems and Applications. Springer.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Data Communication and Network Management Overview;
2. Data and Telecommunications Networks;
3. Exploring Existing Networks;
4. Building a Simple Network: Physical View;
5. Simple Network: Management View and Simulator;
6. Designing Large IP Networks;
7. Network Routing Protocols;
8. Service Level Management;
9. Management Information Bases (MIBs);
10. SNMP;
11. Remote Monitoring (RMON);
12. Network Performance Monitoring;
13. Securing the Network
Course Text/Reference:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Introduction:
Motivating examples; Basic concepts: confidentiality, integrity, availability,
security policies, security mechanisms, assurance;
2. Basic Cryptography
Historical background; Transposition/Substitution, Caesar Cipher; Introduction to
Symmetric crypto primitives, Asymmetric crypto primitives, and Hash functions
3. Secret Key Cryptography
Applications; Data Encryption Standard (DES); Encrypting large messages (ECB,
CBC, OFB, CFB, CTR); Multiple Encryption DES (EDE)
4. Message Digests
Applications; Strong and weak collision resistance; The Birthday Paradox; MD5,
SHA-1
5. Public Key Cryptography
Applications; Theory: Euclidean algorithm, Euler Theorem, Fermat Theorem,
Totent functions, multiplicative and additive inverse; RSA, Selection of public and
private keys.
6. Advanced Encryption System
7. Electronic Mail Security;
8. IP Security;
9. Web Security
10. Network Management Security
11. System Security: Intruders and Viruses, Firewalls
Course Text/Reference:
Stallings, W. (2010). Network Security Essentials: Applications and Standards (4th
Edition).
Bhaiji, H.Y. (2008). Network Security Technologies a
and
nd Solutions (CCIE Professional
Development Series)
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
Course Text/Reference:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Learning Process;
2. Correlation Matrix Memory;
3. The Perceptron;
4. Least Mean Square Algorithm;
5. Multilayer Perceptrons;
6. Radial Basis Function Networ
Networks;
7. Recurrent Networks Rooted in Statistics;
8. Hebbian;
9. Modular Networks;
10. Temporal Processing;
11. Neurodynamics;
12. VLSI Implementations of Neural;
13. Neural Networks for Non
Non-linear pattern recognition;
14. Learning of Linear Pattern by Neural Networks;
15. Implementation of Neural Network Models for Extracting Reliable Patterns from
Data;
16. Assessment of Uncertainty of Neural Network Models Using Bayesian Statistics;
17. Discovering Unknown Clusters in Data with Self
Self-organizing
organizing Maps.
Course Text/Reference:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Contents:
1. Digital Systems and VLSI
2. Transistor and Layout
3. Logic Gates
4. Combinational Logic Gates
5. Sequential Machines
6. Subsystem Design
7. Floorplanning
8. Architectural Design
9. Chip Design
10. CAD System and Algorithm
Course Text/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Text/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Contents:
1. Introduction to ASICs: Types of ASICs, Design flow, Case study, study Economics of
ASICs, ASIC cell library
2. CMOS logic cells: Combinational logic cells, Sequential Logic cells, Datapath
Logic cells, I/O cells, Cell compil
compilers
3. ASIC Library Design: Transistor as resistors, Transistor as parasitic capacitance,
Logic Effort, library
brary cell design, library architecture
4. Gate Design: Gate array cell design, standard cell design, datapath cell design
5. Programmable ASICs: Antifuse, Static RAM, EPROM, EEPROM technology,
Practical issues
6. Programmable ASIC I/O cells: DC output, AC output, DC input, AC input, Clock
input, Power input, Xilinx I/O Block
7. Programmable ASIC Interconnect: Actel ACT routing resources, emlore’s
constant,
8. Delay: RC delay in antifuse connections, antifuse parasitic capacitance
9. ASIC Cinstruction: Physical design, CAD ttools,ools, estimating ASIC size, Power
dissipation
Course Text/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Principles of standard digital I/O cell design; buffer sizing, load capacity; Tri-state
Tri
output and enabling;
2. Bidorectional I/O circuits, IO Timing Characteristics, Noise immunity
improvement, Schmitt trigger input circuits. Improvement of load ability and
switching speed;
3. Design reliability; Latch Up; Parasit
Parasitic
ic bipolar transistor models; SCR; Latch-Up
Latch
prevention, lay out design rules; Protection against electrostatic, discharge and
overloading; High voltage tolerance output buffers, Secondary protection.
4. Two-supplied
supplied voltage I/O circuits; core voltage; I/O vol
voltage;
tage; Level translators;
Digital level shifters; High performance level shifter; supply voltages sequencing
issues.
Course Text/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Code: MCpE-V04
Course Credit: 3 Credit Hours
Course Title: Advanced Semiconductor Physics
Course Description: This advanced course in sem semiconductor
iconductor physics will cover classic
devices and the physical concepts of novel devices conceived since 1981. It will also
guide the students to be actively involved in semiconductor device research and
development.
Course Content:
1. Compound-Semiconductor
Semiconductor Field-Effect Transistors
• GaAs MESFETs
• Heterostructure Field
Field-Effect Transistors (HFETs)
• Gate Leakage Current
• Novel Compound-Semiconductor
Semiconductor FETs
2. Scaled MOSFETs
• CMOS/BiCMOS ; SOI and 3D Structures
• Power Rectifiers ; Power MOSFETs
• Insulated-Gate Bipolar Transistors
• MOS-GatedGated Thyristors
• Silicon Carbide Power Devices
3. Quantum-Effect
Effect and Hot
Hot-Electron Devices
• Resonant-Tunneling
Tunneling (RT) Structures
• Hot-Electron
Electron Structures
• Device Applications
4. Active Microwave Diodes
• Heribert Eisele and George I. Haddad
• Transit-Time
Time Diodes
• Resonant-Tunneling
Tunneling Diodes
• Transferred-Electron
Electron Devices
5. High-Speed
Speed Photonic Devices
• Laser Design and Basic Principles of Operation
• Quantum-Well Well and Strained
Strained-Layer Quantum-Well Lasers
• Advanced Laser Structures and Photonic Integrated Circuits (PICs)
• Photoreceivers and Optoelectronic Integrated Circuits (OEICs)
6. Solar Cells
• Solar Radiation and Ideal Energy
Energy-Conversion Efficiency
• Silicon Solar Cells: Crystalline, Multicrystalline, and Amorphous
• Compound-Semiconductor
onductor Cells
• Modules
Textbook/References:
Juin J. Liou : Advanced Semiconductor Device Physics and Modeling (Artech House
Materials Science Library). 1994
Michael E. Levinshtein, Sergey L. Rumyantsev, and Michael S. ShurShur: Properties of
Advanced Semiconductor ctor Materials : Gan, Aln, Inn. 2001
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
1. Basics Of Developing For Embedded Systems,
2. Embedded System Initialization, Introduction To Real
Real-Time
Time Operating Systems,
3. Tasks,
4. Semaphores,
5. Message Queues,
6. Kernel Objects,
7. RTOS Services,
8. Exceptions and Interrupts,
9. Timer and Timer Services,
10. Subsystem, Memory Management,
11. Modularizing An Application For Concurrency,
12. Synchronization Communication and Common Design Problems
Problems.
Course Text:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
CourseText/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Descriptions: This course will introduce Embedded programming using C++:
testing memory chips, writing and erasing Flash memory, verifying nonvolatile memory
contents with CRCs, Interfacing to onon-chip
chip and external peripherals, Device driver
design and implementation and Optimizing embedded software for size and speed
Course Outline:
1. Testing memory chips,
2. Writing and erasing Flash memory,
3. Verifying nonvolatile memory ccontents with CRCs,
4. Interfacing to on-chip
chip and external peripherals,
5. Device driver design and implementation and
6. Optimizing embedded software for size and speed
Course Text/References::
Michael
ael Barr. Programming Embedded Systems in C and C ++
Publisher: O' Media, Inc. 2008
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Outline:
Course Text/References:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
MSc CpE
CpE Syllabus
Course Content:
Course Text/References:
Cook, D. (2010). Robot Building for Beginners (Technology in Action)
Action).
Jones, J. and Roth,, D. (2003). Robot Programming : A Practical Guide to Behavior-
Based Robotics)
Jazar, R.N. (2010). Theory of Applied Robotics: Kinematics, Dynamics,
Dyna and Control
(2nd Edition)
Craig, J.J. (2004). Introduction to Robotics: Mechanics and Control (3rd Edition)
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Laboratory Equipment:
1. LabVIEW®/ MATLAB®
2. Texas Instruments® TMS320C6000 DSP Board
Laboratory Experiments
1. Discrete and Continuous
Continuous-Time Signals
2. Discrete-Time
Time Systems
3. Frequency Analysis
4. Sampling and Reconstruction
5. Digital Filter Design (part 1)
Digital Filter Design (part 2)
6. Discrete Fourier Transform and FFT (part 1)
Discrete Fourier Transform and FFT (part 2)
7. Discrete-Time
Time Random Processes (part 1)
Discrete-Time
Time Random Processes (part 2)
Power Spectrum Estimation
8. Number Representation and Quantization
9. Speech Processing sing (part 1)
Speech Processing (part 2)
10. Image Processing (part 1)
Image Processing (part 2)
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Laboratory Equipment:
1. Spartan®-3 3 FPGA Starter (Different Gate sizes)
2. Xilinx Virtex pro virtex II & virtex IVTainer kit,Altera,Virtex4 MB Development Kit
3. Xilinx® ISE™ 9.1i
3S1000 Board V1.1
4. XSA-3S1000
5. XStend Board V3.0
Laboratory Experiments:
1. Design Flow, EDA Tools, Translation of VHDL Code into a Circuit
2. Code Structure, Fundamental VHDL Units, LIBRARY Declarations, ENTITY,
ARCHITECTURE
Defined Da
3. Data Types: Pre-Defined Data Types, User-Defined
Defined Data Types, Subtypes,
Arrays, Port Array, Records, Signed and Unsigned Data Types, Data Conversion
4. Operators and Attributes: Operators, Attributes, User
User-Defined
Defined Attributes,
Operator Overloading
5. WHEN (Simple and Selected), GENERATE a and
nd BLOCK functions
6. PROCESS function, Signals and Variables, IF, WAIT, CASE, LOOP functions,
CASE versus IF, CASE versus WHEN, Design of Combinational Circuits
7. Signals and Variables: CONSTANT, SIGNAL, VARIABLE, SIGNAL versus,
VARIABLE, Number of Registers
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Laboratory Equipment:
1. Spartan®-3 3 FPGA Starter (Different Gate sizes)
2. Xilinx Virtex pro virtex II & virtex IVTainer kit,Altera,Virtex4 MB Development Kit
3. Xilinx® ISE™ 9.1i
3S1000 Board V1.1
4. XSA-3S1000
5. XStend Board V3.0
6. Universal VLSI Design Trainer Advanced (LTX (LTX-VL002)
7. VLSI PIGGY BACK CPU CARD
8. VLSI Advanced I/O Interface Module (Designed to connect the low cost
universal VLSI trainer if additional I/O interface is required) VLSI Experiment
Module
9. 7 Segment Displayy Module,SRAM Interface Module
10. Logic Gates Module,Modulo
Module,Modulo-n n Synchoronous/Asynvhoronous up/down counter
Module,Multiplexer / Demultiplexer Module
Module/ALU Module
11. 7 Segment display Module, Simulation of 8255 Module, 8279 Simulation
Module
12. Data Acquisition Module S STAND
TAND ALONE VLSI TRAINER KIT
Laboratory Experiments:
1. Oscillator, Noise Injector, Simulation and Analysis
2. D-Flipflops, D-Flipflops
Flipflops with RESET, AND Gate, D-flipflop
flipflop Phase/Frequency
Detector
3. Charge Pumps, Loop Filters, OpenOpen-Loop Test, Closed-Loop Loop Test
4. Models for Packaging, Models for Bond Pads, Models for Bond, Schematics
5. Complete Test Circuit Construction, VDD and VSS Pads, VCO Output Buffering
6. PLL Test, Layout of PLL, Floor
Floor-Planning
Planning of PLL, I/O Pin Assignment, Layout of
Pads, Layout of Output Buffers
Buffers.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Laboratory Equipment:
• Computer Networking
• Network Security
• Networking Design Courses
• Data Communication Environment
• Network Management
Laboratory Experiments:
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Parts needed:
1. ASCII to fixed-point
point conversions (unsigned 0.01)
2. Debugging, oscilloscope fundamentals, logic analyzer, dump profile
3. Alarm clock, LCD, key wakeup, and Output Compare interrupts
4. Stepper
per motor, output compare interrupts, finite state machine
5. 12-bit
bit DAC, SPI, Music player, audio amp
6. Temperature measurement, ADC, LCD
7. Introduction to PCB Layout, PCB Artist (paper design only)
8. Prototype Hardware and Layout of an Embedded System
9. Capacitance Meter, input capture, noise pdf, FIFO analysis
10. ZigBee, SCI, distributed systems, level conversions
11. Final Design and Evaluation of Embedded System
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
Laboratory Activities:
1. Mobile robots. Students are ask to bring a set of Legos with DC Motors and
asked to experiment in building small mobile robots of various shapes and
capabilities.
2. Microcontrollers and programming. The Handyboard, a Motorola 68HC11 based
microcontroller board developed by the MIT Med Media
ia Lab is used to teach students
sensor-based
based control of DC motors. The board, small size and battery powered,
is designed to easily interface to a variety of sensors and control up to four small
DC motors. On the software side, a C C-like language called Interactive
teractive C (IC) has
been developed to easily program the handy board through a personal computer.
3. Sensors. Students are taught the principles of operation of a variety of sensors
for position, velocity, acceleration, proximity and range, heat, and light.
4. Robot building contest. The class is divided into teams of 3 or 4 students. A robot
contest theme is adopted early by the class and each team designs, builds, and
programs its own robot for this competition. The class contest acts to motivate
student interest
est in learning the material presented in the lectures.
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP
FUTURE UNIVERSITY FACULTY OF ENGINEERING
XIV. APPENDIX
A. References:
Looft, F.J. & Orr, J. (2002). Computer and Communication Networks: MS Graduate
Program. 32nd ASEE/IEEE Frontiers of Education Conference. Available at
ieee.org.
Marti,
i, P, Velasco, M. and Fuertes, J. (2010). Design of an Embedded Control
Systems Laboratory Experiment. IEEE Transactions on Industrial Electronics,
Vol. 57, No. 10, October 2010.
Ust. Atika Malik Hussein Dr. Aristotle A. Ancheta Dr. Inoray Dindang Osop
HOD, Computer Engineering Faculty of Engineering Faculty of KE/KM
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UST. ATIKA MALIK ⦿ DR. ARISTOTLE A. ANCHETA ⦿ DR. INORAY DINDANG OSOP