Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition

By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

R R
D D
G G
M1 M2

S S

Figure 20.1 A basic current mirror.

Same point
VDD

R I REF = I D1
I O = I D2

IO VO
M1 M2 V O

Figure 20.2 The current mirror and how we think about it.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD VDD

90/2 300/2 15/2

30/2

60 µA 200 µA 10 µA
I REF = 20 µA
R
Channel-length modulation
is neglected here.
Figure 20.3 How current mirrors are ratioed.

µA IO
+5V

I REF I REF
200k
IO
V GS1 = 1.05 V
M1 M2 V O
V DS,sat = 250 mV

VO

Figure 20.4 The operation of an NMOS current mirror.

(b)

(a) (c)

Figure 20.5 (a) Large device with a single contact and (b) its equivalent circuit.
(c) Adding more contacts to reduce parasitic resistance.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Drain metal 1

(b)

Larger undercut
Resist

(a)
Dummy poly strip
Source metal 1
Etched layer
(c)
Figure 20.6 (a) A parallel device with dummy strips, (b) the equivalent circuit, and
(c) undercutting.

Figure 20.7 Devices with differing orientation (bad).

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Gate-drain contact Drain of M1

(a)

Sources of M1/M2
Drain of M2

M1 M1 M2 M2 M1 M1 M2 M2

M1 M2

(b)

Figure 20.8 (a) Layout of a simple current mirror using interdigitation and
(b) equivalent circuit.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

I REF IO
Drain of M1
Sources connected M1 M2
to ground 20/2 40/2

Drain of M2

(a)

Drain of M1

I REF IO

Drain of M2 M1
20/2
M2a M2b
20/2 20/2

Sources connected
(b) to ground

Figure 20.9 Layout of a current mirror (a) without width correction

and (b) with width correction.

VDD = 1 V
IO
M1 M2
100/2 100/2
I REF
65k I REF IO

(a)
VDD
(b)
Figure 20.10 How reference and output current vary with VDD.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD = 1 V

M1 M2 IO
100/2 100/2

IO I REF
I REF

(a)
VDD
(b)
Figure 20.11 Showing that VDD variations don’t affect the reference current.

VDD VDD
M3
M4
I REF IO IO

M2
M1
M2 mirrors the current
bias circuit in M1 while M4 mirrors
the current in M3.

Figure 20.12 A MOSFET-only bias circuit.

 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD I Op

M3, 30/2 M4, 30/2

I Op
M1, 10/270

Think of NMOS as the resistor.

Think of PMOS as the resistor.
VDD
I On

M3, 10/90
I On
M1, 10/2 M2, 10/2

Figure 20.13 Behavior of MOSFET-only bias circuits with changes in VDD.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

M2, K
M5 M1 M5
M2

R R

(a) (b)
VDD VDD

M4
M3 V biasp

M2, K
M1 V biasn

I REF I REF R

(c)

Figure 20.14 Developing the Beta-multiplier reference.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD

MSU3, M3, 30/2
M4, 30/2
MSU2, 10/100 10/1 V biasp

M2, 40/2
MSU1, 10/2 V biasn
M1, 10/2

I REF 6.5k
Start-up circuit
(important)

Figure 20.15 Beta-multiplier reference for biasing in the long-channel

process described in Table 9.1.

VDD

Figure 20.16 The reference currents through M1 and M2 in the Beta-multiplier.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD

VDD
V biasp M3
Reference M4
from Fig. 20.15 V biasn

M1 M2 M6
All NMOS are 10/2.
All PMOS are 30/2.
Figure 20.17 Circuit used in Ex. 20.3

VDD VDD VDD

M3, 100/2
M4, 100/2
MSU2, 10/20 V biasp

MSU3,
10/1 M2, 200/2
MSU1, 50/2 V biasn
M1, 50/2
I REF1 I REF2
6.5k
See Table 9.2.

VDD

Figure 20.18 Beta-multiplier reference for short-channel design (see Table 9.2).
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

V biasp M4, 100/2

M3, 100/2 V biasp

V biasn V reg
M2, 200/2
M1, 50/2 V biasn

I REF1 I REF2 5.5k

V biasp
V reg
V biasp V reg
10
Modeled in SPICE V biasn
V biasn using a voltage-controlled Gain
voltage source.
V biasp = 10 ⋅ (V reg − V biasn )

Figure 20.19 Increasing the output resistance of short-channel MOSFETs

using feedback. The result, for the Beta-multiplier circuit,
is better power supply sensitivity.

VDD

Figure 20.20 Improvement with the added amplifier.

 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

MA3, MA4,
100/2 100/2
Out

MA1, MA2,
50/2 50/2

Figure 20.21 A possible implementation of the diff-amp in Fig. 20.19.

VDD VDD VDD VDD VDD VDD

MSU2, 10/20
MCP,
100/100

V biasp
MSU3,
10/1 V biasn
V biasn V reg
MCN,
100/100
M2,
200/2
I REF1 I REF2 5.5k

All unlabeled NMOS are 50/2.

All unlabeled PMOS are 100/2.

Figure 20.22 Improved current reference for short-channel devices.

See also Sec. 23.1.3 for more information.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD
Figure 20.23 Variation of reference currents with VDD for the circuit in Fig. 20.22.

(a) MCP and MCN not present (b) MCP and MCN present

Figure 20.24 What happens when VDD is pulsed from 0 to 1 at 50 ns.

 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

T = 100 C
T = 80 C
T = 60 C
T = 40 C
T = 20 C
T=0 C

Figure 20.25 Variation in the reference gate voltage in the PMOS mirror seen in Fig. 20.11.

T=0C

T = 27 C

T = 100 C

Figure 20.26 Example 20.4 showing the temperature behavior of the

reference current in Fig. 20.10.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

T = 100 C
T = 75 C

T = 50 C

T = 25 C

T=0C

Figure 20.27 Temperature performance of a voltage reference using the Beta-multiplier.

VDD IO

Beta-multiplier V biasp
from Fig. 20.22 50/2 VO
(Table 9.2) V biasn

Think of
IO
IO

I D,sat I D,sat ro VO

1 1
Slope = r o =
167 kΩ
V DS,sat VO
Figure 20.28 How the finite output resistance of the MOSFET
affects the output current.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

V biasp
Beta-multiplier I REF IO
from Fig. 20.15 M5
(Table 9.1)
VO
M3 M4
M4 triodes

IO M1 M2

NMOS are 10/2.

PMOS are 30/2.

VO
M2 triodes

Figure 20.29 Biasing of the cascode current source and its operation.

iT

vT
M4 ro
v gs4

M2 ro −v gs4
v gs2 = 0
iT

Figure 20.30 AC circuit used to determine the output resistance of a cascode current source.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Table 20.1 Output resistances for cascode structures.

Cascode type Long-channel Short-channel

process, Table 9.1, Ro process, Table 9.2, Ro

PMOS 2.4 GΩ 16.6 MΩ

NMOS 3.75 GΩ 4.2 MΩ

VDD

V biasp I REF
≥ 2 ⋅ V DS,sat + V THN

2 ⋅ V GS = 2 ⋅ (V DS,sat + V THN ) M3 M4
V GS = V DS,sat + V THN

M1 M2
V GS = V DS,sat + V THN

(a) Regular cascode structure

≥ 2 ⋅ V DS,sat

V G = 2V DS,sat + V THN
M4
V DS,sat
V GS = V DS,sat + V THN
M2

(b) Low-voltage (aka wide-swing) structure

Figure 20.31 DC voltages in (a) a cascode current mirror and in

(b) a low-voltage cascode.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

V biasp I REF
I REF
M5a
M5b
V GS = 2V DS,sat + V THN
MWS M4

1 ⋅ W or 1 ⋅ W see text V GS = V DS,sat + V THN

4 L 5 L M1 M2

Figure 20.32 Generating a bias voltage for M4.

VDD VDD VDD

V biasp
Beta-multiplier IO
from Fig. 20.15
(Table 9.1)
VO
MWS
10/8 M4

IO M1 M2

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 30/2.

VO
2 ⋅ V DS,sat

Figure 20.33 Wide-swing cascode current source in the long-channel process.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Drain current of M2
C
A
M4
I steal B

M2

Drain-source voltage of M2

Figure 20.34 Showing how stealing current from M2 moves it into the triode region.

W
L
W
L
1⋅W
W
5 L
L
W
L
W
L

Figure 20.35 Using equal length devices to implement a long L MOSFET.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD

V biasp
Beta-multiplier M5b IO
from Fig. 20.22 M5a
(Table 9.2)
VO
MWS
50/8 M4

IO
M1 M2

Unlabeled NMOS are 50/2.

Unlabeled PMOS are 100/2.

VO

Figure 20.36 Wide-swing cascode current source in the short-channel process (bad).

IO

MWS is 10/10 in
Fig. 20.36.

VO

Figure 20.37 Increasing the W/L of MWS to 1/25 the other W/Ls.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD Added device

VDD
V biasp M5a
Beta-multiplier M5b IO
from Fig. 20.22
(Table 9.2)
VO
M3
MWS
10/10 M4

IO
M1 M2

Unlabeled NMOS are 50/2.

Unlabeled PMOS are 100/2.

VO
Figure 20.38 Wide-swing cascode current source in the short-channel process (good).
Notice the drain-to-source voltages of M1 and M2 are the same.

IO

VO
Figure 20.39 Resimulating the circuit in Fig. 20.39 using a 10/4 device for MWS.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

Added amplifier to increase output resistance.

IO
MWS M3
VO
M4

M1 M2

Figure 20.40 Regulating the drain of M2 using an amplifier.

iT
−A ⋅ i T ⋅ r o

vT
M4 ro
v gs4

M2 ro iT ⋅ ro
v gs2 = 0
iT

Figure 20.41 Determining the output impedance of a regulated drain current mirror.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD VDD

V biasp
Beta-multiplier IO
from Fig. 20.22
(Table 9.2) M5 MA3 MA4
VO
M3 M4

MA1 MA2
M1 M2
IO

NMOS are 50/2.

PMOS are 100/2.

VO
Figure 20.42 Using amplifiers to regulate the drain potentials in a current mirror.
 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD

VDD VDD VDD

VDD V bias1
V high
10/100
30/10 V bias2
10/1
V ncas

40/2

6.5k V bias3
From below

VDD VDD VDD

Bias voltages from above

V bias1

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 30/2.
See Table 9.1.

V pcas

10/10 V bias3
V low
V bias4

Figure 20.43 General biasing circuit for long-channel CMOS design using
the data in Table 9.1
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD I op

V bias1
30/2

V bias2
30/2

I op
V op
V op
I on
V on
I on
V bias3
10/2

V bias4
10/2

V on

Bias voltages come from Fig. 20.43 (long-channel parameters in Table 9.1).

Figure 20.44 How cascode currents are biased and how they operate.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD

V bias1 V bias1
MA4 MB7 MB8

V bias2 V bias2
MA3 MB5 MB7

Out Out
V bias3 V bias3
MA2 MB3 MB4

V bias4
MA1 MB1 MB2

(a) (b) Folded cascode structure

Bias voltages come from Fig. 20.43 (long-channel parameters in Table 9.1).
All NMOS are 10/2, while all PMOS are 30/2.

Figure 20.45 Using a folded cascode structure to make sure that

the current sourced by the PMOS equals the current
sourced by the NMOS.

VDD VDD
45/2 45/2
V bias1 30 µA
30 µA
10 µA
MB7 MB8

10 µA V bias2
V bias3
Out
M2 V bias3
V bias4 M1
10/4 20 µA 20 µA
10/4

Bias voltages come from Fig. 20.43 (long-channel parameters in Table 9.1).
All unlabeled NMOS are 10/2, while all unlabeled PMOS are 30/2.

Figure 20.46 Stealing current from the folded cascode structure.

 Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD VDD VDD VDD VDD VDD

10/20
MCP,
100/100

V biasp
10/1

200/2

5.5k

Unlabeled NMOS are 50/2. VDD

Unlabeled PMOS are 100/2.
See Table 9.2.
VDD VDD

VDD VDD V bias2

VDD V bias1
V biasp V high
20/10 V bias2
V pcas V ncas
10/10 V bias3
V low
V bias4 V bias3

Figure 20.47 General biasing circuit for short-channel design using

the data in Table 9.2.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD
I op
V bias1
100/2

V bias2
100/2

I op
V op V op
I on
V on
I on
V bias3
50/2

V bias4
50/2

V on

Bias voltages come from Fig. 20.47 (short-channel parameters in Table 9.2).

Figure 20.48 Cascode current sources operating in a short-channel process.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD

Ideally at V high V bias1

10 µA
VDD
Ideally at V bias1 V bias2

MOP, 1000/2
MFCP
V pcas 50/2 5 µA
100 µA Out
5 µA
V ncas 25/2
Ideally at V bias4
MFCN
MON, 500/2
V bias3
Ideally at V low
10 µA
Stage 2
V bias4

Stage 1

Bias voltages come from Fig. 20.47 (short-channel parameters in Table 9.2).
Unlabeled NMOS are 50/2, while unlabeled PMOS are 100/2.

Figure 20.49 Biasing with a floating current source.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Stage 1 Stage 2

Figure 20.50 The simulated currents that flow in stages 1 and 2

of the circuit in Fig. 20.49.

VDD VDD

100k 100k

M1 M2

M1 and M2 are 10/2.

Figure 20.51 Current mirror used in Problem 20.1.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

VDD

100k

M1 M2

M1 and M2 are 10/2.

Figure 20.52 Circuit used in Problem 20.2.

∆V THN

Figure 20.53 Modeling an offset voltage in SPICE (or for hand calculations).

VDD

Figure 20.54 Problems with reference current increasing with VDD.

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Figure 20.55 Resistance looking into the drain of a MOSFET with a source
resistance. See Problem 20.16.