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It is the longest path in the Circuit which decides the most critical function,and
requires the attention to timing details.
2.What are the main levels that a critical paths affect a system?
d=f+p
9.define effort delay.
The delay that depends on the load and on properties of the logic gate driving the
load.it is related in two terms: the logic effort of the logic gate and the electrical
effort h characteristics the load.
f=gh
Electrical effort is the ratio of output capacitance to the input capacitance of the
gate.the electrical effort h describes how the environment of the logic gate affects
the performance and how the size of the transistors in the gate determines its load
driving capability.
Logical effort of a gate is defined as the ratio of the input capacitance of the gate to
the input capacitance of an inverter that can deliver the same output current.
The parasitic delay is the ratio of the parasitic capacitance to the input capacitance
of the inverter which is just Pinv.
The logical effort along a path compounds by multiplying the logical efforts of all
the logic gates along the path.the path logical effort G is defined as
G=πgi
Power dissipation due to circuit switching to charge and discharge the output load
capacitance at a particular node at operating is called dynamic power dissipation.
during switching both nMOS and pMOs transistor will conduct simultaneously and
provide a direct path between Vdd and the ground rail resulting in short circuit
power dissipation
1.by selecting multi threshold voltages on critical paths with low-vt transistors
while leakage on other paths with high vt transistors
2.By using two operating modes active and stanby for each blocks
3. By adjusting the body bias (i.e) adjusting FBB in active mode to increase
performance and RBB in standby mode to reduce leakage.
4.By using sleep transistors to isolate the supply from the block to achieve
significant leakage savings.