HITEC University Taxila

Department of Electrical Engineering

Subject: ASIC Design

ASIC Design Assignment #02

Instructor:
Engr. Fahad Islam Cheema

Submitted By:
Nisar Ahmed Rana
07-HITEC-EE-94
Q 1:- We discussed general slice architecture of Xilinx FPGA.
a. Why this is better than PLD?
The PLD based on PAL is programmable array which can be programmed using logic with a fixed OR array and a
programmable AND array. The slice architecture of FPGA consist on Logic block having look up table, multiplexers, gates
and Flip-Flops .In FPGA we have the ability to reprogram the CLBs and implement a large variety of applications by using
different logic implementations in program using LUTs, MUX and Flip-Flops.
b. Why Xilinx selected 4-bit size of LUT?
Xilinx uses 4bit LUTs because it is designed using pass-transistor logic. Because pass-transistor logic is used, we must
double invert the output so that our output is true VDD or true GND. A common design rule for pass-transistor logic is to
only allow a signal to pass through a maximum of 4 transmission gates without being refreshed.
c. What tradeoff will occur, if we suggest 8-bit LUT?
If we use 8 bit LUT it is designed using pass-transistor logic. Using transmission gates, the select lines chose with bit to
output. Because pass-transistor logic is used, we must double invert the output so that our output is true VDD or true
GND. Without this double invert, our 8 bit LUT could lose its value. A common design rule for pass-transistor logic is to
only allow a signal to pass through a maximum of 4 transmission gates.
d. Can you suggest any improvements in this slice?
I think we can change two 4-bit lookup tables into one 8-bit lookup table. But this will need the entire change of basic
architecture.
Q 1:- What is the difference between Block-RAM (BRAM) and Distributed-RAM? Suppose we have
200 CLB in an FPGA and each CLB have four slices and each slice have 2 LUTs of 4-bit each and two
1-bit Flip Flops. What would be the maximum possible distributed RAM (in bytes) for this FPGA?
In Xilinx FPGAs, a B-RAM is a two port dedicated memory. It may contain several kilobits of memory. A FPGA contains
several of these blocks. A block RAM has synchronous write capability. It provides the capability for fast, discrete, large
blocks of RAM. Whereas for D-RAM, Inside of each small logic block is a configurable lookup table. It is normally used for
logic functions, but you can reconfigure it as a few bits of RAM. You can combine several of them into a larger RAM. This
is called distributed RAM. Both of these RAMs can be initialized with data, or used as a ROM.
Solution of Numerical:
Given Data:
Total number of CLBs = 200
No of slices in a CLB =4
LUT’s per slice = 2 (size of LUT is 4-bit)
Flip-Flop per slice = 2 (1-bit each)
Solution:
In a 4-bit LUT we have 16x1 registers
Total DRAM for given FPGA = 200x4x[2x16+2x1] bits
=200x4x34 bits
=27.2 kbits or 3.4 kbytes
Q 3:- Detail the difference between Single-port and dual-port RAM?
Single port RAM has a synchronous write operation and asynchronous read operation. Synchronous read operation are
possible by using the Flip-Flop associated with DRAM. Whereas dual port RAM has one synchronous write and the two
asynchronous read ports for the same reason mentioned in single port RAM. The dual port RAM has one R/W port and
an independent read port.