Ganesh Sir 1

Prof.
Ganesh Akoliya
Chapter – 2 & 3
Introduction to Microprocessor
The microprocessor is a programmable (means it can be instructed to perform the given task within
its capability) integrated device that has computing and decision-making capability similar to that
of a C.P.U of computer.
The microprocessor can be embedded in a larger system; can be stand-alone unit controlling
processes or it can function as the C.P.U of the computer called a Microcomputer.
The microprocessor communicates and operates in the binary numbers 0 and 1 called bits.
Each microprocessor has a fixed set of instructions in the form of binary patterns called a machine
language. Since it is difficult for the user to communicate in terms of 0s and 1s hence the binary
instruction are given abbreviated names called mnemonics, which forms the assembly language for
a given microprocessor.
Microcomputer: - The computer using the microprocessor as its CPU is called as microcomputer.
Block Diagram of Microprocessor based system and bus architecture: -
Input Output
Unit Unit
A.L.U R.U
Timing and
Control Unit
ROM RAM
Memory
Microprocessor is a semiconductor device consisting of electronic logic circuit. It is capable of
performing various computing functions and decision making to change the sequence of program
execution.
The three segments of microprocessor are: -
A.L.U: - This is the area of microprocessor where various computing functions are performed on
data. This unit performs arithmetic and logical operations such AND, OR, EXOR. The result is
either stored in registers or in memory.
Control Unit: - The control unit provides the necessary timing and control signals to all the
operations of processor. It also controls the flow of data between the microprocessor and memory
and peripherals.
Register unit (R.U): - It consists of Flip – Flop. The R.U consists of accumulator, Flag register, and
temporarily registers and two 16-bit pointers stack pointer and program counter.
A register stores digital information. One byte register will store 8-bit information.
• Accumulator: - It is an 8-bit register and is a part of A.L.U. It is used to store 8-bit data in
performing arithmetical and logical operations. The result of operation is also stored in
accumulator. The accumulator is also identified as A.
• Temporary Registers: - These registers store 8 bit or 16 bit information temporarily

before/after processing. 8 bit registers used are B, C, D, E, H, and L. For storing 16 bit
information register pairs are used such as BC, DE, and HL pair. These registers are
programmable means the user can use them to load or transfer data from registers by using
instructions. These registers can be viewed as memory locations except that they are built
inside the processor.
Prof. Ganesh Akoliya 1

Prof. Ganesh Akoliya
• Program counter: - It is a 16-bit pointer. This register is a memory pointer. The processor
uses this register to sequence the execution of instruction. The function is to point to the
memory location from which the next byte is to be fetched. When a byte is being fetched
the program counter is incremented by one to point to the next memory location.
• Stack Pointer (SP): - It is a 16-bit pointer, which is used as memory pointer. It points to the
memory location in read write memory called stack. The beginning of the stack is defined
by loading 16-bit address in the stack pointer.
• Flag Register: - It is an 8-bit register of which only 5 locations are empty. Flag registers
reflect the status of operation taking place in accumulator. The flags are stored in the 8-bit
register called so that the programmer can examine the flags by accessing the register
through the instruction.
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
1. Sign Flag (S): - After the execution of an arithmetic or logical operation if bit D7 of the
result is 1 the sign flag is set. This flag is used with signed numbers. In a given byte if D7
bit is 1 the number is viewed as a negative number; if it is zero then the number will be
considered as positive number. The bit D7 is reserved for indicating the sign and the
remaining seven digits are used for indicating the magnitude of the result.
2. Zero Flag (Z): - The zero flag is set if the ALU operation results in zero, and the flag is
reset if the result is not 0. This flag is modified by results in the accumulator as well as in
the other registers.
3. Parity Flag (P): - After an arithmetic and logical operation, if the result has even number of
1’s the flag is set. If it has odd number of 1’s then the parity flag is reset.
4. Carry Flag (CY): - If an arithmetic operation results in carry then the carry flag is set
otherwise it is reset. The carry flag also serves as a borrow flag for subtraction.
5. Auxiliary Cary (AC): - In an arithmetic operation when a carry is generated by digit D3 and
passed on to digit D4, the Ac flag is set. The flag is used only internally for BCD (Binary
Coded Decimal) operations and is not available for programmer to change the sequence of
a program with the jump instruction.
Introduction to Buses: - Various input output devices are connected to the CPU by a group of
lines called as Bus. There are three types of buses: address bus, data bus, and control bus.
 The address bus carries the address of a memory location or the I/O device that the CPU
has to access. When an address is sent by the processor all devices connected to it receive this
address but only that device will respond which has received the chip enable signal from the
CPU. The address bus is unidirectional. The address bus of the 8085 is 16-bit wide hence it can
address up to 64k bytes of memory location.
 Data bus is used to carry the data to the processor and from the processor either between
the memory and I/O devices. The data bus is bi-directional. The data bus for 8085 is 8-bit wide.
 Control bus is used to carry control signals between the CPU and various devices
connected to them. For e.g. the CPU issues Rd and WR control signals for read and write
operations. Depending on the status of these signals a device understands whether the CPU
wants to read from the device or write on the device.
Features of 8085:
 It is an 8-bit microprocessor i.e. it can accept or provide 8 bit data simultaneously.
 It is a single chip, NMOS device implemented with 6200 transistors.
 It requires a single +5 V power supply.
 The maximum clock frequency is 5MHZ; normally it operates with 3MHZ.
Pin diagram of 8085: The logic pin-out of 8085 is divided into 6 groups:
 Address Bus.
 Data Bus
 Control and status signals.
 Power supply and Frequency signals.
 Interrupt signals.
 Serial I/O ports.
 X1, X2: microprocessor requires a clock frequency of 3MHz. the internal circuitry
divides the clock frequency by two. Hence the crystal of 6MHz is connected across X1, X2.
 Clock out: The 3MHz clock frequency is available on this pin using which it can be
supplied to other peripheral devices.
 AD0-AD7: Multiplexed lower order address and data lines i.e. the same lines can
be used as address and data lines.
 Address latch enable (ALE): For any operation of the microprocessor the AD0-
AD7 lines are demultiplexed. This work is done by ALE line which is a positive pulse.
If ALE = 1 => AD0-AD7 will form A0-A7
If ALE =0 => AD0-AD7 will form D0-D7
 A15-A8: Unidirectional higher order address lines/bus.
 IO/M: If IO/M is high than IO devices are selected and if IO/M is low then memory is
selected.
 Rd: When Rd is low then the data is read from the selected device.
 Wr: When Wr is low then the data is written to the selected device.
 S0, S1: They are called status pins. By examine signals from S0 and S1 a certain operation
done by microprocessor can be determined.
IO/ S1 S0 Machine cycle

M
0 1 1 Opcode Fetch
0 1 0 Memory Read.
0 0 1 Memory write
1 1 0 IO Read
1 0 1 IO write
 Serial Output Data (SOD): By using this pin data is given by microprocessor serially.
 Serial Input Data (SID): By using this pin data is accepted serially.
 HOLD: This is s request signal which is given by peripheral device to the microprocessor
to have control over address and data lines.
 HLDA: If the microprocessor is ready to give the control of address and data lines to
external device then it provides Hold Acknowledge.
 RESET IN: The programming of microprocessor can be stopped by giving RESET signal.
When this signal is received the program counter is made 0000H. The flag register and
temporary registers are cleared.
 RESET OUT: By using this signal the microprocessor can reset other devices. RESET
OUT signal is given only when the microprocessor is reseted.
 READY: This signal is given by slow operating external device to fast operating
microprocessor for synchronization.
 RST 7.5, 6.5, 5.5, INTR, TRAP: This entire are interrupt request signals given to the
microprocessor.
 INTA: When INTR signal is accepted by microprocessor then it gives Interrupt
Acknowledge signal.
Architecture of 8085: The various blocks in the architecture of 8085 are:
 Address Buffer: When this unit is enabled A15 to A8 are available.

 Address and Data Buffer: When ALE=1 address buffer is enabled and A7-A0 are available.
When ALE=0 data buffer is enabled and D7-D0 are available.
 Increment or Decrement Latch: When this unit is in increment mode then ALE=1 and when
in decrement mode then ALE=0.
 Multiplexer: In multiplexed mode then 16-bit pairs HL, BC, DE are available and in
demultiplexed mode 8-bir registers B, C, D, E, H, L are available.
 Register Select (Register Decode): It is used to select the registers by decoding the signal
received from the control unit.

 Instruction decoder: The first part of only instruction is opcode. This is written in memory
in hexadecimal value. This opcode is brought in instruction decoder and decoded so that the
instruction can be identified.
 Instruction Register: If the instruction decoder is not free then the opcode is stored
temporary in instruction register.
 Control and Timing Unit: It gives signals for proper and sequential functioning of various
blocks of processor. This unit synchronizes all the microprocessor operations with clock and
generates control signals necessary for communication between microprocessor and external
devices.
 Serial IO Unit: This unit controls the serial data transfer of microprocessor.
 Interrupt Controller: this controls various interrupt operations taking place inside
microprocessor.
 Program Counter: It is a 16-bit pointer. This register is a memory pointer. The processor
uses this register to sequence the execution of instruction. The function is to point to the
memory location from which the next byte is to be fetched. When a byte is being fetched the
program counter is incremented by one to point to the next memory location.
 Stack Pointer (SP): - It is a 16-bit pointer, which is used as memory pointer. It points to the
memory location in read write memory called stack. The beginning of the stack is defined by
loading 16-bit address in the stack pointer.
 Accumulator: - It is an 8-bit register and is a part of A.L.U. It is used to store 8-bit data in
performing arithmetical and logical operations. The result of operation is also stored in
accumulator. The accumulator is also identified as A.
 Temporary Registers: - These registers store 8 bit or 16 bit information temporarily
before/after processing. 8 bit registers used are B, C, D, E, H, and L. For storing 16 bit
information register pairs are used such as BC, DE, and HL pair. These registers are
programmable means the user can use them to load or transfer data from registers by using
instructions. These registers can be viewed as memory locations except that they are built
inside the processor.
 Flag Register: - It is an 8-bit register of which only 5 locations are empty. Flag registers
reflect the status of operation taking place in accumulator. The flags are stored in the 8-bit
register called so that the programmer can examine the flags by accessing the register through
the instruction

Chapter – 5 & 6
Microcontroller-8051
8051 Features: -
1. 8-bit CPU with registers accumulator (A) and register B.
2. 16-bit Program Counter (PC) and Data pointer (DPTR).
3. 8-bit Program Status Word.
4. 8-bit Stack- Pointer.
5. Internal ROM or EPROM of 0 to 4K.
6. Internal Ram of 128 bytes:
Four register banks each containing eight registers.
Sixteen bytes which may be addressed at the bit level
Eighty bytes of general-purpose data memory.
7. Thirty-two input/output pins arranged as four 8-bit ports: P0 to P3.
8. Two 16-bit timers/counters: To and T1.
9. Full Duplex serial data receiver /transmitter: SBUF.
10. Control Registers: TCON, TMOD, SCON, PCON, IP and IE.
11. Two external and three internal interrupt sources.
12. Oscillator and clock circuits.
8051 Micro controller Architecture: - The 8051 micro controller is available in N-channel Metal
Oxide Silicon (NMOS) and Complementary Metal Oxide Silicon (CMOS). The 8051 is housed in a
40-pin DIP.
The figure shows the usual CPU components: Program Counter, ALU, working registers, and clock
circuits.
The programming model shows the 8051 as a collection of 8-bit and 16-bit registers and 8-bit
memory locations. Most of the registers have specific functions. Each registers except program
counter has an internal 1-byte address assigned to it. Some of the registers are both bit and byte
addressable i.e. the entire byte of data at the register address may be read; altered or individual bits
may be read or altered.
The pin out of 8051 is also shown with the full and abbreviated names of signals of each pin. Many of
the pins are used for more than one function.
E.g. port 3 bit 0 (P3.0) can be used as a general purpose I/O pin or also as an input (RXD) to SBUF
the serial data receiver register.
8051 Oscillator and clock: - Pins XTAL1 and XTAL2 are provided for connecting a resonating
network to form an oscillator. A quartz crystal and capacitors are employed. The crystal frequency is
the basic internal frequency of the micro controller.

The 8051 can be designed to run at specified maximum and minimum frequency from 1 MHz to 16
MHz. Ceramic resonators may be used as a low cost alternative to the crystal but decreases the
frequency stability and accuracy for high-speed serial data communication.
The clock frequency establishes the smallest interval of time within the micro controller called as
pulse P time. The machine cycle is made up of six states. A state is the basic time interval required for
discrete operations of micro controller. Program instructions may require one/two/ four machine
cycles to be executed depending upon the type of instructions.
There are two ALE pulses per machine cycle. The ALE pulse is used primarily as a timing pulse for
external memory access indicates when every instruction byte is to be fetched. Two bytes of single
instruction are to be fetched and executed in one machine cycle. But single byte instructions are not
executed in half cycle they throw away the second byte (which is the first byte of the next
instruction.)
Program Counter and Data Pointer: - The 8051 contains two 16-bit registers: the program counter
(PC) and the data pointer (DPTR). Each is used to hold address of a byte in memory.
Program instruction bytes are fetched from locations in memory that are addressed by PC. Program
ROM may be on chip at addresses 0000H to 0FFF H, external to the chip for addresses that exceeds
0FFF h, or totally external for all addresses from 0000 H to FFFF H. The PC is incremented
automatically after every instruction byte is fetched. The PC is the only register that does not have
any address.
The DPTR register is made up of two registers named as DPH and DPL. Which are used to access
any memory address that may be internal and external code access and external data access. The
DPTR is under the program control and can also be specified as16-bit pointer as DPTR or by
individual 8-bits as DPH and DPL. DPTR does have a single address but the DPH is assigned the
address as 83H and DPL is assigned the address as 82H.
A and B CPU registers: - The 8051 contains 34 general-purpose registers/working registers. Two of
these are A and B, which holds results of many instructions, particularly math and logical operations
of the 8051 CPU. The other 32 are arranged as part of internal RAM in four banks as B0 to B3 of
eight registers.
The A (accumulator) register is the most versatile out of the CPU registers and used for many
operations including addition, subtraction, integer multiplication and division and also bit
manipulations. The A is also use for all data transfers between the 8051 and external memory. The B
register is used with the A register for multiplication and division operations and no other function
other than a location where the data may be stored.
Flags and Program Status Word (PSW): - Flags are 1-bit registers provided to store the results of
certain program instructions. Other instructions can test the condition of the flags and make decisions
based on the flag states. For addressing the flags they are grouped inside the Program status word
(PSW) and the power control (PCON) registers.
The 8051 ahs four-math flags that respond automatically to the outcomes of math operations and
three general purpose user flags that can be set to 1 or cleared to 0. The math flags include Carry (C),
Auxiliary flag (AC), Overflow Flag (OV), and Parity (P). User flags are named F0, GF0 and GF1,
which are general-purpose flags that may be used by the programmer to record some event in the
program.
The program stats word contains the math flags, user flags F0 and the register select bits that identify
which of the four general purpose register banks is currently in use by the program. The remaining
two user flags GF0, GF1 are stored in PCON.
Internal Memory: - A computer must have memory for program code bytes, commonly in ROM,
and RAM memory for variable data that can be altered as the program runs. The 8051 have internal
RAM and ROM memory for these functions.

Internal RAM: - The 128 byte internal RAM is organized into three distinct areas: -
 Thirty-two bytes from address 00 H to 1F H that make up 32 working registers organized as four
banks of eight register each. The four registers banks are numbered 0 to 3 and are made up of
eight registers named R0 to R7. Each register can be addressed by name (when it’s bank is
selected) or by its RAM address. Thus R0 of bank 3 is R0 if bank 3 rd is selected or address 18H
whether bank 3 is selected or not. Bits RS0 and RS1 in the PSW determine which bank of
registers is currently in use at any time when the program is running. Registers banks not selected
can be used as general-purpose RAM. Bank 0 is selected on reset.
 A 2-bit addressable area of 16 bytes occupies RAM byte addresses 20 H to 2F H, forming a total
of 128 addressable bits. An addressable bit may be specified by its bits address of 00 H to 7F H or
8-bits may form any byte address from 20 H to 2F H. thus for e.g. bit address 4F H is also bit 7 of
byte address 29H. Addressable bits are useful when the program need only remember a binary
event.
 A general purpose RAM area above the bit area, from 30 H to 7F H addressable as bytes.

Internal ROM: - The 8051 so that data memory and program code memory can be in two different physical
entities. Each has the same address ranges.
A corresponding block of internal program code occupies the code address space 0000H to 0FFFH. The PC
is ordinarily used to address program code bytes from addresses 0000H to FFFFH. Program addresses
higher than 0FFFH, which exceed the internal ROM capacity, will cause the 8051 to automatically fetch
code bytes from external program memory. Code bytes can also be fetched from an external memory,
addresses 0000H to FFFFH by connecting the external access pin (pin 31 on the DIP) to ground.
Stack and the Stack Pointer: - The stack refers to an area of internal RAM that is used in
conjunction with certain opcodes to store and retrieve data quickly. The 8-bit Stack pointer (SP)
register is used by the 8051 to hold an internal RAM address that is called the top of stack. The
address held in the SP register is the location in internal RAM where the last byte of data was
stored by a stack operation. When the data is to be placed on the stack, the SP increments before
storing data on stack so that the stack grows up, as data is stored. As data is retrieved from the
stack, the byte is read from the stack, and then the SP decrements to point to the next available
byte of stored data.
Special Function Registers: - The 8051 operations that do not use the internal 128-byte addresses
from 00H to 7FH. Are done by a group of specific internal registers, each called a Special Function
Registers (SFR), which may be addressed much like internal RAM using addresses from 80H to FFH.
Some SFR’s are also bit addressable (marked with an * in the programming model). This feature
allows the programmer to change only what needs to be altered leaving the remaining bits in that SFR
unchanged. All address from 80H to FFH is not used. An attempt to use an address that is not defined
or empty results in an unpredictable results. SFR’s are named in certain opcodes by their functional
names such as A or TH0 and they are referred by other opcodes by their address as 0E0H or 8CH.
Any address in the program must start with a number thus address E0H for the A begins with 0 if not
used it results in an assembler error.

Architecture of 8051:

Block diagram of 8051:

Pin- Diagram of 8051:

Input/Output Pins, Ports and Circuits: - The major feature of the micro controllers is that it has
built in I/O ports/circuits that connects it outside. The Dip has 40 pins and has flexibility built into use
of these pins. For this reason 24 of the pins has been given Dual function. The function of the pin
perform at any instant depends on what is physically connected to it and then what software
commands are used to program the pin. Due to flexibility the 8051 may be configured as single
component with I/O only, or may be expanded to include additional memory, parallel ports, and serial
data communication by using alternate pin assignments. Each port has a D-type output latch for each
pin. The SFR for each port is made up of these eight latches, which can be addressed at the SFR
address for that port i.e. the eight latches for port 0 are addressed at location 80H. The two data paths
are shown by the circuits that read the latch or pin data by using entirely separate buffers. The upper
buffer is enabled when the latch data is read, and the lower buffer when the pin state is to be read.
The status of each latch may be read from a latch buffer, while an input buffer is connected directly to
each pin so that the pin status may be read independently of latch state. Programmable port pins have
completely different alternate functions. The configuration of the control circuit between the output
latch and the port pin determines the nature of any particular port pin function.
Port 0: - Port 0 pins may serve as inputs, outputs or when used together as a bi-directional low order
address and data bus for external memory.

 Input: When used as an input a 1 is written to the corresponding port 0 latch by the program, thus
turning both of the output transistors off, which in turn causes the pin to “float” in a high impedance
state, and the pin is essential connected to the input buffer.
 Output: When used as an output, the pin latches that are programmed to a 0 will turn on the lower
FET grounding the pin. All the latches that are programmed to a 1 still float, thus external pull-up
resistors will be needed to supply logic high when using port 0 as an output.
 Address: When a port 0 is used as an address bus to external memory, internal control signals
switch the address lines to the gates of the FET’s. Logic 1 on the address bit will turn the upper FET
on the lower FET off to provide logic high at that pin. When the address bit a zero, the lower FET is
on and the upper FET off to provide a logic a logic low at the pin. After the address has been formed
and latched into external circuits by the ALE pulse, the bus is turned around to become a data bus.
Port 0 now reads data from the external memory and must be configured as an input so logic 1 is
automatically written by the internal control logic to all port 0 latches.
Port 1: - Port 1 pins have no dual functions. Therefore the output latch is connected directly to the
gate of the lower FET, which has an FET circuit labeled internal FET pull-up as an Active Pull-up
load.
 Input: When used as an input a 1 is written to the latch, turning the lower FET off, the pin and
the input to the pin buffer are pulled high by the FET load. An external circuit can overcome the high
impedance pull-up and drive the pin low to input a 0 or leave the input high for 1.
 Output: When used as an output the latches containing a 1 can drive the input of an external
circuit high through the pull-up. If a 0 is written to the latch, the lower FET is on, the pull-up is off,
and the pin can drive the input of the external circuit low. To help in speeding the switching times
when the pin is used as an output, the internal FET pull-up has another FET in parallel with it. The
second FET is turned on for two oscillators time periods during a low to high transition on the pin.
This arrangement provides a low impedance path to the positive voltage supply to help reduce rise
times in charging any parasitic capacitances in the external circuitry.
Port 2: - Port 2 may be used as an input/output port similar to operation of port 1. The alternate use of
port 2 is to supply a high order address byte in conjunction with the port 0 low order byte to address
external memory. Port 2 pins are momentarily changed by the address control signals when supplying
the high byte of a 16-bit address, as they do not have to be turned around (set to 1) for data input, as is
the case for port 0.
Port 3: - Port 3 is an input/output port similar to port1. The input and output functions can be
programmed under the control of the P3 latches or under the control of various other special function
registers. The port 3 alternate uses are as follows:
Pin Alternate Use SFR

P3.0-RXD Serial Data Input SBUF
P3.1-TXD Serial Data Output SBUF
P3.2-INTO External Interrupt 0 TCON.1
P3.3-INT1 External Interrupt 1 TCON.3
P3.4-T0 External Timer 0 Input TMOD
P3.5-T1 External Timer 1 Input TMON
P3.6-WR External Memory write pulse ----------
P3.7-RD External Memory read pulse ---------
Unlike ports 0 and 2, which can have external, addressing functions and change all eight port bits
when in alternate use each pin of port 3 may be individually programmed to be used either as I/O or
as one of the alternate functions.
Counters and Timers: - Many micro controller applications require the counting of external events
such as frequency of pulse train and generation of precise time delays between computer applications.
Using software programs can do both these tasks but these keep the processor occupied and hence the
processor can execute no other functions. Hence for this purpose two 16- bit up counters T0 and T1
are used.
The counters are divided into two 8-bit registers called the timer low (TL0, TL1)
and timer high (TH0, TH1) bytes. All control actions are controlled by bit states in the timer mode
control register (TMOD), the timer/counter control register (TCON), and certain program
instructions.
TMOD is dedicated to the two timers and can be considered to be duplicate 4-bit registers each of
which controls the action of one of the timers. TCON has control bits and flags for timers in the upper
4-bits and control bits and flags for external interrupts in the lower 4-bits.
Timing: - If a counter is programmed to be a timer it will count the internal clock frequency of the
8051 oscillator divided by 12d.
E.g. If crystal frequency is 6MHz then the timer clock will have a frequency of 500Khz.
In order for oscillator lock pulses to reach the Timer the C/T bit in the TMOD register must be set to
zero (timer operation). Bit TRX in the TCON register must be set to 1 (timer run) and the gate bit in
the TMOD register must be 0 or external pin INTX must be 1 i.e. the counter is configured as a timer,
then the timer pulses are gated to the counter by the run bit and gate bit or the external input bits
INTX.
TCON Control Word:
D7 D6 D5 D4 D3 D2 D1 D0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit addressable as TCON.0 to TCON.7
• TF1: Timer 1 Overflow flag: Set when timer rolls from all 1’s to all 0’s. Cleared when
processor vectors to execute interrupt service routine located at address 001B H.
• TR1: Timer 1 run control bit: Set to 1 by program to enable timer to count. Cleared to 0 by
program to halt the timer. Does not reset the timer.
• TF0: Timer 0 Overflow flag: Set when timer rolls from all 1’s to all 0’s. Cleared when
processor vectors to execute interrupt service routine located at address 000B H.
• TR0: Timer 0 run control bit: Set to 1 by program to enable timer to count. Cleared to 0 by
program to halt the timer. Does not reset the timer.
• IE1: External interrupt 1 Edge flag: Set to 1 when a high –low edge signal is received on port
3.3 (INT1’). Cleared when processor vectors to interrupt service routine at program address 0013
H. Not related to timer operations
• IT1: External interrupt 1 signal type control bit: Set to 1 by program to enable external
interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low level
signal on the external interrupt 1 to generate an interrupt.
• IE0: External interrupt 0 Edge flag: Set to 1 when a high –low edge signal is received on port
3.2 (INT0’). Cleared when processor vectors to interrupt service routine at program address 0003
H. Not related to timer operations
• IT0: External interrupt 0 signal type control bit: Set to 1 by program to enable external
interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low level
signal on the external interrupt 1 to generate an interrupt.
TMOD control word:

D7 D6 D5 D4 D3 D2 D1 D0
Gate C /T M1 M0 GATE C / T M1 M0
Timer 1 Timer 0
7/3: Gate: OR gate enable bit that controls RUN/STOP of timer 1/0. set to 1 by program to enable
timer to run if TR1/0 in TCON is set and signal on external interrupt INT1/0 ‘ pin is high. Cleared to
0 by program to enable timer to run if bit TR1/0 in TCON is set.
6/2: C / T : Set to 1 by program to make timer 1/0 act as counter by counting pulses from external
input pins 3.5 (T1) or 3.4 (T0). Cleared to 0 by program to make timer by counting internal
frequency.
5/1 M1: Timer/ Counter operating mode select bit 1. Set / cleared by program to select mode.
4/0 M0: Timer/ Counter operating mode select bit 0. Set / cleared by program to select mode.
M1 M0 Mode
0 0 0
0 1 1
1 0 2
1 1 3
Timer Mode of Operation: - The timers may operate in any of four modes that are determined by
the mode bits M1 and M0 in the TMOD register.
• Timer Mode 0: 13 bit Timer/Counter: - Setting timer X mode bits to 00b in the TMOD register
results in using the THX register as an 8-bit counter and the TLX as a 5-bit counter, the pulse
input is divided by 32d in the TL so that TH counts the original frequency reduced by a total
384d.
Pulse
I/p TLX 5 THX 8 Bits TFX Interrupt
Bits
E.g. the 6Mhz oscillator frequency would result in a final frequency to TH of 15625 Hz. The
timer flag is set when THX goes from FFh to 00h in 0.164 sec.
• Timer Mode 1: 16 Bit Timer/Counter: - Mode 1 is similar to Mode 0 except that TLX is
configured as a full 8-bit counter when the mode bits are set to 01b in TMOD register.
Pulse
I/P
TLX 8 THX 8 Bits TFX Interrupt
Bits
E.g. the timer flag will be set in 0.1311 seconds using a 6Megahertz crystal.
• Timer Mode 2: Auto Reload of TL from TH: - Setting the timer in mode bits to 10b in TMOD
register configures the timer to use only the TLX counter as an 8-bit counter. THX is used to hold
the value that is loaded into the TLX register everytime the TLX overflows from FFh to 00h. The
Timer flag is also set when the TLX overflows.
Pulse I/P TLX 8 Bits TFX Interrupt
Reload
THX 8 Bits

This mode exhibits auto-reload function. TLX will count up from the number in THX, overflow
and be initialized again with the contents of THX.
• Timer Mode 3: Two 8-bits Timers using Timer 0: - Timers 0 and 1 can be programmed to be in
mode 0, 1, or 2 independently of a similar mode for the other timers. Timers do not operate
independently if mode 3 is selected for Timer 0. Placing Timer 1 in mode 3 causes it to stop
counting, the control bit TR1 and the Timer 1 Flag TF1 are then used by timer 0.
Pulse I/P TL0 8 Bits TF0 Interrupt
F /12
(TR1 bit TH0 8 Bits TF1 Interrupt
In TCON)
Timer 0 in mode 3 becomes two completely separate 8-bits counters. TL0is controlled by gate
arrangement and sets timer flag TF0 whenever it overflows from FFh to 00h. TH0 receives the
timer clock under the control of TR1 only and sets the TF1 flag when it overflows.
Timer 1 may still be used in modes 0,1, and 2 while the timer 0 is in mode 3. But no interrupts can
be generated by timer1 while timer 0 is using the TF1 overflow flag. Hence timer 1 can be used as
baud rate generator or any other mode 0,1 or 2 function that does not depend upon interrupt.
Counting: - The only difference between counting and timing is the source of the clock pulses to the
counters. When used as a timer, the clock pulses are sourced from the oscillator through the divide by
12d. When used as a counter, pin T0 (p3.4) supplies pulses to counter 0 and pin T1 (P 3.5) to counter
1. The C/T bit in TMOD must be set to 1 to enable pulses from the TX pin to reach the control circuit.
The input pulse on TX is sampled during the P2 state of 5 every machine cycle. A change on the
input from high to low between samples will increment the counter. Each high and low state of the
input pulse must be held constant for at least one machine cycle to ensure reliable counting.
Serial Data Input /Output: - Computers must be able to communicate with other computers in
modern multiprocessor distributed systems. One way to communicate is to send and receive data bits
serially. The 8051 have a serial data communication circuit that uses register SBUF to hold data.
Register SCON controls data communication; register PCON control data rates, and pins RXD (P3.0)
and TXD (P3.1) connect to the serial data network. SBUF is physically two registers. One is write
only and is used to hold data to be transmitted out of the 8051 via TXD. The other is read only and
holds received data from external sources via RXD. Both exclusive registers use address 99h.There
are four programmable modes for serial data communication that are chosen by setting the SMX bits
in the SCON register. Baud rates are determined by the selected mode.
Serial Data interrupts: - Serial data communication is a relatively slow process, occupying many
milliseconds per data byte to accomplish. The data transmission is under the program control but the
reception of data is unpredictable and at random times that are beyond the control of program. The
serial data flags in SCON, T1 and R1 are set whenever a data byte is transmitted (T1) or received
(R1). These flags are ORed together to produce an interrupt to the program. The program must read
these flags to determine which caused the interrupt and then clear the flag.
Data Transmission: - Transmission of serial data bits begins anytime data is written to SBUF. T1 is
set to a 1 when the data has been transmitted and signifies that SBUF is empty and that another data
byte can be sent. If the program fails to wait for the T1 flag and overwrites SBUF while a previous
data byte is in process of being transmitted the results will be unpredictable.
Data Reception: - Reception of serial data will begin if the receive enable bit (REN) in SCON is set to
1 for all modes. In addition for mode 0 only, RI must be cleared to 0. Receiver interrupt flag RI is set
after data has been received in all modes. Setting REN is the only direct program control that limits
the reception of unexpected data, the requirement that RI also be 0 for mode 0 prevents the reception
of new data until the program has dealt with the old data and reset RI. Reception can begin in modes
1, 2 and 3 if RI is set when the serial stream of bits begins. RI must have been reset by the program
before the last bit is received or the incoming data will be lost. Incoming data is not transferred to
SBUF until the last data bit has been received so that the previous transmission can be read from
SBUF while new data is being received.
SCON Control Word:
D7 D6 D5 D4 D3 D2 D1 D0
SM0 SM1 SM2 REN TB8 RB8 TI RI
 SM0: Serial port mode bit 0. Set / Cleared by program to select mode.
 SM1: Serial port mode bit 1. Set / Cleared by program to select mode.
SM0 SM1 Mode Description

0 0 0 Shift Register; Baud rate = f / 12
0 1 1 8-bit UART; Baud rate = variable
1 0 2 9-bit UART; Baud rate = f / 32 or f / 64
1 1 3 9-bit UART; Baud rate = variable
 SM2: Multiprocessor Communication bit: Set / Cleared by program to enable multiprocessor

communications in modes 2 & 3. When set to 1 an interrupt is generated if bit 9 of received data
is 1; no interrupt is generated if bit 9 is 0. if set to 1 for mode 1, no interrupt is generated unless a
valid stop bit is received. Clear to 0 if mode 0 is in use.
 REN: Receive enable bit: Set to 1 to enable reception; cleared to 0 to disable reception.
 TB8: Transmit bit 8: set / cleared by program in modes 2 & 3.
 RB8: Receive bit 8: set / cleared by program in modes 2 & 3.
 TI: Transmit Interrupt Flag: Set to 1 at the end of bit 7 time in mode 0 & at the beginning of
the stop bit of other modes. Must be cleared by program.
 RI: Receive Interrupt Flag: Set to 1 at the end of bit 7 time in mode 0 & half way through the
stop bit of other modes. Must be cleared by program.
Serial Data Transmission Modes: - The 8051 have included four modes of serial data transmission
that enable data communication to be done in a variety of ways and a multitude of baud rates. Modes
are selected by the programmer by setting the mode bits SM0 and SM1 in SCON. Baud rates are
fixed for mode 0 and variable using timer1 and the serial baud rate modify bit (SMOD) in PCON for
modes 1, 2 and 3.
 Serial Data Mode 0: Shift Register Mode: - Setting bits SMO and SM1 in SCON to 00b
configures SBUF to receive or transmit eight data bits using pin RXD for both functions. Pin TXD is
connected to the internal shift frequency pulse source to supply shift pulses to external circuits. The
shift frequency or baud rate is fixed at 1/12 of the oscillator frequency, the same rate used by the
timers when in the timer mode. The TXD shift clock is a square wave that is low for machine cycle
states S3-S4-S5 and high for S6-S1-S2.

When transmitting data is shifted out of RXD, the data changes on the falling edge of S6P2, or one
clock pulse after the rising edge of the output TXD shift clock. The user must design the circuit that
receives this data to receive the data reliably based on this timing.
Received data comes in on pin RXD and should be synchronized with the shift clock produced at
TXD. Data is sampled on the falling edge of S5P2 and shifted into SBUF on the rising edge of the
shift clock.
Mode 0 is not intended for data communication between computers but as a high-speed serial data-
collection method using discrete logic to achieve high data rates. The baud rate used in mode 0 will
be much higher than standard for any oscillator frequency.
 Serial Data Mode 1: Standard UART: - When SM0 and SM1 are set to 01b SBUF becomes a 10-
bit full duplex receiver/transmitter that may receive and transmit data at the same time. Pin RXD
receives all data, and pin TXD transmits all data.
Transmitted data is send as a start bit, eight data bits (at least LSB first) and then stop bit. Interrupt
flag T1 is set once all ten bits have been sent. Each bit interval is the inverse of the baud rate
frequency, and each bit is maintained high or low over that interval.
Received data is obtained in the same order. Reception is triggered by the falling edge of the start bit
and continues if the stop bit is true (0 level) halfway through the start bit interval. This is an anti-noise
measure; if the reception circuit is triggered by noise on the transmission line, the check for a low
after half a bit interval should limit false data reception.
Data bits are shifted into the receiver at the programmed baud rate, and the data word will be loaded
to SBUF if the following conditions are true: RI must be 0, and mode bit SM2 is 0 or the stop bit is 1
(the normal state of stop bits). RI set to 0 implies that the program has read the previous data byte and
is ready to receive the next; a normal stop bit will then complete the transfer of data to SBUF
regardless of the state of SM2. SM2 set to 0 enables the reception of a byte with any stop-bit state, a
condition that is of limited use in this mode, but very useful in modes 2 and 3. SM2 set to 1 forces
reception of only “good” stop bits, an anti-noise safeguard. Of the original ten bits, the start bit is
discarded the eight data bits go to SBUF, and the stop bit is saved in bit RB8 of SCON. RI is set to 1,
indicating a new data byte has been received.
If RI is found to be set at the end of the reception, indicating that the previously received data byte
has not been read by the program, or if the other conditions listed are not true, the new data will not
be loaded and will be lost.
 Serial Data Mode 2: Multimode Mode: -

Mode 2 is similar to mode 1 except 11 bits are transmitted: a start bit, nine data bits, and a stop bit.
The ninth data bit is copied from bit TB8 in SCON during transmit and stored in bit RB8 of SCON
when data is received. Both the start and stop bits are discarded.
The conditions for settings R1 for mode 2 are similar to mode 1: R1 must be 0 before the last bit is
received, and SM2 must be 0 or the ninth data bit must be at 1. Setting R1 based on the state of SM2
in the receiving 8051 and the state of bit 9 in the transmitted message makes multiprocessing possible
by enabling some receivers to be interrupted by certain messages, while other receivers ignore those
messages. Only those 8051s that have SM2 set to 0 will be interrupted by received data that has the
ninth data bit set to 0; those with SM2 set to 1 will not be interrupted by messages with data bit 9 at 0.
All receivers will be interrupted by data words that have the ninth data bit set to 1; the state of SM2
will not block reception of such messages.
 SERIAL DATA MODE 3

Mode 3 is identical to mode 2 except that the baud rate is determined exactly as in mode 1; using
timer 1to generate communication frequencies.
Addressing Modes: - Data is stored at the source address and moved to a destination address. The
ways by which these addresses are specified are called the addressing modes. The 8051 mnemonics
are written with the destination address named first followed by source address.
The addressing modes of 8051: -
 Immediate addressing modes.
 Register addressing mode.

 Direst addressing mode.
 Indirect addressing mode.
 Direct and Immediate addressing mode.
 Indirect and immediate mode.
 Indirect and Direct addressing mode.
Immediate addressing mode: -The simplest way to get data to a destination address is to make the
source of the data part of the opcode. The data source is then immediately available as a part of
instruction.
When the 8051 execute an immediate data move, the program counter is automatically incremented
to point to the byte(s) following the opcode byte in the program memory.
The mnemonic for the immediate data is pound sign #.
E.g. MOV A, #n: - Copy immediate data byte n to register A.
MOV DPTR, #nn: - Copy the immediate 16-bit number nn to the DPTR register.
MOV A, #0F1H: - Move the immediate data byte F1H to the A register.
Register Addressing Mode: - Certain register names may be used as part of the opcode mnemonic as
source or destination of data. Registers A, DPTR, and R0 to R7 may be named as a part of the
mnemonic opcode.
The register names used in the opcode as R0 to R7 are those that are currently selected by the bank
select bits RS0 and RS1 in the PSW.
E.g. MOV A, R0: - Copy the data in register R0 to register A.
MOV R5, #A: - Copy the data in register A to register R5.
NOTE: - Register to Register moves using the register addressing modes must occur between
registers A and R0 to R7.
Direct Addressing modes: - All 128 bytes of internal RAM and the SFR’s may be addressed directly
using the single byte addresses assigned to each RAM location and to each special SFR’s. Internal
RAM uses address from 00H to 7FH and that of SFR’s ranges from 80H to FFH.
Only one bank of working registers is active at any given time. The PSW special function register
holds the bank select bits RS0 and RS1, which determine which register bank, is in use. When the
8051 is resetted RS0 and RS1 are set to 00H to set the working registers in the bank 0, located from
00H to 07H in internal RAM. Reset also sets SP to 07H.
E.g. MOV Rr, add: - Copy data from direct address add to register Rr.
MOV add1, add2: - Copy data from direct address add2 to direct address add1.
Indirect Addressing Mode: - The indirect addressing mode uses a register to hold the actual address
that will be used in data moves, the register it self is not the address but the number in the register.
Indirect addressing for MOV opcodes uses register R0 or R1 often called as data pointer to hold the
address of one of the data locations in RAM address 00H to 07H.
The mnemonic symbol used for indirect addressing is the @ symbol. Only registers R0 or R1 may be
used for indirect addressing mode. The number in register Rp must be a RAM address.
E.g. MOV A, @R0: -Copy the contents of the address in R0 to the register A.
MOV@R1,#35H: - Copy the number 35H to address in R1.
MOV add, @Rp: - Copy the contents of the address in Rp to add.
Direct and Immediate Addressing: - This is the combination of direct and immediate addressing
mode. In this mode the destination operand is the data memory while the source operand is the
immediate operand. The address of the operand is specified as second byte and the immediate
operand is specified as third byte. The immediate operand is stored in program memory along with
the opcode.
e.g. MOV 08,#06: - In this 08 H is the address of the destination data memory location and 06 is the
immediate operand.
Indirect and Immediate Addressing: - This is the combination of indirect and immediate addressing
modes. In this addressing mode the destination is located by indirect addressing mode while source is

specified as immediate operand. The address of the destination operand is stored in memory pointer
Rp. This is applicable only to internal data memory only. The length of this instruction is two bytes.
e.g. MOV @ Rp, 08: - In this instruction 08 is the immediate operand.
Indirect and Direct addressing mode: - This is the combination of indirect and direct addressing
modes. In this mode the source or destination operand is located by indirect addressing mode while
destination operand is located by direct addressing modes i.e. one operand is indirect and other is
direct. The length of this instruction is two bytes. In this Rp is used as an 8- bit pointer. It is not
applicable to external data memory.
E.g. PUSH 07: - The address of the destination is stored in SP and 07H is the address of the source
memory.
Byte level logical operations: - The byte level logical operations use all four addressing modes for
the source of a data byte. The A register or a direct address in internal RAM is the destination of the
logical operation result.
No flags are affected by the byte level logical operations unless the RAM address is PSW. Many of
the byte level operations use a direct address, which can include the port SFR addresses as a
destination. The normal source of data from a port is the port pins; the destination for the port data is
the port latch. When the destination of the logical operations is the direct address of a port the latch
register is used as both the source for the original data and then the destination for the altered byte of
data.
Mnemonic Operation
ANL A, #n AND each bit of A with the immediate number & result in A.
ANL A, add AND each bit of A with the contents of address & result in A.
ORL A, # n OR each bit of A with the immediate number & result in A.
ORL A, Add OR each bit of A with the contents of address & result in A.
XRL A, #n XOR each bit of A with the immediate number & result in A.
XRL A, add XOR each bit of A with the contents of address & result in A.
CLR A Clear each bit of A register to 0
CPL A Complement each bit of A.
Bit Level Logical Operations: - Bit addressing is the convenient when a single bit of byte is to be
altered. Only Carry flag is affected unless the flag is an addressed bit.
Rotate and Swap Operations: - The ability to rotate data is useful for inspecting bits of a byte
without using individual bit opcodes. The A register can be rotated one bit position to left or right
with or without carry flag in the rotation.
The swap instruction can be thought of as a rotation of nibbles in the A register.
Rotate and Swap instructions are related to A register.
 RL A : Rotate the A register one bit position to left.

 RLC A: Rotate the A register and the carry flag as a ninth bit one bit position to left.
 RR A: Rotate the A register to one bit position to right.
 RRC A : Rotate the A register and the carry flag as a ninth bit one bit position to the right.
 SWAP A : Interchange the nibbles of register A, i.e. put the upper nibble position and the low
nibble in high nibble position.
Incrementing or Decrementing instructions: - The simplest arithmetic operations involve adding or

subtracting a binary 1 with a number. These simple operations are coupled with ability to repeat the
operations of INCrement and DECrement until the desired result is reached.
Mnemonic Operation
INC A Add 1 to the contents of A and result in A
INC Rr Add 1 to the contents of Rr and result in Rr
DEC A Subtract 1 to the contents of A and result in A
DEC Rr Subtract 1 to the contents of Rr and result in Rr
Addition: - All addition is done with A register as a destination of the result. All addressing modes
may be used for the source: an immediate number, a register, a direct address or an indirect address.
Some instructions include carry flag as an additional source of a single bit that is included in the
operation at the LSB position.
Mnemonic Operation
ADD A, #n Add A and the immediate number n; result in A

ADD A, Rr Add A and register Rr; put the sum in A
ADD A, add Add A and the address contents; put the result in A
ADD A, @Rp Add a and the contents of the address in Rp; put the sum in A
The following instructions list the add with Carry:
Mnemonic Operation
ADDC A, #n Add A and the immediate number n and the carry flag; result in A
ADDC A, Rr Add A and register Rr and the carry flag; put the sum in A
ADDC A, add Add A and the address contents and the carry flag; put the result in A
ADDC A, @Rp Add A and the contents of the address in Rp and the carry flag; put the sum in A
Subtraction: - Subtraction can be done by taking the two’s complement of the number to be
subtracted and the subtrahend, and adding it to another number, the minuend. Register A is the
destination address for subtraction. All four addressing modes may be used for source address. The
commands treat the carry flag as a borrow ad always subtract the carry as part of the operation.
Mnemonic Operation
SUBB A, #n Subtract immediate number n and the C flag from A, result in A

SUBB A, add Subtract the contents of add and C flag from A, result in A
SUBB A, Rr Subtract Rr and C flag from A, result in A
SUBB A, @Rp Subtract the contents of the address in Rp and C flag from A, result in A.
Multiplication: - Multiplication operations are performed use registers A and B as both source and
destination addresses for the operations. The unsigned number in register A is multiplied by the
unsigned number in register B as indicated:
MUL AB: multiply A by B, put the lower byte of the product in A, and put the high order byte in B.
The OV flag is set if A x B >FFH. This indicates the number is larger than 8 bits and the user needs
to inspect register B for the high order byte of the multiplication operation.
NOTE: There is no comma between A and B in the MUL mnemonic.
Division: - Division operations use registers A and B as both source and destination addresses for the
operation. The unsigned number in register A is divides by the unsigned number in register B as
indicated:
DIV AB: Divide A by B, put the integer part of quotient in register A and the integer part of the
remainder in B.
The OV flag is cleared to 0 unless B holds 00H before the DIV. Then the OV flag is set to 1 to show
division by 0. The carry flag is always reset.
NOTE: The original contents of A and B are lost. There is no comma between A and B in the DIV
mnemonic.
Jump Program Range: - A jump instruction can replace the contents of the program counter with a
new address number that causes program execution to begin at the code located at the new address.
The difference of bytes of this new address from the address in the program in the program where the
Jump is called the range of the jump.
It may have three ranges:
 Relative range: Jumps that

replace the PC contents with a new address that is greater than the address of the instruction
following the jump by the 127D or less than the address of the instruction following the jump by
128D are called relative jump. They are so named because the address that is placed in the PC is
relative to the address where the jump occurs. If the relative range are needed, then a relative jump
can be done by another relative jump until desired address is reached.
 Short absolute range: -This

makes use of dividing memory into logical divisions called pages. Program memory may be regarded
as one continuous stretch of addresses from 0000H to FFFFH. Absolute range addressing has the
same advantage as relative, fewer bytes are needed and the code is relocated as long as the relocated
code begins at the start of a page.
 Long absolute range:

-Addresses that can access the entire program space from 0000H to FFFFH uses long range
addressing. Long-range addresses require more bytes of code to specify and are relocated only at the
beginning of 64K pages. The program must be reassembled every time a long-range address changes
and these branches are not generally relocatable as the Rom address range is restricted to 64K.
Bit Jumps: - Bit jumps all operate according to the status of the carry flag in the PSW or the status of
any bit-addressable location. All bit jumps are relative to the PC.
Mnemonic Operation
J JC radd J Jump relative if the carry flag is set to 1.
J JNC radd J Jump relative if the carry flag is reset to 0.
JB b,radd J Jump relative if addressable bit is set to 1.
J JNB b, radd J Jump relative if addressable bit is reset to 0.
J JBC b, radd J Jump relative if addressable bit is set and clear the addressable bit to
0 0.
Byte Jumps: - Byte jumps that test bytes of data as bit jumps. If the condition that is tested is true the
jump is taken if the condition is false the instruction after the jump is executed. All byte jumps are
relative to the PC.
Unconditional Jumps: - Unconditional jumps do not test any bit or byte to determine whether the
jump should be taken. The jump is always taken. All jump ranges are found in this group of jumps
and these are only jumps that can jump to any location in memory.
Call and the Stack: - A call causes jump to the address where the called subroutine is located. At the
end of subroutine the program resumes operation at the opcode address following the call. The stack
area of internal Ram is used to automatically store the address, called as return address of the
instruction found immediately after Call.
Calls use short or long range addressing, return have no addressing mode specified but are always
long range.
Mnemonics Operation
ACALL sadd Call the subroutine located on the same page as the address of the opcode I
i immediately following the ACALL instruction; push the address of instruction
immediately after the call on the stack.
LCALL ladd Call the subroutine located anywhere in program memory space push the address
o if the instruction immediately following the call on stack.
RET Pop 2 bytes from the stack into the program counter.
RETI Pop 2 bytes from stack into the program counter and reset the interrupt enable flip
fflop.
The only difference between the RET and RETI instructions is the enabling of the interrupt logic
when RETI is used. RET is used at the end of subroutine called by the opcode. RETI is used by
subroutines called by an interrupt.
PUSH and POP opcodes: - The PUSH and POP opcodes specify the direct address of the data. The
data moves between the area of internal RAM, known as stack and the specified direct address. The
stack pointer SP contains the address from where the data is to be POPed or where the data is to be
PUSHed.
A PUSH instruction copies from the source address to the stack. SP is incremented by 1 before the
data is copied to the RAM location whose address is in SP so that the data is stored from lower
address to the higher address. Excessive PUSHing can make the stack exceed 7F H after which the
data is lost.
A POP copies data from the stack to the destination address. SP is decremented by 1 after data is
copied from the stack RAM address to the direct destination to ensure that data placed on the stack is
retrieved in the same order as it as stored.
Mnemonic Operation
PUSH add I Increment SP; copy the data in add to the internal RAM address contained in the RAM.
POP add Copy the data from the internal RAM address contained in SP to address; decrement the
SSP.
The SP is set to 07 when resetted, which is the same direction address in the internal RAM, as register
R7 in bank 0.
Data Exchanges: - MOV, PUSH, and POP instructions all involve copying the data in the source
address to the destination address, the original data in the source is not altered. Exchange instructions
actually move data in two directions from the source to destination and from destination to source.
All addressing modes except immediate can be used in XCH instructions.
Mnemonic Operation
XCH A, R7 Exchange bytes between register A and register R7
XCH A, 0F0h Exchange bytes between register A and register B.
XCH A, @R1 Exchange bytes between register A and address in R1.
XCHD A, @R1 Exchange lower nibble in A and address in R1.
Note: When using XCHD the upper nibble of A and the upper nibble of the address location in Rp do
not change.

PCI (Peripheral Component Interface): - PCI is 33 MHz fixed frequency bus architecture
capable of transferring data at 132MB/sec as compared to 5MB/sec transfer rate of ISA bus. It has
automatic configuration capabilities for switchless/jumperless peripherals. Auto configuration takes
care of all the address interrupts requests and DMA assignments used by a PCI peripheral. This bus
architecture was developed to give a faster performance to the 32 bit CPU and graphic intensive
operation systems for which the ISA bus performance was no longer satisfactory.
The PCI bus features are: -
1. Data bursting as normal operating mode.
2. Linear Burst Ordering: Linear Burst is a method of transferring data that ensures that the
bus is continuously filled with data. The peripheral device will be accepting data from the
system in a linear manner.
3. Concurrency support. Concurrency is a technique that ensures that the microprocessor
operates simultaneously with these masters without waiting for them.
4. Low Latency guarantees for real time devices. Low access Latency means reducing the
time required for a peripheral to be granted control of bus after requesting access.
5. Support for multiple loads at 33MHz.
6. Error detection and reporting.
7. MultiMaster and peer-peer communication.
8. 32-bit multiplexed and processor independent operation.
9. Synchronous 132 MB/sec operation.
10. Variable length, linear bursting (both read and write).
11. Parity on address, data and command signals.
12. Initialization hooks for auto configuration.
13. 64-bit extension compatible with 32 bits.
14. CMOS drivers, TTL voltage levels.
PCI Express (Peripheral Component Interconnect Express): It isofficially abbreviated as PCIe

(or PCI-E, as it is commonly called), is a computer expansion card standard designed to replace the
older PCI, PCI-X, and AGP standards. Introduced by Intel in 2004, PCIe is the latest standard for
expansion cards that is available on mainstream personal computers
PCI Express is used in consumer, server, and industrial applications, as a motherboard-level
interconnect (to link motherboard-mounted peripherals) and as an expansion card interface for add-
in boards. A key difference between PCIe and earlier buses is a topology based on point-to-point
serial links, rather than a shared parallel bus architecture.
Conceptually, the PCIe bus can be thought of as a high-speed serial replacement of the older
(parallel) PCI/PCI-X bus. At the software-level, PCIe preserves compatibility with PCI; a PCIe
device can be configured and used in legacy applications and operating-systems which have no
direct knowledge of PCIe's newer features. In terms of bus-protocol, PCIe communication is
encapsulated in packets. The work of packetizing and depacketizing data and status-message traffic
is handled by the transaction-layer of the PCIe port (described later.) Radical differences in
electrical-signalling and bus-protocol require the use of a different mechanical form factor and
expansion connectors (and thus, new motherboards and new adapter-boards.)
PCI Express Technology:

PCI Express provides a scalable, high-speed, serial I/O bus that maintains backward compatibility
with PCI applications and drivers. The PCI Express layered architecture supports existing PCI
applications and drivers by maintaining compatibility with the existing PCI load-store (and flat
address space) model. The layered architecture is discussed in the sidebar, "PCI Express Layered
Architecture."
Formerly known as 3GIO, PCI Express is the open standards- based successor to PCI and its
variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on
32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that
found in Gigabit1 Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express
reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point
serial buses.

Features of PCI-Express:
1. Compatibility with the existing PCI enumeration and software device drivers.
2. Physical connection over copper, optical or other physical medium to allow further
encoding schemes.
3. Maximum Bandwidth per pin allows for small form factors, reduced cost, simpler board
designs and routings and reduced signal integrity issues.
4. Embedded clocking scheme enables easy frequency changes as compared to synchronous
clocking.
5. Bandwidth increases easily with frequency and width increases.
6. Low latency suitable for applications requiring isochronous data delivery, such as
streaming video.
7. Power Management capability.
PCI Express has the following advantages over PCI:

• Serial technology providing scalable performance.
• High bandwidth—Initially, 5-80 gigabits per second (Gbps) peak theoretical bandwidth,
depending on the implementation.
• Point-to-point link dedicated to each device, instead of the PCI shared bus.
• Opportunities for lower latency (or delay) in server architectures, because PCI Express
provides a more direct connection to the chip set Northbridge (see Note 2) than PCI-X.
• Small connectors and, in many cases, easier implementation for system designers.
• Advanced features—Quality of service (QoS) via isochronous channels for guaranteed
bandwidth delivery when required, advanced power management, and native hot plug/hot
swap support.
PCI Express will replace the PCI, PCI-X, and AGP parallel buses gradually over the next decade. It
will initially replace buses that need the additional performance or features. For instance, PCI
Express will initially be deployed as a replacement for the AGP8X graphics bus in client systems,
providing high bandwidth and support for multimedia traffic. It will also coexist with and
ultimately replace the PCI-X bus in server systems.
PCI-X Features: PCI-X is a second generation development of the PCI bus that provides faster
speeds as compared to PCI. Its features are:
• Backward compatible with PCI.
• Used in workstation and server installations.
• PCI-X supports 64-bit slots that are compatible with 64-bit and 32-bit PCI cards.
• PCI-X version 1 runs at 133 MHz and PCI-X version 2.0 supports operations up to 533
MHz.
• PCI-X 2.0 bandwidth is subdivided among multiple PCI-X and PCI slots.
Concept Of Cache Memory: Cache memory is a buffer memory between the main memory
and CPU. A CPU’s time is wasted during memory access due to large access time of the main
memory. To minimize the idle time of the CPU a small and fast memory is introduced is
introduced between the main memory and the CPU. A portion of the program is brought into
the cache memory in advance. The MMU keeps track of location of the main memory which is
mapped in cache memory at a given time. When the CPU is in need of an instruction or
operand it gets it from the cache memory instead of accessing the main memory. When an
address accessed by the CPU is not mapped in cache memory then a direct access is made to
the main memory. At the same time the cache memory is updated by the operating system. This
means more locations of main memory are brought into the cache memory. If the cache
memory is full then some existing contents of cache memory are removed in order to create
space for new entry. It is made up of SRAM memory.

Two levels of cache are used in PC:
1. Level 1 Cache (L1/ Internal Cache): L1 type cache resides on the processor itself on the
same chip. L1 cache is always built into the processor die and runs at full-core speed of
processor internally. L1 has 90% hit ratio. It operates with the same speed as the core and
hence improves the system performance.
2. Level 2 Cache (L2/ External Cache): L2 cache resides on the motherboard outside the
processor. This is used whenever an L1 cache miss occurs. As L2 is mounted on the
motherboard it runs at the motherboard speed. L2 has a hit ratio of 90%.
CPU
L1 cache L2 cache Main Secondary

Memory Memory
Level 3 Cache (L3): Processors that were designed for high performance desktop operations or
enterprise server contains a third level of cache known as L3 cache. Very few processors have
integrated L3 cache. It also operates with same speed as L1 and L2 cache. L3 cache was used with
the 1st version of P IV extreme edition processor. Future processors may include L3 cache as a more
standard feature

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Block Diagram of Microprocessor based system and bus architecture: -

• Temporary Registers: - These registers store 8 bit or 16 bit information temporarily

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IO/ S1 S0 Machine cycle

Architecture of 8085: The various blocks in the architecture of 8085 are:

 Address Buffer: When this unit is enabled A15 to A8 are available.

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Block diagram of 8051:

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Pin- Diagram of 8051:

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Pin Alternate Use SFR

TCON Control Word:

Bit addressable as TCON.0 to TCON.7

TMOD control word:

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Pulse I/P TLX 8 Bits TFX Interrupt

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Pulse I/P TL0 8 Bits TF0 Interrupt

SCON Control Word:

SM0 SM1 Mode Description

 SM2: Multiprocessor Communication bit: Set / Cleared by program to enable multiprocessor

 TB8: Transmit bit 8: set / cleared by program in modes 2 & 3.

 RB8: Receive bit 8: set / cleared by program in modes 2 & 3.

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 Serial Data Mode 2: Multimode Mode: -

 SERIAL DATA MODE 3

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Rotate and Swap instructions are related to A register.

 RL A : Rotate the A register one bit position to left.

Incrementing or Decrementing instructions: - The simplest arithmetic operations involve adding or

ADD A, #n Add A and the immediate number n; result in A

The following instructions list the add with Carry:

SUBB A, #n Subtract immediate number n and the C flag from A, result in A

 Relative range: Jumps that

 Short absolute range: -This

 Long absolute range:

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PCI Express (Peripheral Component Interconnect Express): It isofficially abbreviated as PCIe

PCI Express Technology:

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PCI Express has the following advantages over PCI:

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Two levels of cache are used in PC:

L1 cache L2 cache Main Secondary

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