Advanced Computer Architecture (CSE 904)

Home Work 3

Guidelines and Instructions:-

1. Please write answers point-wise as briefly as possible and giving relevant

details only. Highlight (underline) the main points you are emphasizing.

2. Wherever possible use self explanatory diagrams/tables/flowcharts with

proper labeling, no need for explaining diagrams if they are self explanatory.
Preferably, use pencils to draw diagrams.

3. Write the answers on sheets of paper and submit the hand-written copy.

4. Please note that this home work consist of 10 marks (instead of 7

marks).

Total
Marks: [10]

Questions:-

1. Discuss the performance improvement of linear pipelining as compared to

the case when pipelining was not used, w.r.t. following cases:-
[1]

a. n is very large, n: number of processors in pipeline

b. k is very large, k: number of stages in pipeline

2. Given two floating point numbers, A=1.2 X 2 4 and B=8.9 X 26, find the
intermediate results, assuming a 4-stage floating point adder pipeline.
(Refer Figure 3.2 of Textbook or Class Slides)
[1]

3. Assuming two-functional pipeline with following reservation table. Draw a

state diagram (indicating stages, latches and MUX as discussed in class)
for the pipeline and indicate the data flow pattern in the state diagram.
[2]

where

t0, t1, t2, t3, t4, t5 are time slots and S0, S1, S2 are stages of pipeline.
 t0 t1 t2 t3
t4

A B A B
S0
A B A

B AB
S1

S3

4. We are given 5 instructions (each of which can be subdivided into 4 sub-

tasks namely IF, ID, OF and EX). Solve the following:-
[3]

IF: Instruction Fetch; ID: Instruction Decode; OF: Operand Fetch & EX:
Execute

a. Calculate clock period, given time delays of 4 sub-tasks are 20ns,

30ns, 50ns and 40ns; assume latch time delay as 10ns.

b. Calculate average idle time (time during which a stage has

completed its task and is waiting for next set of inputs) for the
pipeline, assume time delays as stated in a.

c. Calculate the speed-up for the pipeline.

d. Draw time space diagram for the pipeline, find number of idle
space-time spans and busy space-time spans. Assume 3
processors.

5. Why is interleaved memory organization required? Memory of size 1K

(number of words) has to be interleaved using 4 memory modules.
Assume memory cycle time as 1.28µs. Compare time taken in case of
default memory organization (no interleaving used), S-access interleaving
and C-access interleaving for following memory requirements:-
[3]

a. Access 4 words at locations starting from 8th to 11th memory

address.
 b. Access 4 words at locations starting from 4th to 7th memory address.

Illustrate your solution with diagrams.