1044

A Software Defined Radio Receiver using the Direct Conversion Principle:

Implementation and Evaluation

Hiroshi Yoshida, Syoji Otaka, Takayuki Kato, and Hiroshi Tsurumi

Mobile Communication Laboratory

Corporate Research & Development Center, Toshiba Corp.
hiroshi7.yoshida@toshiba.co.jp

ABSTRACT - A software defined radio with the analog
stage using the direct conversion principle and the digital
stage using DSP demodulator has been developed. The
developed receiver realizes multi-band characteristic of
1.5 GHz and 1.9 GHz band and broadband characteristic
up to 10 MHz together with demodulation function of
d4-QPSK and GMSK, and overall receiver performance
was confirmed.
INTRODUCTION
Software defined radio (SDR) is one of the
solutions for realizing a multi-mode terminal for mobile
communication[l]. The ideal SDR consists of a
combination of an analog-to-digital ( A D ) or a
digital-to-analog (D/A) converter connected directly to
an antenna and a digital signal processor (DSP)[2].
However, it is as yet difficult to realize high resolution
A/D/A converter or high speed DSP which will be
needed for the ideal SDR for the current mobile
communication application. The first step toward
realization of a practicable SDR is to distribute the
minimum analog components for constructing an analog
stage where received RF signal is down-converted to the
baseband and baseband signal for transmission is
up-converted to RF before A/D or D/A converter. The
analog stage for the practicable SDR is required to have
multi-band and broadband characteristics.
We proposed a flexible receiver architecture for a
handheld SDR for a multi-mode mobile communication
terminal using the direct conversion and the low-IF
principle[3],[4]. This paper presents implementation of
and evaluation results for an SDR utilizing the proposed
architecture.
SOFTWARE DEFINED RADIO ARCHITECTURE
FOR REALIZING MULTI-MODE TERMINAL
The SDR can increase flexibility of a radio terminal.
O-fj803-6465-5/00 $10.00 Q 2000 E E E
For the multi-mode terminal application using the SDR
technique, it is desirable to convert broadband RF signal
including desired channel to baseband with single
broadband analog stage. In this procedure, broadband RF
signals are fed to the high speed A/D converter and then
the desired channel signal is selected by the
programmable digital filter. Therefore, demodulation for
the signals with various bandwidths, transmission rates
and modulation schemes can be processed programmably.
The analog stage for this procedure is required to
down-convert the entire bandwidth of various mobile
standards with different frequency band to the baseband;
therefore, the following characteristics are needed for the
analog stage.
(1) Multi-band characteristic for down-converting
various frequency band signals to the baseband
(2) Broadband Characteristic for down-converting
entire system channels to the baseband
The direct conversion principle is inherently
equipped with the multi-band characteristic, because
unlike the heterodyne principle it does not require
passive filters and band-limited components in RF and IF
stages. Therefore, this principle has attracted attention in
recent years as a possible means of achieving RF stage
for multi-band terminal[5]. Furthermore, adopting the
direct conversion principle, the entire channel bandwidth
including desired channels can be down-converted to the
baseband by an analog quadrature demodulator with
frequency-fixed local oscillator prepared for each band.
However, in this case, care needs to be exercised as the
corresponding image signals exist inside the system band.
We have introduced the image cancellation technique[6]
for digitized baseband IQ signals including
multi-channels[3],[4]. The image rejection with only
phase cancellation between IQ channels has been limited
to around 40 dB because of insufficient balance in phase
and amplitude between IQ mixers in the analog
quadrature demodulator, although the image rejection
ratio of more than 70 dB is required to meet the
 1045
specification of receiver chain for the mobile
communication standard. We proposed an alternative
structure as shown in Fig. 1.[3],[4]. In this architecture, a
band-pass filter (BPF), which is not required for the
direct conversion, is inserted in the top of the receiver
front-end for broadband signal selection. The first local
frequency is fixed at a few megahertz lower (or few
megahertz higher) than the lowest (or highest) frequency
of the system band of interest so as to eliminate image
signals with the BPF of the order of 30 to 40 dB.
Therefore, overall image rejection ratio of 70 to 80 dB
can be achieved. This mechanism is considered to
resemble the well-known “low-IF‘’ topology[6]. However,
the proposed architecture is basically different from the
well-known ”low-IF” where the desired signal is detected
by frequency-fixed analog filter. In the following section,
the experimental SDR with the low-IF architecture is
described.
CONFIGURATION OF DEVELOPED SDR
A photograph of the developed SDR is shown in Fig.
2. Fig. 3 shows the detailed block diagram of the SDR,
which consists of the following five boards in VME
chassis and a notebook PC.
A. RFboard
B. Sampling board
C. DSPboard
D. CPUboard
E. RF control board
A. RFboard
The RF board consists of BPFs subsequent to the
antenna for the image suppression, the quadrature
demodulator, two LPFs for anti-aliasing, and frequency
synthesizers to supply local signals to the quadrature
demodulator.
Image suppression BPFs are provided for 1.5 or
1.9 GHz band which are switched according to the
required system band. The passband widths of the
BPFs are 25 MHz for 1.5 GHz[7] and 27 MHz for
1.9 GHz[8].
Quadrature demodulator consists of a harmonic
mixer fabricated with BiCMOS process[9].
LPFs are passive filters designed using discrete
LCRs with 5 MHz of cutoff frequency.
Synthesizers are provided for 1.5 GHz and 1.9 GHz
band which are switched according to the required
system band.
B. Sampling board
The sampling board consists of two AID converters,
two digital quadrature demodulators, four decimation
filters and four FIR filters with 256 taps [lo]. The A/D
converters of 64MHz with 12-bit resolution[ 113 are
utilized for digitizing the signals for IQ channels. The
quadrature demodulators, the decimation filters and the
FIR filters are realized with programmable hardware[ 121.
Although the FIR filters should be inserted following the
complex adder as shown in Fig. 1 for minimizing the
circuit complexity, they are inserted between digital
quadrature demodulators and the complex adder because
of a limitation of the hardware. Digitized signals for I
and Q channels are fed into two quadrature demodulators,
and are down-converted into the baseband signals by
NCOs with the center frequency of the desired signal.
Four baseband signals from the quadrature demodulators,
“II”, “IQ’ for the I-channel and “QI“, “QQ” for the
Q-channel, are converted into 8 times the symbol rate of
the desired signal with the decimation filters, and then
filtered with the FIR filters for channel selection, and are
output to the DSP board.
C. DSPboard
The DSP board consists of three fixed-point DSPs
of 166 MHz, 32-bit[13] and STAG (Joint Test Action
Group) interface for downloading software from the
notebook PC.
The flow of the signals is shown in Fig. 4. The “II”,
“IQ’ signals and the “QI”, “QQ’ signals from FIR filters
are input into DSP-A and DSP-B through the buffer
memory, respectively. DSP-B outputs the received
signals into DSP-A through the inter-DSP memory. As
shown in Fig. 5, most demodulation processes are
performed in DSP-A. First, in the image rejection
process, the “11”, “IQ’ signals and the “QI”, “QQ’
signals are complex-operated to cancel the image signals,
and thus desired IQ channels are extracted. Next, the
clock recovery process selects an optimal sampling point
for signal detection, and thus de-mapping process
together with differential decoding process recovers the
original data sequence.
DSP-C continuously monitors the global shared
memory, and sets parameters for the sampling board such
 1046

as frequency of NCO, decimation rate and FIR filter tap application. They are considered to be degraded by the
coefficients when the global shared memory is imbalance of amplitude and phase in IQ mixers and also
overwritten by the control command from the notebook imperfection in layout pattern of the quadrature
PC. demodulator. Therefore, further improvement in IQ
balance of the quadrature demodulator over broadband
D, CPUboard (e.g. around 10 MHz) will be necessary in order to adopt
this architecture for the mobile communication
The CPU board consists of a 32-bit CPU and application in which strict specification for image
peripherals such as HDD, FDD, Ethernet interface and rejection (i.e. 70 dB) will be required.
VME bus interface[l4]. The setting parameters for the
RF board are sent out to the RF control board via VME Finally, overall receiver performance was confirmed
bus. by receiving the three channels listed in Table 2 with
digital stage whose parameters are shown in Table 3
E. RF control board where NCO frequency was set to IF (i.e. 2.5MHz). The
parameters shown in Table 4 were set for each channel.
The RF control board consists of PLD
(Programmable Logic Device) for VME bus control and Table 2. Transmission parameters
other peripheral LSIs. Parameters from CPU board are
converted into the control signals of the RF board, and Carrier Modulation Transmission
are output to the RF board via flat cable in the front Frequency Scheme Rate .
panel. CH 1 1572.5MHz d4-QPSK 42kbps
CH2 1886.OMHz GMSK 270.833kbps
EVALUATION RESULTS CH 3 1916.OMHz d4-OPSK 384kb~s
~ ~ ~ ~~~~~

Specifications of the developed SDR are shown in
Table 1.
Table 1. Specificationsof the developed SDR
RF Band 1.5 / 1.9 GHz
Bandwidth 10 MHz
Modulation Scheme n-PSK, d4-QPSK, GMSK,
MSK
Transmission Rate Max. 384kbps
Differential Encoding ON / OFF
The measurement result for passband characteristic
of the SDR is shown in Fig. 6 where center frequency is
DC. The result shows that 3 dB bandwidth of 10 MHz is
achieved in I .5 GHz and 1.9 GHz bands.
Next, the measurement results for amplitude error
and phase error in IQ channels are shown in Fig. 7 and
Fig. 8, respectively. The amplitude error of less than 0.5
dB and phase error of less than f 6 " over 5 MHz, and
1.4 dB and +9" over 10 MHz are achieved. The image
rejection ratios calculated from these values are 24 dB
over 5 MHz and 19 dB over 10 MHz. The resultant
image rejection values are not sufficient for practical
Table 3. Parameters in digital stage (1)
NCO Frequency 2.5MHz
A/D Converter Conversion Rate 64MHz
DSP Clock Frequency 166MHz
Tap Number of FIR Filters 128
The sampling clock of the A/D converters was not
an integer multiple of the symbol rate for each channel in
Table 4; therefore, the decimation rate closest to 8 times
the symbol rate was chosen to realize reasonable bit error
rate. The digitized signals with sample rate of Table 4 are
input into the DSP board. The constellations and eye
diagrams of the image canceled baseband signals are
shown in Fig. 9 and Fig. 10 where each signal is selected
by digital channel selection filters programmatically
according to the modulation scheme and bandwidth for
each channel.
CONCLUSIONS
The multi-band and broadband SDR for multi-mode
mobile communication terminal using direct conversion
and the low-IF principle has been developed. The
developed SDR receiver realizes multi-band
 1047

characteristic of 1.5 GHz and 1.9 GHz band and Architecture for Multistandard Compatible Radio
broadband characteristic of up to 10 MHz together with Systems. Girafe Project," Proc. 46th IEEE VTC, vol.
demodulation function of d4-QPSK and GMSK, and 2, pp. 1052-1056, 1996.
overall receiver performance has been confirmed. [6] P. R. Gray and R. G. Meyer, "Future Directions of
Further improvement is required respecting the IQ Silicon IC's for RF Personal Communications,"
balance of the quadrature demodulator in order to CICC '95, pp. 368-369, 1995.
increase image cancel ratio. The evaluation of the [7] Murata Manufacturing Co., Ltd., "Murata
complete transceiver with transmitter chain is also a Products," pp. 4 5 4 8 , 1998.
subject for future work. [81 Murata Manufacturing Co., Ltd., "Murata
Products," pp. 52-55, 1998.
Table 4. Parameters in digital stage (2) P I T. Yamaji, H. Tanimoto, and H. Kokatsu, "An VQ
Active Balanced Harmonic Mixer with IM2
Baseband Filter
Decimation FIR Filter Cancelers and a 45" Phase Shifter," IEEE Journal of
Rate SamDling Rate Solid-state Circuits, Vol. 33, no. 12, pp.
CH 1 Root Nyquist 384 167ksps 2240-2246,1998.
(~0.5) [IO1 Pentek, Inc., "Pentek Model 6210 Operating
CH2 Gaussian 30 2.13Msps Manual," 1998.
(B~x0.3) [I11 Analog Devices, Inc., "AD6640 Datasheets," 1998.
CH 3 Root Nyquist 42 1 S2Msps 1121 Harris Semiconductor, "HSP502 14B Datasheets,"
(~0.5) 1998.
~ 3 Pentek,
1 Inc., "Pentek Model 4290 Operating
Local Modulation Transmission Manual," 1998.
Frequency Scheme Rate c 141 SBS Technologies, Inc., "V5B Technical Manual,"
CH 1 1570.OMHz d4-QPSK 42kbps 1997.
CH2 1883.5MHz GMSK 270.833kbps ,
A
Dtgml quadrature
demodulator

CH 3 1913.5MHz d4-QPSK 384kbps

Ay -,*
REFERENCES (Variable frequency)

J. Mitola, "The Software Radio Architecture," IEEE

Communications Magazine, vol. 33 No. 5 , pp. 4 I c
Analog stage Digital stage
26-38, 1995.
J. Mitola, "Software Radios Survey, Critical Fig. 1: Configuration of low-IF receiver
Evaluation and Future Directions," IEEE AES
Systems Magazine, vol. 8 No. 4, pp. 25-36, 1993.
H. Yoshida, H. Tsurumi, and Y. Suzuki, "Broadband
RF Front-end and Software Execution Procedure in
Software-defined Radio," Proc. IEEE VTC
1999-Fall, vol. 4, pp. 2133-2137, 1999.
H. Tsurumi, H. Yoshida, S. Otaka, H. Tanimoto, and
Y. Suzuki, "Broadband and Flexible Receiver
Architecture for Software Defined Radio Terminal
Using Direct Conversion and Low-IF Principle,"
Special Issue on Software Radio IEICE Trans.
Commun., vol. E83-B, no. 6, pp. 1246-1253,
2000.
CPU Board
/ RF Board
\ DSP Board and
Sampling Board
A. Fernandez-Duran, T. Sanjuan, J. Sevenhans, J. RF Control Board

Dulongpont, J. M. Parez, J. Casajus, J. Barrett, T.

Fig. 2: Developed SDR
Roste, and G. Fletcher, "Zero-IF Receiver
 1048

mslaoe j OQ&4 Sase 10

,......... ................... , _ . _ _ ~ ~ _ _ ~ ~ _c--_--__-._-.__-__--
: RF board W.tUR
j ;Smpfing board
,I
~~__.~_~_________
j:DSPhrd (o1.5GHzjI

. . . . . . . . . . . . . . . . . .

.......-...........
............
I-__-_ S I
_ _ _ _ _ _ _ _ _ _ _ . I

: CPU board ::notebodc pc : y y C ? N - O - N " - r u l

h e t Frequency [MHz]
Fig. 3: Detailed block diagram of developed SDR
Fig. 8: Phase error in the analog stage
From FIR tiller

Inter-DSP

0
Memory
From FIR filler Global
shared Conlrd command
Buffer DSP-B
From notebook PC

Monitoring
Parameter setting of
the sampling board 6,,ffer
DSP-C

. . . . . . . . . . . . . . . . . . .
Fig. 4: Signal flow in DSP board
d4-QPSK GMSK
Fig. 9: Constellation of demodulated signal

Fig. 5: Detailed processes in DSP-A

9
- lOMHz
c

d -25

-30
34-QPSK

Fig. 6: Bandwidth of the analog stage

GMSK
0
U
""""""""""""""""""""'
? P C ? N - O - N m " m
6ffset'Frequency [MHz] Fig. 10: Eye diagram of the demodulated signal

Fig. 7: Amplitude error of the analog stage