Tnetc 4401

TNETC4401
Cable Broadband
Controller Data Manual
Version 1.2
ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Version 1.2 – April 2003 SPRS201 i

TNETC4401 Cable Broadband Controller Data Manual
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Copyright © 2003, Texas Instruments Incorporated
ii SPRS201 Version 1.2 – April 2003

Table of Contents
Table of Contents
Chapter 1: Introduction.........................................................................................................1-1
1.1 Features ......................................................................................................................................................1-1
Chapter 2: Description ..........................................................................................................2-1

2.1 Functional Block Diagram.........................................................................................................................2-2
Chapter 3: Memory Map........................................................................................................3-1
Chapter 4: Functional Overview...........................................................................................4-1

4.1 MIPS Processor..........................................................................................................................................4-1
4.1.1 I Stage (Instruction Fetch) ..............................................................................................................4-3
4.1.2 E Stage (Execution) .......................................................................................................................4-3
4.1.3 M Stage (Memory Fetch)................................................................................................................4-3
4.1.4 A Stage (Align) ...............................................................................................................................4-4
4.1.5 Writeback (W Stage) ......................................................................................................................4-4
4.2 Peripheral Modules....................................................................................................................................4-4
4.2.1 External Memory Controller (EMIF) ...............................................................................................4-4
4.2.2 Interrupt Controller (INTC)..............................................................................................................4-5
4.2.3 General-purpose I/O (GPIO) ..........................................................................................................4-5
4.2.4 Timers (TIMER) ..............................................................................................................................4-6
4.2.5 Universal Async Receiver/Transmitter 16C550 (UART) ................................................................4-6
2
4.2.6 I C Interface (I2C)...........................................................................................................................4-6
4.3 Clock Control (CLKC) ................................................................................................................................4-6
4.4 Reset Control (RSTC) ................................................................................................................................4-6
4.5 DOCSIS 2.0 Subsystem .............................................................................................................................4-7
4.6 10/100 Base-T Ethernet Interface Module (EMAC)..................................................................................4-7
4.7 Flexible USB Function Controller (USBS) ...............................................................................................4-8
4.8 VLYNQ Interface.........................................................................................................................................4-8
4.9 PCM Clock for Voice Applications ...........................................................................................................4-8
4.10 DES Module (DES) .....................................................................................................................................4-8
4.11 General-purpose DMA Engine (DMA) ......................................................................................................4-9
4.12 Test Ports (E/JTAG) ...................................................................................................................................4-9
Version 1.2 – April 2003 SPRS201 iii

Chapter 5: Clock Management............................................................................................. 5-1

5.1 Input Clock .................................................................................................................................................5-2
5.2 DOCSIS Clock Tree....................................................................................................................................5-2
5.3 MIPS Clock .................................................................................................................................................5-2
5.4 VBUS Clock ................................................................................................................................................5-2
5.5 USB Clock...................................................................................................................................................5-2
5.6 Ethernet PHY Clock ...................................................................................................................................5-2
5.7 VLYNQ Clock..............................................................................................................................................5-2
5.8 PCM Clock ..................................................................................................................................................5-2
Chapter 6: Power Management............................................................................................ 6-1

6.1 Idle Mode (MIPS Low-power Mode)..........................................................................................................6-1
6.2 Standby Mode ............................................................................................................................................6-1
6.3 Halt Mode....................................................................................................................................................6-1
6.4 Peripherals Low-power Modes.................................................................................................................6-1
Chapter 7: Initialization ........................................................................................................ 7-1

7.1 Hardware Logic Reset ...............................................................................................................................7-1
7.2 Boot-mode Pins .........................................................................................................................................7-2
7.3 Boot Modes Supported in the ROM Code ...............................................................................................7-3
7.3.1 Boot from CS0 (BOOTS = 001) .....................................................................................................7-3
2
7.3.4 Boot from E PROM (BOOTS = 100, 101) ......................................................................................7-4
7.3.5 Boot from VLYNQ (BOOTS = 111) ................................................................................................7-4
Chapter 8: Terminal Descriptions........................................................................................ 8-1

8.1 Terminal Descriptions by Interface..........................................................................................................8-1
8.2 Pinout by Terminal Number......................................................................................................................8-7
Chapter 9: Electrical Specifications .................................................................................... 9-1

9.1 Operating Conditions and Device Electrical Characteristics................................................................9-1
9.2 Analog Electrical Characteristics over Recommended Operating Conditions...................................9-3
9.2.1 US DOCSIS Application.................................................................................................................9-3
9.2.2 EuroDOCSIS Application ...............................................................................................................9-4
Chapter 10: System Design Considerations..................................................................... 10-1

10.1 Crystal Oscillator .....................................................................................................................................10-1
10.2 Power Pin Summary ................................................................................................................................10-2
10.3 Analog.......................................................................................................................................................10-3
10.3.1 DAC..............................................................................................................................................10-3
10.3.2 ADC..............................................................................................................................................10-4
10.3.3 Band Gap .....................................................................................................................................10-4
10.4 AGC Connections and Functions ..........................................................................................................10-5
10.5 Layout Recommendations......................................................................................................................10-5
iv SPRS201 Version 1.2 – April 2003

Table of Contents
Chapter 11: Switching Characteristics ..............................................................................11-1

11.1 JTAG TEST Interface ...............................................................................................................................11-1
11.1.1 Timing Requirements ...................................................................................................................11-1
11.1.2 Switching Characteristics over Recommended Operating Conditions.........................................11-1
11.2 EJTAG Interface .......................................................................................................................................11-2
11.3 Ethernet Interface ....................................................................................................................................11-3
11.3.1 Switching Characteristics over Recommended Operating Conditions.........................................11-4
11.4 USB Interface............................................................................................................................................11-5
2
11.5 I C Master Interface..................................................................................................................................11-7
11.6 VLYNQ Interface.......................................................................................................................................11-8
11.7 External Memory Interface ......................................................................................................................11-9
Chapter 12: Parameter Measurement Information............................................................12-1

12.1 Signal Transition Levels..........................................................................................................................12-1
Chapter 13: Mechanical Data..............................................................................................13-1
Version 1.2 – April 2003 SPRS201 v

List of Figures
Figure 2-1. TNETC4401 Functional Block Diagram ......................................................................................................2-2
Figure 4-1. 4Kc Core Block Diagram ...............................................................................................................................4-2
Figure 4-2. 4Kc Core Pipeline...........................................................................................................................................4-3
Figure 4-3. Minimum Timing Requirements for External Interrupts ............................................................................4-5
Figure 5-1. Clock Management Module ..........................................................................................................................5-1
Figure 10-1. Crystal Oscillator ..........................................................................................................................................10-1
Figure 10-2. DAC Output Circuits.....................................................................................................................................10-3
Figure 10-3. ADC Circuits..................................................................................................................................................10-4
Figure 10-4. AGC Control Line Filtration Stage .............................................................................................................10-5
Figure 11-1. JTAG TEST ...................................................................................................................................................11-1
Figure 11-2. EJTAG Test...................................................................................................................................................11-2
Figure 11-3. MII_RX Port...................................................................................................................................................11-3
Figure 11-4. MII_TX Port ...................................................................................................................................................11-4
Figure 11-5. MII_DIO Data Input Port..............................................................................................................................11-4
Figure 11-6. MII_DIO Data Output Port...........................................................................................................................11-5
Figure 11-7. USB I/O Timing Requirements ...................................................................................................................11-5
Figure 11-8. USB I/O..........................................................................................................................................................11-6
Figure 11-9. IIC_SCL and IIC_SDA .................................................................................................................................11-7
Figure 11-10. Acknowledge ............................................................................................................................................11-7
Figure 11-11. Start and Stop Condition ........................................................................................................................11-8
Figure 11-12. VLYNQ Timing .........................................................................................................................................11-8
Figure 11-13. Synchronous DRAM Read .....................................................................................................................11-9
Figure 11-14. Synchronous DRAM Write ...................................................................................................................11-10
Figure 11-15. Asynchronous Memory Read (No Wait).............................................................................................11-11
Figure 11-16. Asynchronous Memory Read (Wait)...................................................................................................11-12
Figure 11-17. Asynchronous Memory Write (No Wait) .............................................................................................11-13
Figure 11-18. Asynchronous Memory Write (Wait) ...................................................................................................11-14
Figure 12-1. Tester-Pin Electronics..................................................................................................................................12-1
Figure 12-2. Input and Output Voltage Reference Levels for Timing Measurements ..............................................12-1
Figure 13-1. Mechanical Package Diagram....................................................................................................................13-1
vi SPRS201 Version 1.2 – April 2003

List of Tables
List of Tables
Table 3-1. Memory Map................................................................................................................................................... 3-1
Table 7-1. Boot-Mode Settings ....................................................................................................................................... 7-2
Table 8-1. Terminal Descriptions by Interface.............................................................................................................. 8-1
Table 8-2. Pinout by Terminal Number ......................................................................................................................... 8-7
Table 9-1. TNETC4401 Absolute Maximum Ratings over Operating Case Temperature Range
†
(unless otherwise noted) ............................................................................................................................. 9-1
Table 9-2. Recommended Operating Conditions ........................................................................................................ 9-2
Table 9-3. Electrical Characteristics over Recommended Range of Supply Voltage and Operating
Case Temperature Range for USB Terminals USBDM and USBDP (unless otherwise
noted)............................................................................................................................................................... 9-2
Table 9-4. Electrical Characteristics over Recommended Range of Supply Voltage and Operating
Case Temperature (unless otherwise noted) ............................................................................................ 9-2
Table 9-5. Crystal Electrical Characteristics over Recommended Operating Conditions...................................... 9-2
Table 9-6. US DOCSIS Settings .................................................................................................................................... 9-3
Table 9-7. DAC Specifications, with US DOCSIS Configuration ............................................................................... 9-3
Table 9-8. ADC Specifications, with US DOCSIS Configuration ............................................................................... 9-4
Table 9-9. EuroDOCSIS Settings................................................................................................................................... 9-4
Table 9-10. DAC Specifications, with EuroDOCSIS Configuration ............................................................................. 9-5
Table 9-11. ADC Specifications, with EuroDOCSIS Configuration ............................................................................. 9-5
Table 10-1. Matching Values from US DAC, per Application..................................................................................... 10-3
Table 10-2. Matching Values to D/S ADC, per Application ........................................................................................ 10-4
Table 11-1. JTAG Test..................................................................................................................................................... 11-1
Table 11-2. JTAG Test..................................................................................................................................................... 11-1
Table 11-3. EJTAG Timing Requirements .................................................................................................................... 11-2
Table 11-4. EJTAG Test – Switching Characteristics over Recommended Operating Conditions ...................... 11-2
Table 11-5. RX Timing Requirements ........................................................................................................................... 11-3
Table 11-6. TX Timing Requirements............................................................................................................................ 11-4
Table 11-7. TX Port – Switching Characteristics over Recommended Operating Conditions .............................. 11-4
Table 11-8. MII_DIO Data Input Port ............................................................................................................................. 11-4
Table 11-9. MII_DIO Data Output Port .......................................................................................................................... 11-5
Table 11-10. USB I/O Timing Requirements .................................................................................................................. 11-5
Table 11-11. USB I/O – Switching Characteristics over Recommended Operating Free-Air
Temperature Range (Full Speed).............................................................................................................. 11-6
2
Table 11-12. I C Master – Switching Characteristics over Recommended Operating Conditions ......................... 11-7
Table 11-13. VLYNQ Timing Parameters........................................................................................................................ 11-8
Table 11-14. Synchronous DRAM Read – Switching Characteristics over Recommended Operating
Conditions ..................................................................................................................................................... 11-9
Table 11-15. Synchronous DRAM Write – Switching Characteristics over Recommended Operating
Conditions ................................................................................................................................................... 11-10
Table 11-16. Asynchronous Memory Read (No Wait)................................................................................................. 11-11
Table 11-17. Asynchronous Memory Read (Wait)....................................................................................................... 11-12
Table 11-18. Asynchronous Memory Write (No Wait) ................................................................................................. 11-13
Table 11-19. Asynchronous Memory Write (Wait) ....................................................................................................... 11-14
Version 1.2 – April 2003 SPRS201 vii

Revision History
The following major changes were made from Revision 1.1:
Section Description
Chapter 7, Boot option pins require pull-up/down resistors of 4.7 KΩ when
Initialization, DEFAULT mode is not selected.
Section 7.2
Chapter 9, The specification data were updated.
Electrical
Specifications
Sections 9.1 and
9.2
Chapter 10, The RSTEXT resistor value was changed from 20 KΩ to 19.1 KΩ.
System Design
Considerations,
Section 10.3.3
Chapter 11, The timing specifications were updated.
Switching
Characteristics
viii SPRS201 Version 1.2 – April 2003

Chapter 1
Introduction
1.1 Features
•= MIPS Processor •= 10/100 Base-T Ethernet Interface Module

125Mhz Jade 4Kc Core (32 Bit RISC Memory-mapped Interface for Configuration
Processor, MIPS R4000 Core) Ring Buffer Chaining (DMA Master)
MIPS 32 Instruction Set RX and TX Status Reporting
16KB 4-way Set-Associative I-Cache 10- and 100-Mbps Data Rate
16KB 4-way Set-Associative D-Cache Internal and External Loopback
Programmable Memory Management Unit IEEE802.3/Ethernet MAC with MII Interface
(MMU) Address Filtering (Unicast, Multicast,
•= 4KB General-purpose SRAM Broadcast or promiscuous mode)
•= 8 KB Boot ROM Supports Management Interface
Boot from FLASH Two Terminal Standard Management
Interface (MDCLK/MDIO)
Boot from SRAM
Boot from EEPROM •= Flexible USB Function
Boot from VLYNQ USB 1.1 Compliant
Support for BULK and INTERRUPT
•= DOCSIS Subsystem
Endpoints
DOCSIS 2.0 MAC
Support for CONTROL Endpoint 0
DOCSIS 2.0 PHY, Digital and Analog Cells
•= VLYNQ Interface
Full support of DOCSIS 1.x
High-Speed Point-to-Point Serial Interface
DMA Capabilities for Direct Connection to Devices with
•= External Memory Interface (EMIF) VLYNQ Interface
Four Configurable Chip-Selects to Support Programmable 5-pin (two transmit, two
External SDRAM, SRAM, FLASH, and ROM receive and one clock) or 3-pin (one
Supports 16-bit SDRAM Interface transmit, one receive and one clock)
Interface
Supports Glueless Interface to TI Standard
DSPs through HPI Memory-mapped Master/Slave
Supports 8/16-bit Interface for SRAM, Flash, 125-MHz Clock Rate
and ROM Hardware Flow Control
Internal Loopback Mode
Version 1.2 – April 2003 SPRS201 1-1

•= DES Module •= Three 16-bit Timers with 12-bits Pre-scale

Supports DES-ECB, DES-CBC, 3DES-ECB, Two Generic
3DES-CBC
One Watchdog
•= GPIO Module
•= Two 16550 Interface (UART)
28 possible General-purpose I/Os
(dedicated as well as multiplexed with other Hardware Flow Control
functional pins) Programmable Baud Rate Generator
•= PCM Clock for Voice Applications •= Interrupt Controller (INTC)
40 Primary Programmable Priority Interrupts
32 Secondary Interrupts with Fixed Priority
for Low Priority Interrupts and Exceptions
Four External Interrupts (these pins are
configurable as GPIOs)
•= Clock Generator and Controller (CLKC)
•= Reset Controller (RSTC)
2
•= I C Master Interface (I2C)
•= General-purpose DMA Engine
Four Independent DMA Channels
•= Test
EJTAG Interface for MIPS
JTAG TAP Controller for Device Boundary
Scan
1-2 SPRS201 Version 1.2 – April 2003

Chapter 2
Description
The TNETC4401 is a system-on-a-chip, which consists of a Million-Instruction-Per-Second (MIPS) processor and
peripherals designed to serve as a broadband network controller for residential and small-office applications. The
TNETC4401 is the DOCSIS 2.0 enhancement of the TNETC4400, and is based on the TNETC4305 broadband
communications processor and the TNETC4042A integrated cable modem, which enables cable broadband
home access along with various interfaces for making local connections, such as Ethernet, WLAN and USB.

2.1 Functional Block Diagram
SDRAM
FLASH , SRAM
External Memory Controller

VLYNQ
(SDRAM, FLASH , SRAM)
High-speed Crossbar - 125Mhz
DMA
Icache Dcache 125Mhz -
8KB 4KB DMA 62.5Mhz
ROM RAM Engine Bridge
10/100Base-T
Ethernet MAC
MIPS JADE MII
RISC Proccesor
125Mhz
JTAG
Test & Configuration
Flexible
DES Full-Speed USB
Function
Timer
Timer
Power Managment Module
VBUS 62.5Mhz
+ PLLs WDT GPIOs
Interrupt
Controller I2C
UART
UART
PCM Clock
DOCSIS 2.0 PHY
A-TDMA DOCSIS 2.0 MAC DMA
S-CDMA
Figure 2-1. TNETC4401 Functional Block Diagram

Description
The TNETC4401 includes the following modules:

•= 125-MHz RISC processor (MIPS R4000)
•= DOCSIS-2.0-compliant MAC and PHY
•= 10/100-Mbps Ethernet MAC
•= MII Interface (including serial management interface)
•= Flexible USB Function Controller (Integrated PHY)
•= 8 Kbytes on-chip ROM (programmable at manufacturing time)
•= 4 Kbytes on-chip RAM
•= Security module for supporting encryption/decryption, as proposed by the IPSEC specification
•= Four general-purpose DMA channels
•= 28 GPIOs (16 dedicated)
•= Three 16-bit timers (one configured as watchdog)
•= Two 16550 UART modules
2
•= I C module
•= Interrupt Controller
•= Flexible, high-performance external memory controller (EMIF)
•= Supports Glueless Interface to TI Standard DSPs through HPI
•= VLYNQ interface for direct connection to DSPs and other devices with VLYNQ interface


Chapter 3
Memory Map
The following table defines the memory map for the TNETC4401. All addresses are physical addresses.
Table 3-1. Memory Map

Device Start End Allocated Masters That Can
Address Address Size (bytes) Access This Region
Internal SRAM 0000:0000 0000:0FFF 4K MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
Reserved 0000:1000 00FF:FFFF
DOCSIS space 0100:0000 01FF:FFFF 16M MIPS, DMA, VLYNQ
USB Configuration Space 0340:0000 037F:FFFF 4M MIPS, VLYNQ
VLYNQ portal 0400:0000 07FF:FFFF 64M MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
Reserved 0800:0000 085F:FFFF
DES 0860:0000 0860:FFFF 64K MIPS, DMA, VLYNQ
Ethernet MAC 0861:0000 0861:07FF 2K MIPS, VLYNQ
Memory Controller 0861:0800 0861:08FF 256 MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
GPIO 0861:0900 0861:09FF 256 MIPS, DMA, VLYNQ
Clock Control 0861:0A00 0861:0AFF 256 MIPS, VLYNQ
Watchdog Timer 0861:0B00 0861:0BFF 256 MIPS, DMA, VLYNQ
Timer 1 0861:0C00 0861:0CFF 256 MIPS, DMA, VLYNQ
Timer 2 0861:0D00 0861:0DFF 256 MIPS, DMA, VLYNQ
UARTA 0861:0E00 0861:0EFF 256 MIPS, DMA, VLYNQ
UARTB 0861:0F00 0861:0FFF 256 MIPS, DMA, VLYNQ
I2C 0861:1000 0861:10FF 256 MIPS, DMA, VLYNQ
Reserved 0861:1100 0861:11FF 256
USB Slave 0861:1200 0861:12FF 256 MIPS, DMA, VLYNQ
Reserved 0861:1300 0861:13FF 256
DMA 0861:1400 0861:14FF 256 MIPS, VLYNQ
Reserved 0861:1500 0861:15FF 256
Reset Control 0861:1600 0861:16FF 256 MIPS, VLYNQ
BIST Control 0861:1700 0861:17FF 256 MIPS, VLYNQ
VLYNQ Control 0861:1800 0861:18FF 256 MIPS, VLYNQ

Device Start End Allocated Masters That Can

Address Address Size (bytes) Access This Region
Reserved 0861:1900 0861:19FF
Device Configuration Latch 0861:1A00 0861:1AFF 256 MIPS, VLYNQ
Reserved 0861:1B00 0861:23FF
Interrupt Controller 0861:2400 0861:27FF 1K MIPS, VLYNQ
Reserved 0861:3000 0861:37FF 2K
Reserved 0861:2800 0FFF:FFFF
CS0 (Flash) 1000:0000 11FF:FFFF 32M MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
Reserved 1200:0000 13FF:FFFF 32M
CS1 (SDRAM) 1400:0000 1BFF:FFFF 128M MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
CS3 (Asynchronous Memory) 1C00:0000 1CFF:FFFF 16M MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
CS4 (Asynchronous Memory) 1D00:0000 1DFF:FFFF 16M MIPS, EMAC, USB, DOCSIS, DMA, VLYNQ
Reserved 1E00:0000 1FBF:FFFF
Internal ROM 1FC0:0000 1FC0:FFFF 64K MIPS, VLYNQ
Reserved 1FC1:0000 3FFF:FFFF
Reserved 4000:0000 7FFF:FFFF 1G
Note: The master interfaces in the TNETC4401 are as follows:

1. MIPS: MIPS processor master bridge
2. EMAC: EMAC transmit DMA
EMAC receive DMA
3. DMA: General purpose DMA
4. USB: USB function controller master
5. DOCSIS: DOCSIS subsystem master
6. VLYNQ: VLYNQ master

Chapter 4
Functional Overview
This chapter provides a high-level overview of each module in the TNETC4401 design. Detailed descriptions of
each module can be found in the TNETC4400/4401 User’s Guide and TNETC4401 DOCSIS Cable Modem Block
User's Guide.
4.1 MIPS Processor

The 4Kc™ core from MIPS® Technologies is a high-performance, low-power, 32-bit MIPS RISC core. The 4Kc
core operates up to 125 MHz. The 4Kc core implements the MIPS32™ architecture and contains all MIPS II™
instructions, as well as special multiply-accumulate, conditional move, pre-fetch, wait, leading zero/one detect
instructions, and the 32-bit privileged-resource architecture. The R4000®-style memory management unit
contains a three-entry instruction and data transition lookaside buffer (ITLB/DTLB) and a 16-dual-entry joint
transition lookaside buffer (JTLB) with variable page sizes.
The RISC includes a 16KB four-way set-associative instruction cache and a 16KB four-way set-associative data
cache. On a cache miss, loads are blocked only until the first critical word becomes available. The pipeline
resumes execution while the remaining words are being written to the cache. Both caches are virtually indexed
and physically tagged. Virtual indexing allows the cache to be indexed in the same clock that the address is
translated.
An Enhanced JTAG (EJTAG) block allows for single-stepping of the processor, as well as instruction and data
virtual-address breakpoints.

Figure 4-1 shows the block diagram of 4Kc core.
Processor Core
Multiply/Divide Instruction EJTAG

Unit Cache Controller
Bus-Interface Unit
Interface
Memory-
Execution On-Chip
Thin
Management Cache Control
Core Unit Bus(es)
System Transition
Coprocessor Lookaside Data Cache Power
Control Buffer Management
Figure 4-1. 4Kc Core Block Diagram
The core consists of required and optional blocks, as follows:

•= Execution Core
•= Multiply/Divide Unit (MDU)
•= System Coprocessor Control (CP0)
•= Memory Management Unit (MMU)
•= Transition Lookaside Buffer (TLB)
•= Cache Controllers
•= Bus Interface Unit (BIU)
•= Power Management
•= Instruction Cache
•= Data Cache
•= EJTAG Controller
The 4Kc core includes a five-stage pipeline. The pipeline allows the processor to achieve high frequency, while
minimizing device complexity, reducing both cost and power consumption.
The five stages are:

•= Instruction Fetch (I Stage)
•= Execution (E Stage)
•= Memory Fetch (M Stage)
•= Align (A Stage)
•= Writeback (W Stage)

Functional Overview
Figure 4-2 shows the timing diagram of the 4Kc core pipeline.
Stage I E M A W
Bytes
Bytes
I-Cache RegRd ALU Op
I TLB I Dec DAC D-Cache Align RegW
I-A1 I-A2
Bypass
RegW
Bypass
RegW
RegW
Multiply - 16 × 16, 32 × 16
Figure 4-2. 4Kc Core Pipeline
4.1.1 I Stage (Instruction Fetch)

During the instruction fetch stage, an instruction is fetched from the instruction cache.
4.1.2 E Stage (Execution)

During the execution stage:
•= Operands are fetched from the register file.
•= Arithmetic logic unit (ALU) begins the arithmetic or logical operation for register-to-register instructions.
•= ALU calculates the data virtual address for load and store instructions.
•= ALU determines whether the branch condition is true and calculates the virtual branch target address for
branch instructions.
•= Instruction logic selects an instruction address.
•= All multiply and divide operations begin in this stage.
4.1.3 M Stage (Memory Fetch)

During the memory fetch stage:
•= ALU operation completes.
•= Data cache fetch and the data virtual-to-physical address translation are performed for load and store
instructions.
•= Data cache lookup is performed, and a hit/miss determination is made.
•= 16 x 16 or 32 x 16 multiply calculation completes.
•= 32 x 32 multiply operation stalls for one clock in the M stage.
•= Divide operation stalls for a maximum of 34 clocks in the M stage (7, 15, or 23 stall clocks).

4.1.4 A Stage (Align)

During the align stage:
•= Separate aligner aligns load data to its word boundary.
•= 16 x 16 or 32 x 16 multiply operation performs the carry-propagate-add. The actual register writeback is
performed in the W stage.
•= Multiply operation makes the result available for writeback. The actual register writeback is performed in the
W stage.
4.1.5 Writeback (W Stage)

For register-to-register or load instructions, the instruction result is written back to the register file during the W
stage.
The 4Kc core supports three modes of operation: user mode, kernel mode, and debug mode. User mode is most
often used for applications programs. Kernel mode typically is used for handling exceptions and operating-system
kernel functions, including processor management and I/O device accesses. An additional debug mode is used
during system startup and software development.
4.2 Peripheral Modules
4.2.1 External Memory Controller (EMIF)

The external memory controller supports four configurable chip-selects for accessing different types of memories.
It supports access to asynchronous memories such as Flash, ROM, RAM, and also to synchronous memories
(SDRAM). It also supports glueless interface to HPI (Host-Port Interface for TI standard DSPs).
The following table describes the assignment of chip selects to different types of memories:
Table 4-1. Chip-Select Assignments
Memory Port Memory Type

CS0 Flash
CS1 SDRAM
CS3 Asynchronous Memory Bank/HPI
CS4 Asynchronous Memory Bank/HPI
The following parameters can be configured by software for each asynchronous memory:
•= Access waveform timings (wait states etc.)
•= Memory width (8, 16 for ASYNC memories and 16-bit for SDRAM)
The memory controller is limited to support only 16-bit data width for SDRAM and 8-/16-bit widths for
asynchronous memories. It is designed to run at either half the speed of the processor, or at the same speed as
the processor. The rate is selected at boot time via the EA12 address pin.
Note:
The memory controller does not support burst accesses across chip select boundaries.
Application programs must comprehend this and must set the memory buffers' (e.g.
buffers for the DMAs) range within a memory range controlled by a single chip select.

Functional Overview
4.2.2 Interrupt Controller (INTC)

The TNETC4401 supports 40 primary programmable priority interrupts and 32 secondary fixed-priority interrupts.
Each interrupt can be individually masked using the mask interrupt mask registers. The logical OR of the
secondary interrupts is daisy chained with primary interrupts. The secondary interrupts are fixed in priority, with
interrupt0 being the highest and interrupt31 the lowest. Each of the primary interrupts is programmable for the
priority. The interrupt controller provides the interrupt status flag (one bit per interrupt) for both of the interrupt
sets. In addition, the interrupt controller has the Interrupt index register to indicate the highest priority pending
interrupt. For details regarding the interrupt mapping, see the TNETC4400/4401User's Guide.
The TNETC4401 supports four external interrupts. These external interrupts go through two-stage synchronizers.
The external interrupts are programmable to be level sensitive or edge triggered. The polarity also is
programmable (i.e., high or low in case of level sensitive and positive edge or negative edge triggered in case of
edge triggered).
The logical OR of these 40 primary interrupts is connected to the interrupt0 of the CPU. In addition, the internal
CPU timer_out signal is connected back as interrupt5 to the CPU.
1st INT 2nd INT
Level Sensitive - Active High
A B
Level Sensitive - Active Low
A >= 1 VBUS Clock B >= 3 VBUS Clock
1st INT 2nd INT

Falling Edge
A A
Rising Edge
Figure 4-3. Minimum Timing Requirements for External Interrupts
In case of a pulsed-type interrupt (rising/falling edge), the INTH receives only one interrupt for each transition.
The interrupt signal must return to the inactive state before additional interrupts can be generated. In the case of
level-sensitive interrupt, the device receives interrupts continuously as long as the interrupt signal is in the active
state (low for active low and high for active high).
The secondary interrupts/exceptions can be managed similar to primary interrupts, using the registers dedicated
for secondary interrupts/exceptions.
4.2.3 General-purpose I/O (GPIO)

Many functional pins can be used as GPIO pins if the primary function is not desired in the application. Along with
these functional pins, there are 16 dedicated GPIO pins.

4.2.4 Timers (TIMER)

The TNETC4401 implements three 16-bit timers with 13 different pre-scale values. Each timer is configurable in
either ‘auto reload’ or ‘one-shot’ mode and generates interrupts to the MIPS CPU when equal to zero.
The first timer (TIMER0) is configured for use as a watchdog. The two other timers (TIMER1 and TIMER2) are
configured for general-purpose use.
4.2.5 Universal Async Receiver/Transmitter 16C550 (UART)

The TNETC4401 has two UART 16C550 interfaces: One utilizes four pins and the other a two-pin interface. The
UART interface can be used to connect to a PC-based software debugger tool through a standard wired
interface. The UART Module supports data transfer and hardware flow control. It integrates two 16-bit words (8
and 11 bits) and receives and transmits FIFOs with programmable trigger levels. The baud-rate is generated
internally from a programmable divisor. Transmission parity can be even, odd, or without parity, and the number
of stop bits is 1, 1.5, or 2. The character width can be 5, 6, 7, or 8. The receiver can detect break, idle, framing
errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow.
4.2.6 I2C Interface (I2C)

This module implements the serial I2C-bus protocol and supports master-mode operation only.
•= 7-bit device address
•= 8-bit subaddress
•= Master write to slave receiver in single or multiple mode (data loop)
•= 16-byte transmit FIFO
•= Master simple read to slave receiver
•= Read Combined cycle
•= 16-bit programmable SCL clock divider to support a wide range of input clock frequencies. The I2C SCL clock
frequencies are:
12C Standard Mode: 100 kHz
12C Fast Mode: 400 kHz
•= A 3-bit programmable spike filter provides noise filtering on the I2C input signal
4.3 Clock Control (CLKC)

This module is responsible for control of all clock activity on the device. It includes configuration registers for
programming all clock sources and frequencies. This module also controls all clock gating used for
power-management features of the device.
4.4 Reset Control (RSTC)

This module is responsible for control of all reset signals on the device. It includes configuration registers for
global and peripheral resets. Global resets are held asserted internally for 64 system clocks.

Functional Overview
4.5 DOCSIS 2.0 Subsystem

The DOCSIS subsystem is fully compliant with DOCSIS 2.0, and consists of the following components:
•= Downstream QAM receiver

Compliant with ITU-T J.83 Annex A, B, C
Parallel/Serial MPEG-TS interface
Supports 64 and 256 QAM
Blind acquisition within 20 ms typical (TI’s proprietary technology)
•= Upstream QPSK, 8,16,32,64 & 128 QAM transmitter
Programmable pulse-shaping filter
Internal PLL
SinX/X compensation filter
FEC and preamble compliant to DOCSIS
Fully supports both A-TDMA and S-CDMA
•= DOCSIS 2.0 Media Access Controller (MAC)
Fully compliant with DOCSIS 2.0
Privacy hardware compliant with DOCSIS Baseline Privacy/BPI+ specification
Performs concatenation and fragmentation
Supports Unicast and Multicast address filtering
Automatic sync and CRC detection
Automatic packet scheduling
Upstream MAC header generation
Programmable frame processor
Two programmable DMA engines
•= PCM clock extraction for voice applications
4.6 10/100 Base-T Ethernet Interface Module (EMAC)

The EMAC module provides a straightforward and effective method of integrating an IEEE802.3/Ethernet MAC
functionality into a processor I/O subsystem. The EMAC provides:
•= Memory-mapped interface for configuration

•= DMA with ring-buffer chaining
•= RX and TX status reporting
•= 10- and 100-Mbps data rate
•= Internal and external loopback
•= IEEE802.3/Ethernet MAC with MII interface
•= Address filtering (Unicast, Multicast, Broadcast or Promiscuous Mode)
•= MII standard management interface

4.7 Flexible USB Function Controller (USBS)

The USBS module implements a full-speed (12MHz) USB-1.1-compliant function controller. The USB function
includes a 2Kbyte buffer RAM that can be programmed to support up to 8 in and 8 out endpoints.
Data movement from the 2Kbyte buffer can be done via built-in DMA or through programmed I/O.
The following endpoints are supported:
•= BULK OUT endpoint for host write to V-bus address space
•= BULK IN endpoint for host read of V-bus address space
•= BULK OUT endpoint for raw data movement to V-bus space
•= BULK IN endpoint for raw data movement from V-bus space
•= BULK OUT endpoint for continuous write to V-bus address space
•= INT IN endpoint for host interrupts
4.8 VLYNQ Interface

This interface enables the TNETC4401 to connect directly to a C55x DSP for voice applications, or any other
device that uses VLYNQ. The interface consists of either three terminals (clock input, receive data input and
transmit data output) or five terminals (clock input, two receive data inputs and two transmit data outputs) and
runs up to 125 MHz. It also supports flow control in hardware.
The VLYNQ interface can use either an internal or an external clock source. For details, see the
TNETC4400/4401 User's Guide.
4.9 PCM Clock for Voice Applications

The TNETC4401 provides a PCM clock output for use in voice applications. The clock is extracted from the cable
modem termination system, and its rate is configurable to support a variety of industry-standard CODECs. For
more information on the programming of the PCM clock, refer to the TNETC4401 DOCSIS Cable Modem Block
1
User Guide.
4.10 DES Module (DES)

The DES module is designed to efficiently implement the basic building blocks of the developing IP Security
Standard (IPSEC). The same blocks can be used to implement any other security schemes that use the same
blocks. The IPSEC standard defines both encryption/decryption and signing/authentication of IP packets. The
current implementation supports only the encryption/decryption part of the IPSEC standard.
The following encryption/decryption methods are supported:

•= DES-CBC
•= DES-ECB
•= 3DES-CBC
•= 3DES-EBC
1
Texas Instruments Literature Number SPRU571, September 2002

Functional Overview
4.11 General-purpose DMA Engine (DMA)

The TNETC4401 includes one general-purpose DMA engine with four channels designed to improve system
performance. Each DMA channel can be independently configured to move a block of data between any source
and destination address in the TNETC4401 address space. A transfer is initiated by writing the start source
address, the destination address, and the length of the transfer (in 32-bit words, up to 64K). The DMA can be
programmed to issue an interrupt at the end of the transfer or reload the source address, destination address,
and transfer length from reload registers.
4.12 Test Ports (E/JTAG)

This interface is used to support both MIPS CPU emulation and IEEE 1149 Boundary Scan. Two additional pins
are added to support MIPS emulation (TMS2 and DINT) through the EJTAG.
The JTAG interface (TAP) of the chip can be selected either:
1) To access the processor on-chip emulator (EJTAG port) with a pseudo-IEEE JTAG protocol for emulation
purposes.
Or,
2) To dialog with an embedded TAP controller whose instructions set supports all the IEEE 1149 BSCAN
modes, the programming of the chip I/O configuration (PMT modes, full-scan modes, BIST modes,
functional 1 or 2 modes), and the selection of the boundary-scan chain for FLASH EPROM programming.


Chapter 5
Clock Management
The clock management module is shown in Figure 5-1.
VLYNQ clock
VLYNQ
System PLL VBUSP clock

latched at reset
POST VBUS clock

PRE PLL DIV
DIV x1 - x15 by 2
latched at reset
POST
PRE PLL DIV
DIV x1 - x15 by 2 USB PLLs
POST
USB_CLK
PRE PLL DIV
USB clock
latched at reset DIV x1 - x15 by 2 48 MHz
XOSC
Ethernet clock
25 MHz
25 MHz
MAC clock
XTAL_IN DMA clock

clock x2
sync_reset_out
XOSC PLL
x6 / x7
25 MHz (DOCSIS1.1)
28.9 MHZ (EuroDocsis) DOCSIS PHY clock
Clock FECB clock
Control
FECA clock
clock x1 QAM clock
US clock
CPU clock
clock_x6x7
clock x6x7
PCM Clock
10.24 DIV
NCO by 1 to 2^14
Figure 5-1. Clock Management Module

5.1 Input Clock

The TNETC4401 has an analog PLL that is fed by an external crystal. The crystal frequency is 25 MHz for US
DOCSIS, and 28.9 MHz for EuroDOCSIS.
5.2 DOCSIS Clock Tree

The DOCSIS subsystem has its own clock-tree that enables power-down modes.
A PLL multiplies the input frequency by 6 or 7. That basic frequency then is distributed to nine different leaves of
the DOCSIS MAC/PHY.
5.3 MIPS Clock

The MIPS clock is derived from external crystal (XTAL_IN: 25 MHz for DOCSIS1.1 or 28.9 for EuroDOCSIS) or
the USBCLKI. Pin EM_A[9] is latched at reset and selects the clock source for the PLL. The input clock then is
multiplied in a programmable PLL module and divided by a programmable divider. Programming a clock divider in
the range of 1 to 15 can lower the input clock for the MIPS for power-saving modes. The maximum clock rate for
the MIPS core is 125Mhz.
5.4 VBUS Clock

The peripherals get their clock from the VBUS. The VBUS runs at one half the speed of the MIPS clock, i.e.,
MIPS_CLK/2.
5.5 USB Clock

The USB module clock (48 MHz) is generated by dividing the DOCSIS subsystem PLL input clock (i.e., 25 MHz)
and multiplying with the two dedicated PLLs for USB (named USB PLL1 and USBPLL2). For EuroDOCSIS
systems, an additional 25-MHz crystal should be connected to the USBCLKI oscillator, which generates the USB
and Ethernet clock. The register bit in Device Configuration Latch (pin EM_A[8]) selects the clock source for the
PLL.
5.6 Ethernet PHY Clock

The Ethernet PHY must be clocked with a 25Mhz clock. When working in US DOCSIS this clock is taken from the
internal DOCSIS oscillator. However, in EuroDOCSIS mode (when the internal oscillator source is 28.9 MHz), an
additional 25-MHz crystal is needed to generate clock for Ethernet PHY and USB. The Peripheral Clock Control
register selects the clock source for the Ethernet PHY clock. The Ethernet PHY clock is not turned off during the
global power-down modes. The register bit in the Peripheral Power-Down register controls the powerdown for this
clock. The register bit in Device Configuration Latch (pin EM_A[7]) selects the clock source for the PLL.
5.7 VLYNQ Clock

The VLYNQ interface supports auto-detection for external/internal driven clock. If the clock is not found, the
VLYNQ can drive the clock signal out. The VLYNQ module can support clock rates of MIPS_CLK down to 0 MHz.
5.8 PCM Clock

The PCM clock is either the upstream 10.24MHz clock (extracted from the CMTS master clock, using NCO) or
the downstream symbol rate (5 MHz for 64 QAM or 5.36 MHz for 256 QAM), divided by a factor between 1 and
2^14.

Chapter 6
Power Management
The TNETC4401 supports three global power-down modes, as well as peripheral local power-down modes. The
supported global power-down modes are Idle, Stand-By, and Halt modes.
In addition, the system clock frequency can be lowered by setting the clock divider to a value greater than one (up
to 16 times slower).
6.1 Idle Mode (MIPS Low-power Mode)

The device can enter into idle mode by setting the GLPD bits to 01 in the PDCR register. In idle mode, only the
MIPS core is turned off (all peripherals are operating) and is awakened by the first interrupt received from one of
the peripherals. Here, wake-up time is significantly shorter.
6.2 Standby Mode

The device can enter into stand-by mode by setting the GLPD bits to 10 in the PDCR register. In idle mode, the
MIPS core and most of the peripherals are turned off and is awakened by the first interrupt. In this mode, the
DOCSIS subsystem, timers, and PLL operate normally. The wake-up time might be slightly longer than the idle
mode, and is driven mainly by the external SDRAM wake-up sequence.
6.3 Halt Mode

The device can enter into halt mode by setting the GLPD bits to 11 in the PDCR register. In idle mode, the MIPS
core and all the peripherals (including the oscillators) are turned off, and are awakened by the first external
interrupt or reset. The wake-up time may be longer than the other two global power-down modes, as the PLL
needs to be locked.
6.4 Peripherals Low-power Modes

Setting the corresponding bit in the PDCR register can individually shut down the MIPS peripherals. It is the
software's responsibility to power down or wake-up individual peripherals.
Note:
The power-down signals are synchronized to the internal VBUS/MIPS clocks. Hence it is
safer to switch the clock source to the internal clock (for the modules which support
external clock sources) and drive them into low-power mode.


Chapter 7
Initialization
7.1 Hardware Logic Reset

The TNETC4401 receives one external reset signal, RESET_N (active low, PIN 190). When asserted, this signal
initializes the entire device. It is activated each time the power supply is applied to the chip. On power-up, the
RESET_N pin must be held low (asserted) until the power supplies ramp up and to allow time for PLL lock-up
(TBD). While RESET_N is asserted during the power-on reset, the clocks to the system are turned off. When the
power-on reset is de-asserted, the clocks are released to the system and the internal reset is held low for 64
clock cycles to reset all the synchronous logic.
Watchdog reset is asserted whenever the programmable timer times out. A Watchdog reset resets all the internal
peripherals, including the MIPS core.
After reset, the MIPS program counter points to address 1FC0:0000, which is mapped to the internal ROM. The
ROM code should jump to the proper boot location to execute the boot sequence with the internal ROM,
depending on the BOOTS (boot select) setting latched at reset in the BOOT MODE Register.
Note:
Only the BOOTS register is implemented in the hardware to latch the value on the pins at
the rising edge of RESET_N. It is the ROM code's responsibility to implement the boot
from different locations, based on this register value.
In addition to the above global resets, the TNETC4401 supports a programmable reset bit for each peripheral. On
power-up, these bits are held in the reset state, so that all the peripherals are held in the reset state (except the
MIPS core, system infrastructure logic and memory interface module). The MIPS core, system infrastructure logic
and the memory controller logic can be reset via a pulsed reset (64 clock cycles) by writing 1 to the Software
Reset Control register bit 0. The Software Reset Control register bit 1 can be set to issue a reset to the MIPS core
and system infrastructure logic without resetting the external memory controller.

7.2 Boot-mode Pins

Several boot-mode settings can be controlled by latching the values of pins on the rising edge of RESET_N.
Table 7-1 describes the functions controlled in this manner. All pins (EM_A[23:1]) have internal weak
pull-ups/downs so that when choosing either Default mode (US DOCSIS or EuroDOCSIS), no external
pull-ups/downs are needed except for EM_A[6] (US DOCSIS) and EM_A[19] (EuroDOCSIS). Otherwise, external
pull-ups or pull-downs must be placed on these pins to control the appropriate function (4.7KΩ pullup/down
resistors are recommended). The MIPS core can get information on these settings through the BOOTCR register.
Configuration of the TNETC4401 device according to the latched values is implemented in the ROM code.
Table 7-1. Boot-Mode Settings

EuroDOCSIS
Description US DOCSIS
External Pin Function Default:
Default:
Manual Settings: EM_A[6]=0, EM_A[19]=0 EM_A[6] = 1 EM_A[6] = 0,
EM_A[19] = 1
Flash width:
EM_A[23:22] FLSHW[1:0] 00 – 8-bit Flash 01 01
01 – 16-bit Flash
Endian select:
EM_A[21] ENDIAN 0 – Little endian 1 1
1 – Big endian
VLYNQ CLK
0 – VLYNQ_CLK is input
EM_A[20] Default 0 0
1 – VLYNQ_CLK is output
Direction
EURO/MANUAL 0 – Read external manual settings
EM_A[19] - -
Settings 1 – Euro default options
Boot-location selects:
000 – Reserved
001 – Boot from CS0 (Flash)
010 – Boot from CS1 (SDRAM)
EM_A[18:16] BOOTS 011 – Boot from CS3 (Asynchronous Memory) 001 001
100 – Boot from small (up to 2K) EEPROM through I2C
101 – Boot from large (up to 64K) EEPROM through I2C
110 – Reserved
111 – Boot from VLYNQ
0 – PLL mode.
EM_A[15] PLLBYPASS 0 0
1 – PLL is bypassed.
0 – Watchdog timer enabled after reset.
EM_A[14] Wdhe 1 1
1 – Watchdog timer disabled after reset.
0 – Watchdog timer disable bit is writeable.
EM_A[13] Wsdp 0 0
1 – Watchdog timer disable bit is protected.
0 – External memory interface is running at one-half the
speed of the processor.
EM_A[12] EMIF_R 1 1
1 – External memory interface is running at the same
speed of the processor.
0 – External memory controller is in normal mode of
operation.
EM_A[11] EMIF_TEST 1 – External memory controller is in test mode in which the 0 0
initialization sequence is shortened in time to reduce the
test time.
0 – The PLL in the DOCSIS is not bypassed. The output
EM_A[10] DOCNOPLL clock is multiplied clock of input clock. 0 0
1 – The PLL in the DOCSIS is bypassed.

Initialization
EuroDOCSIS
Description US DOCSIS
External Pin Function Default:
Default:
Manual Settings: EM_A[6]=0, EM_A[19]=0 EM_A[6] = 1 EM_A[6] = 0,
EM_A[19] = 1
System PLL input clock select:
0 – The input clock to the System PLL is driven by the
EM_A[9] SYSPLSEL USBCLKI oscillator input. 1 0
1 – The input clock to the System PLL is driven by the
XTAL_IN oscillator input.
USB PLL1 input clock select:
0 – The input clock to the USB PLL is driven by the
EM_A[8] USBPLSEL USBCLKI oscillator input. 1 0
1 – The input clock to the USB PLL is driven by the
XTAL_IN oscillator input.
Ethernet clock select:
0 – The Ethernet clock is driven by the USBCLKI oscillator
EM_A[7] ETHCLKSEL input. 1 0
1 – The Ethernet clock is driven by the XTAL_IN oscillator
input.
0 – Check EM_A[19] to determine whether to use the
EM_A[6] DEFAULT internal predefined EuroDOCSIS default values - -
1 – Use the internal predefined US DOCSIS default values
Power down non-DOCSIS PLLs:
EM_A[5] AV_NOPLL 0 – VCO is turned off. 1 1
1 – VCO is on.
Sampled only when EM_A[15] is 1:
USB0_PLL_BY
EM_A[3] 0 – Don’t bypass USB_PLL_0 0 0
PASS
1 – Bypass USB_PLL_0
Sampled only when EM_A[15] is 1:
USB1_PLL_BY
EM_A[1] 0 – Don’t bypass USB_PLL_1 0 0
PASS
1 – Bypass USB_PLL_1
7.3 Boot Modes Supported in the ROM Code

The on-chip ROM supports the booting from any chip select region. After reset, the ROM code reads the device
configuration latch register to determine which boot mode should be used.
7.3.1 Boot from CS0 (BOOTS = 001)

The program branches to virtual address B000:0000 (Flash).

In this mode, the ROM code checks the reset cause register to determine where to branch program execution. If
the last reset was a SW1 reset (EMIF still configured), program execution branches to virtual address B400:0000
(SDRAM). Otherwise, program execution branches to virtual address B000:0000 (Flash).

The program branches to virtual address BC00:0000 (asynchronous memory).

7.3.4 Boot from E2PROM (BOOTS = 100, 101)

2 2 2
The program loads E PROM code through the I C interface. 100 is used for interfacing small E PROM devices
2
(up to 2K addresses of no more than 11 bits per address), and 101 for larger E PROM devices (up to 64K
addresses of 12 to 16 bits per address).
7.3.5 Boot from VLYNQ (BOOTS = 111)

In this mode, the TNETC4401 enables a remote VLYNQ module to access the VBUS for loading boot code and
configuration.

Chapter 8
Terminal Descriptions
8.1 Terminal Descriptions by Interface

The following table contains a list of the TNETC4401 I/O signals. All output buffers are 8-mA buffers. All input and
I/O signals have internal weak pull-ups/downs that prevent them from floating during chip boot-up or I/O direction
change. However, several input pins, marked as ( ↑=) or ( ↓=), do require external pull-ups/downs.
Table 8-1. Terminal Descriptions by Interface

Terminal Description
Name Direction No.
UART A INTERFACE (four signals)
UARTA_RD/GPIO0 IN/OUT 25 Receive data/GPIO0
UARTA_TD/GPIO1 IN/OUT 26 Transmit data/GPIO1
UARTA_CTS/GPIO3 IN/OUT 27 Clear to send/GPIO3
UARTA_RTS/GPIO2 IN/OUT 28 Request to send/GPIO2
UART B INTERFACE (two signals)
UARTB_RD IN 23 Receive data
UARTB_TD OUT 24 Transmit data
PCM CLOCK (one signal)
PCMCLK/GPIO15 IN/OUT 41 PCM_CLK/GPIO15
EXTERNAL INTERRUPTS (four signals)
EINT0/GPIO16 IN/OUT 183 External interrupt0/GPIO16

Name Direction No.
DEDICATED GPIOS (sixteen signals)
GPIO6 IN/OUT 40 GPIO6
GPIO23 IN/OUT 45 GPIO23.
2
I C (two signals)
IIC_SCL/GPIO5 IN/OUT 49 Serial clock link/GPIO5. ( ↑ ) An external 4.7 KΩ pull-up is needed.
IIC_SDA/GPIO4 IN/OUT 50 Serial clock link/GPIO4. ( ↑ ) An external 4.7 KΩ pull-up is needed.
MII INTERFACE (19 signals)
MII_COL IN 138 MII collision
MII_CRS IN 142 MII carrier sense
MII_TCLK IN 143 MII transmit data clock
MII_RCLK IN 144 MII receive data clock
MII_RD0 IN 148 MII receive data [0]
MII_RDV IN 149 MII receive data valid
MII_RER IN 150 MII receive data error
MII_TEN OUT 154 MII transmit data enable
MII_TD0 OUT 158 MII transmit data [0]
MII_LINK IN 162 MII PHY link status
MII_DIO IN/OUT 163 MI serial-port data
MII_DIOCLK OUT 164 MI serial-port clock
MII_PHYCLK OUT 165 Eth PHY clock source (25 MHz)

Name Direction No.
USB INTERFACE (six signals)
USB XTAL GND 131 Should NOT connect to board GND; instead, connect to USB XTAL capacitors.
USBCLKI IN 133 USB XTAL In
USBCLKO OUT 134 USB XTAL Out
USB_PULLE OUT 135 Pull-up enable
USB_DN IN/OUT 136 Slave differential –
USB_DP IN/OUT 137 Slave differential +
VLYNQ INTERFACE (five signals)
VLYNQ_CLK IN/OUT 125 VLYNQ clock ( ↑ )
VLYNQ_TXD0 OUT 126 VLYNQ transmit data [0]
VLYNQ_TXD1 OUT 129 VLYNQ transmit data [1]
VLYNQ_RXD0 IN 127 VLYNQ receive data [0]
VLYNQ_RXD1/GPIO26 IN/OUT 128 VLYNQ receive data [1]/GPIO26
EXTERNAL MEMORY INTERFACE (54 signals)
EM_CS0_n OUT 57 Chip select (Flash)
EM_CS1_n OUT 116 Chip select (SDRAM)
EM_CS3_n OUT 56 Chip select (asynchronous memory)
EM_CS4_n OUT 55 Chip select (asynchronous memory)
SDRAM_WE_n OUT 121 SDRAM write enable
SDRAM_RAS_n OUT 122 SDRAM RAS
SDRAM_CAS_n OUT 123 SDRAM CAS
EM_WE_SDQM0 OUT 99 Write strobe and data mask for SDRAM
EM_WE_SDQM1 OUT 95 Write strobes and data mask for SDRAM
EM_OE_n OUT 54 Output enable
EM_WAIT_n IN 59 Wait-state extend signal
EM_RNW OUT 60 Read/write signal used in HPI interface
EM_SDCKE1 OUT 119 SDRAM clock enable1
EM_SDCLK OUT 120 SDRAM clock signal

Name Direction No.
EM_A23 OUT 61 Address bus [23] Notes:
EM_A22 OUT 62 Address bus [22] EM_A[23:5,3,1] values from external pull-ups/downs are
latched when RESET_N goes high.
EM_A21 OUT 63 Address bus [21]
Note that although these pins have internal pull-ups/downs,
EM_A20 OUT 64 Address bus [20] they must be connected to external pull-ups/downs of 4.7 KΩ
EM_A19 OUT 65 Address bus [19] when defining the required boot-mode as anything other than
Default.
For more details, refer to section 7.2 in this manual and
EM_A17 OUT 67 Address bus [17] section 1.5 in the TNETC4400/4401 User’s Guide.
EM_D15 IN/OUT 75 Data bus [15]
EM_D0 OUT 94 Data bus [0]

Name Direction No.
DOCSIS INTERFACE (16 signals)
AINP A 2 ADC analog input
AINM A 3 ADC analog input
BGPAD A 9 Test terminal to force band gap to 1.0 V
RSTEXT A 10 Reference resistor for band gap bias current setting
XTAL_OUT A 16 XTAL oscillator connection
XTAL_IN A 18 XTAL oscillator connection
AMPC OUT 173 Upstream amplifier clock
AMPD OUT 174 Upstream amplifier data
AMPE_n OUT 176 Upstream amplifier enable
AMPPD_n OUT 177 Upstream amplifier power-down control
TAGCS OUT 191 Automatic gain control (RF AGC)
AGCS OUT 192 Automatic gain control
ION A 197 DAC current output
IOP A 198 DAC current output
REFP A 204 ADC reference 2 V
REFM A 205 ADC reference 1 V
(E)JTAG PORT (eight signals)
EJTAG_TDI IN 167 Test data input ( ↓=)
EJTAG_TDO OUT 168 Test data output
EJTAG_TMS IN 169 Test mode select ( ↑ )
EJTAG_TCK IN 172 Test clock ( ↓ )
EJTAG_TRST0_n IN 178 Test reset (MIPS JTAG) ( ↓ )
EJTAG_TRST1_n IN 179 Test reset (Chip JTAG) ( ↓ )
EJTAG_DINT IN 180 Debug exception request ( ↓ )
EJTAG_SYS_RESET IN 181 JTAG reset ( ↑ )
MISCELLANEOUS (five signals)
TEST IN 189 Test mode terminal, used to latch test modes from functional terminals (↓ )
RST_n IN 190 Chip power-on reset
EM_HIZ IN 124 EMIF terminals 3-state control ( ↓ )
VPP 186 Should be tied to VDD
FOUT_PLL A 13 PLL clock output for test

Name Direction No.
POWER & GROUND (17 signals)
VDD D Power 21, 37, 52, 68, 84, 97, Core digital 1.5-V supply
104, 117, 130, 140,
152, 160, 170
GND D Power 19, 22, 38, 53, 69, 85, Core digital GND
98, 105, 118, 141,
153, 161, 171, 182
VDDSHV D Power 35, 51, 58, 72, 83, 96, I/O digital 3.3-V supply
106, 132, 139, 151,
159, 166, 175, 187
DAC AVDD A Power 195, 200 DAC analog 3.3-V supply
DAC AGND A Power 196, 199 DAC analog GND
DAC DVDD D Power 194 DAC digital 1.5-V supply
DAC DGND D Power 193 DAC digital GND
ADC AVDD A Power 203, 206, 207, 4 ADC analog 3.3-V supply
ADC AGND A Power 201, 202, 208, 1 ADC analog GND
BG AVDD A Power 7 Band gap analog 3.3-V supply (can be tied with ADC AVDD)
BG AGND A Power 8 Band gap analog GND (can be tied with ADC AGND)
PLL AVDD A Power 11 PLL analog 3.3-V supply
PLL AGND A Power 12,14 PLL analog GND
PLL VDD D Power 5 PLL digital 1.5-V supply
PLL GND D Power 6 PLL digital GND
XTAL VDD D Power 17 XTAL digital 1.5-V supply
XTAL GND D Power 15 XTAL digital GND. Should NOT connect to board GND; instead,
connected to XTAL capacitors. Refer to section 10.1.
LEGEND: (_n) – active low ( ↑ ) – pull-up ( ↓ ) – pull-down

8.2 Pinout by Terminal Number
Table 8-2. Pinout by Terminal Number

Terminal Port Name (Functional) Type Description
No.
1 ADC AGND ADC analog GND
2 AINP A ADC analog input
3 AINM A ADC analog input
4 ADC AVDD ADC analog 3.3-V supply
5 PLL VDD PLL digital 1.5-V supply
6 PLL GND PLL digital GND
7 BG AVDD Band gap analog 3.3-V supply
8 BG AGND Band gap analog GND
9 BGPAD A Test terminal to force band gap to 1.0 V
10 RSTEXT A Reference resistor for band gap bias current setting
11 PLL AVDD PLL analog supply
12 PLL AGND PLL analog GND
13 FOUT_PLL A PLL clock output for test
14 PLL AGND PLL analog GND
15 XTAL GND XTAL digital GND. Should NOT connect to board GND; instead, connect to XTAL
capacitors. Refer to section 10.1.
16 XTAL_OUT A XTAL oscillator connection
17 XTAL VDD XTAL digital 1.5-V supply
18 XTAL_IN A XTAL oscillator connection
19 GND Core digital GND
20 - NC
21 VDD Core digital supply
23 UARTB_RD I UARTB: Receive data
24 UARTB_TD I UARTB: Transmit data
25 UARTA_RD/GPIO0 I/O UARTA: Receive data/GPIO0
26 UARTA_TD/GPIO1 I/O UARTA: Transmit data/GPIO1
27 UARTA_CTS/GPIO3 I/O UARTA: Clear to send/GPIO3
28 UARTA_RTS/GPIO2 I/O UARTA: Request to send/GPIO2
29 GPIO11 I/O GPIO11
33 GPIO7 I/O GPIO7
34 GPIO8 I/O GPIO8
35 VDDSHV I/O digital supply
36 GPIO9 I/O GPIO9


No.
40 GPIO6 I/O GPIO6
41 PCMCLK/GPIO15 I/O PCM Clock/GPIO15
49 IIC_SCL/GPIO5 I/O Serial clock link/GPIO5. ( ↑ ) An external 4.7KΩ pull-up is needed.
50 IIC_SDA /GPIO4 I/O Serial data link/GPIO4. ( ↑ ) An external 4.7KΩ pull-up is needed.
54 EM_OE_n O Output enable
55 EM_CS4_n O Chip select (asynchronous memory)
56 EM_CS3_n O Chip select (asynchronous memory)
57 EM_CS0_n O Chip select (flash)
59 EM_WAIT_n I Wait state extend signal
60 EM_RNW I/O Read/write signal used in HPI interface
61 EM_A23 O Address bus [23]
75 EM_D15 I/O Data bus [15]


No.
95 EM_WE_SDQM1 O Write strobe and data mask for SDRAM
99 EM_WE_SDQM0 O Write strobe and data mask for SDRAM
106 VDDSHV I/O Digital Supply
116 EM_CS1 O Chip select (SDRAM)
119 EM_SDCKE1 O SDRAM clock enable 1
120 EM_SDCLK O SDRAM clock signal
121 SDRAM_WE O SDRAM write enable
122 SDRAM_RAS_n O SDRAM RAS
123 SDRAM_CAS_n O SDRAM CAS
124 EM_HIZ I EMIF terminal 3-state control ( ↓ )
125 VLYNQ_CLK I/O VLYNQ clock ( ↑ )


No.
126 VLYNQ_TXD0 O VLYNQ transmit data [0]
127 VLYNQ_RXD0 I VLYNQ receive data [0]
128 VLYNQ_RXD1/GPIO26 I/O VLYNQ receive data [1]/GPIO26
129 VLYNQ_TXD1 O VLYNQ transmit data [1]
131 USB XTAL GND Should NOT connect to board GND; instead, connect to USB XTAL capacitors.
133 USB_CLKI I USB clock in
134 USB_CLKO O USB clock out
135 USB_PULLE O Pull-up enable
136 USB_DN I/O Slave differential -
137 USB_DP I/O Slave differential +
138 MII_COL I MII collision
142 MII_CRS I MII carrier sense
143 MII_TCLK I MII transmit data clock
144 MII_RCLK I MII receive data clock
145 MII_RD3 I MII receive data [3]
149 MII_RDV I MII receive data valid
150 MII_RER I MII receive data error
154 MII_TEN O MII transmit enable
155 MII_TD3 O MII transmit data [3]
162 MII_LINK I MII PHY link status
163 MII_DIO I/O MII serial-port data
164 MII_DIOCLK I/O MII serial-port clock
165 MII_PHYCLK O Ethernet PHY clock source (25 MHz)
167 EJTAG_TDI I Test data input ( ↓=)
168 EJTAG_TDO O Test data output


No.
169 EJTAG_TMS I Test mode select ( ↑ )
172 EJTAG_TCK I Test clock ( ↓ )
173 AMPC O Upstream amplifier clock
174 AMPD O Upstream amplifier data
176 AMPE_ O Upstream amplifier enable
177 AMPPD_ O Upstream amplifier power-down control
178 EJTAG_TRST0_n I Test reset (MIPS JTAG) ( ↓ )
179 EJTAG_TRST1_n I Test reset (Chip JTAG) ( ↓ )
180 EJTAG_DINT I Debug exception request ( ↓ )
181 EJTAG_SYS_RESET I JTAG reset ( ↑ )
183 EINT0/GPIO16 I/O External interrupt-0/GPIO16
186 VPP Should be tied to VDD
189 TEST I Test mode terminal. Used to put the chip into test mode. It must be tied to VSS in
normal functional operation. ( ↓ )
190 RST_N I Chip power-on reset
191 TAGCS O Automatic gain control (RF AGC)
192 AGCS O Automatic gain control
193 DAC DGND DAC digital GND
194 DAC DVDD DAC digital supply
195 DAC AVDD DAC analog 3.3-V supply
196 DAC AGND DAC analog GND
197 ION A DAC minus arm of diff output
198 IOP A DAC plus arm of diff output
199 DAC AGND DAC analog GND
200 DAC AVDD DAC analog 3.3-V supply
204 REFP A ADC reference 2-V
205 REFM A ADC reference 1-V


Chapter 9
Electrical Specifications
9.1 Operating Conditions and Device Electrical Characteristics

The TNETC4401 device does not require specific power sequencing between the core supply (1.5V) and the I/O
supply (3.3V). However, systems should be designed to ensure that neither supply is powered up for extended
periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions
can adversely affect the long-term reliability of the device. In order to avoid system (board) design issues that
might introduce conflicts on the TNETC4401 I/Os, it is preferred design practice to bring up core supply
first and bring it down last, and to have the difference between the two supplies no greater than 2.61 V.
Table 9-1. TNETC4401 Absolute Maximum Ratings over Operating Case Temperature Range (unless otherwise
†
noted)
Supply voltage range: CVDD (CORE) ‡ -0.5 V to 1.836 V
Supply voltage range: DVDD (I/O) -0.5 V to 4 V
Input-voltage range, VI -0.5 V to 4 V
Output-voltage range, VO -0.5 V to 4.5 V
Ambient temperature range (case temperature should not fall below 0°C or exceed 80°C) 0°C to 70°C
Junction-to-ambient thermal resistance, RθJA: 0-LFPM airflow, PYP package 15°C/W
Junction-to-ambient thermal resistance, RθJA: 250-LFPM airflow, PYP package 10°C/W
Junction-to-case thermal resistance, RθJC: PYP package 5°C/W
Storage temperature range, Tstg -55°C to 150°C
CDM 500 V
HBM 2000 V
† Stresses beyond those listed in Table 9-1 may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Voltage values are with respect to ground terminals.

Table 9-2. Recommended Operating Conditions

Parameter Min. Typ. Max. Unit
CVDD Core supply voltage 1.425 1.5 1.575 V
DVDD I/O supply voltage 3.14 3.3 3.46 V
VSS Supply ground 0 V
VIH High-level input voltage 2.4 V
VIL Low-level input voltage 0.8 V
VOH High-level output voltage (DVDD = MIN, IOH = MAX) 2.4 V
VOL Low-level output voltage (DVDD = MIN, IOL = MAX) 0.8 V
IOH High-level output current -8 mA
IOL Low-level output current 8 mA
Table 9-3. Electrical Characteristics over Recommended Range of Supply Voltage and Operating Case
Temperature Range for USB Terminals USBDM and USBDP (unless otherwise noted)
Parameter Test Conditions Min. Typ. Max. Unit
VDI Differential input sensitivity |DP-DM| ±0.2 V
VCM Differential common-mode range Included VDI range 0.8 2.5 V
VIL Low-level input voltage 0.8 V
VIH High-level input voltage 2 V
VOL Low-level static output voltage RL of 1.5 kΩ to 3.6 V 0.3 V
VOH High-level static output voltage RL of 1.5 kΩ to GND 2.8 3.6 V
ILO High-impedance state data-line leakage current ±10 nA
CIN Transceiver capacitance 20 pF
RO(DRV) Driver output resistance 14 Ω=
Table 9-4. Electrical Characteristics over Recommended Range of Supply Voltage and Operating Case
Temperature (unless otherwise noted)
II Input current† VI = VSS to DVDD ±20 µA
IOZ Off-state output current VO = DVDD or 0 V ±20 µA
ICVDD Core and AFE supply current CVDD = Max., RISC bus = 125 MHz, 260 mA
Peripherals bus = 62.5 MHz
with activity on all I/O terminals
IDVDD I/O supply current (including ADC, CVDD = Max., RISC bus = 125 MHz, 87 mA
PLL, DAC and Bandgap) Peripherals bus = 62.5 MHz
with activity on all I/O terminals
Ci Input capacitance 10 pF
Co Output capacitance 10 pF
Table 9-5. Crystal Electrical Characteristics over Recommended Operating Conditions

Frequency range 20 55 MHz
Frequency tolerance @ 25°C -30 +30 PPM
Frequency stability @ 25°C -50 +50 PPM
Shunt capacitance 7 pF

9.2 Analog Electrical Characteristics over Recommended Operating

Conditions
9.2.1 US DOCSIS Application

Table 9-7 and Table 9-8 define the electrical specifications and performance of the DAC and ADC with the
settings given in Table 9-6.
Table 9-6. US DOCSIS Settings

Parameter Value Notes/Test setup
Clock frequency 25 MHz
PLL multiplier *7
RSTEXT 20 KΩ 1%
Reg. 0x79 0x9B
Dig attenuation 0 dB
Reg. 0x4B 0x0
DAC equivalent load 100Ω differential 100Ω resistor from each output to GND, in shunt with
200Ω load (1:4 transformer into a 50Ω spectrum
analyzer)
ADC source equivalent 50Ω differential
impedance
Table 9-7. DAC Specifications, with US DOCSIS Configuration

Resolution 12 Bit
Conversion rate 175 180 MSPS
Digital supply 1.425 1.5 1.575 V
Voltage ripple for f < 1 MHz, peak-to-peak 10 mV
Digital current consumption of 1.5 V 3 5 mA
Analog supply 3.135 3.3 3.465 V
Voltage ripple for f < 1MHz, peak-to-peak 20 mV
Analog current consumption of 3.3 V 7 12 mA
0
Ambient temperature -40 85 C
Total power 35 55 mW
Output
Max analog current output per branch 19 mAptp
Analog voltage output per branch 0.95 Vptp
Equivalent resistive load, from each output to GND 25 50 Ω
Capacitive load 10 20 pF
Output bandwidth (-3 dB) 70 MHz
Dynamic Performance
SNDR non-carrier related (fin = 42 MHz) † -62 -59 dBc
†
SNDR carrier related, 3 max. (fin = 42 MHz) -56 -52 dBc
†
SNDR measured when transmitting a 160ksps QPSK modulated signal with even power function enabled, in a 160kHz measurement
interval.

Table 9-8. ADC Specifications, with US DOCSIS Configuration

Resolution 12 Bits
Sampling rate 30 MSPS
Digital supply voltage 1.425 1.5 1.575 V
Voltage ripple for f < 1 MHz 10 mVpp
Analog supply voltage 3.135 3.3 3.465 V
Power 45 65 mW
Refp 1.75 2.0 2.25 V
Refm 0.9 1.0 1.1 V
Refp-Refm 0.85 1.0 1.15 V
(Refm- (Refp-
AINP-AIM, (Diff signal AC coupled input) V
Refp)/2 Refm)/2
Input Resistance 5 KΩ
Input Cap 5 pF
Source Resistance 50 Ω
Input BW (-3 dB) 85 MHz
ENOB (Fin = 44 MHz) 8.4 8.7 bits
SNR (Fin = 44 MHz) 53 56 dB
SFDR (Fin = 44 MHz) 57 59 dB
SINAD (Fin = 44 MHz) 52 55 dB
Latency 3 Clocks
Gain error 2 1.75 dB
Offset error (3) ±2.5% FS
9.2.2 EuroDOCSIS Application

Table 9-10 and Table 9-11 define the electrical specifications and performance of the DAC and ADC, with the
settings given in Table 9-9.
Table 9-9. EuroDOCSIS Settings

Parameter Value Notes/Test Setup
Clock frequency 28.9 MHz
PLL multiplier *6
RSTEXT 20kΩ 1%
Reg. 0xC9 0x9B
Dig attenuation 0 dB
Reg. 0x4F 0x0
DAC equivalent load 100-Ω differential 100Ω resistor from each output to GND, in shunt with
200Ω load (1:4 transformer into a 50Ω spectrum
analyzer)
2
Guaranteed by design

Table 9-10. DAC Specifications, with EuroDOCSIS Configuration

Resolution 12 Bits
Conversion rate 173.4 180 MSPS
Digital supply 1.425 1.5 1.575 V
Analog supply 3.135 3.3 3.465 V
Total power 35 55 mW
Output
Max analog current output per branch 19 mA ptp
Analog voltage output per branch 0.95 Vptp
Equivalent resistive load, from each output to GND 25 50 Ω
Capacitive load 20 pF
Output BW (-3 dB)3 70 MHz
Dynamic Performance
SNDR Non-carrier related 4 -60 -59 dBc
4
SNDR Carrier related -55 -52 dBc
Table 9-11. ADC Specifications, with EuroDOCSIS Configuration

Resolution 12 Bits
Sampling rate 30 MSPS
Digital supply voltage 1.425 1.5 1.575 V
Analog supply voltage 3.135 3.3 3.465 V
Total
45 65 mW
Power
Refp 1.75 2.0 2.25 V
Refm 0.9 1.0 1.1 V
Refp-Refm 0.85 1.0 1.15 V
(Refm- (Refp-
AINP-AIM, (Diff signal AC coupled input) V
Refp)/2 Refm)/2
Input Resistance 5 KΩ
Input Cap 5 pF
Source resistance 50 Ω
Input BW (-3 dB) 85 MHz
3
This parameter includes the DAC sinc response for the typical sample rate (without Anti-sinc).
4
SNDR measured when transmitting a 160ksps QPSK modulated signal with even power function enabled, in a 160kHz measurement
interval.


ENOB (Fin = 36 MHz) 8.4 8.7 Bits
SNR (Fin = 36 MHz) 53 56 dB
SFDR (Fin = 36 MHz) 57 59 dB
SINAD (Fin = 36 MHz) 52 55 dB
Latency 3 Clocks
5
Gain Error 1.75 dB
Offset Error 5 ±2.5% FS
5
Guaranteed by design

Chapter 10
System Design Considerations
10.1 Crystal Oscillator

The connections to the external crystal (refers to USB crystal as well) are shown in Figure 10-1.
Notes:
Terminal 15 MUST NOT BE connected on board to GND. It must be connected ONLY to
caps C1 and C2.
C1 = C2 = 20pF, total capacitance, including PCB parasitic capacitance.
Rd = 0 Ω
Rbias = 1 MΩ
Terminal 17 should be connected to the device digital core VDD. When using external
clock, it can connect directly to XTAL_IN (terminal 18). In that case, terminal 15 should
remain floating, C1 and C2 are not needed. The external clock should not exceed 1.5 V.
TNETC4401
15, VSS
C2 Rd
16, XO
XTAL Rbias
25/ 28.9 17, VDD
C1
18, XI
Figure 10-1. Crystal Oscillator

10.2 Power Pin Summary

DAC – Analog 3.3 Volt
DAC AVDD pins: 195,200 – Apply filtered supply
DAC AGND pins: 196,199 – connect to general GND plane
ADC – Analog 3.3 Volt
ADC AVDD pins: 203,206,207,4 – Apply filtered supply
ADC AGND pins: 201,202,208,1 – connect to general GND plane
BANDGAP – Analog 3.3 Volt
BG AVDD pin: 7 – Apply filtered supply
BG AGND pin: 8 – connect to general GND plane
PLL – Analog 3.3 Volt
PLL AVDD pins: 11 – Apply filtered supply
PLL AGND pins: 12,14 – connect to general GND plane
XTAL – Digital 1.5 Volt
XTAL VDD pins: 17 – connect to general 1.5V VDD plane
XTAL GND pins: 15 – clear GND plane from the crystal and capacitors area to lower parasitic capacitance.
PLL – Digital 1.5 Volt
PLL VDD pins: 5 – Apply filtered supply
PLL GND pins: 6 – connect to general GND plane
DAC – Digital 1.5 Volt
DAC VDD pins: 194 – Apply filtered supply
DAC GND pins: 193 – connect to general GND plane
CORE Digital 1.5 Volt
VDD pins: 21, 37, 52, 68, 84, 97, 104, 117, 130, 140, 152, 160, 170
GND pins: 19, 22, 38, 53, 69, 85, 98, 105, 118, 141, 153, 161, 171 – connect to general GND plane
I/O Digital 3.3 Volt
VDDSHV pins: 35, 51, 58, 72, 83, 96, 106, 132, 139, 151, 159, 166, 175, 187

10.3 Analog
10.3.1 DAC
The DAC connections need impedance matching for optimum performance. The DAC output impedance is
optimized for a 50-Ω=termination between each output and ground. Also, each output must have a ground path.
This configuration results in a voltage swing of 0V to 0.5V in each output, according to the typical output current.
Figure 10-2 shows an example of the DAC output circuitry.
Tx_IN 198
IOP
Tuner+ Image TNETC4401

rejection LPF
AGND
R DAC
Tx_IN_ 197 ION
Figure 10-2. DAC Output Circuits
The effective impedance from each DAC output to ground is given by (R || Z/2), which should be equal to 50 Ω.
The value of R determines the DC level of the output signal. Recommended levels are between 0.25 VDC to 0.5
VDC at each output terminal.
Table 10-1. Matching Values from US DAC, per Application

Tuner Type Tuner Vendor Input Impedance Recommended Notes
Ω]
[Ω Ω]
Value for R [Ω
DFA1XMB/C Toshiba 200 100
4937 DI5 0x0035, Microtune 150 75
MT2040 Design

10.3.2 ADC
10.3.2.1 General
The ADC has been designed for AC coupled input. The connections to the ADC require two 220-nF capacitors for
AC coupling. The 200-Ω resistor is for impedance matching with the tuner.
Table 10-2. Matching Values to D/S ADC, per Application

Tuner Type Tuner Vendor Recommended Notes
Ω]
Value for R [Ω
DFA1XMB/C Toshiba 200
4937 DI5 0x0035, Microtune 1000
MT2040 Design
Figure 10-3 outlines the ADC circuitry.
TNETC4401
220nF
IFOUT+ 2
AINP
R
Tuner
220nF
IFOUT- 3 AINM
Figure 10-3. ADC Circuits
10.3.2.2 ADC Reference Voltage

The ADC has two reference pins REFP (Terminal 204) and REFM (Terminal 205). From each pin, a pair of 1uF
and 1nF capacitors must be connected to analog ground, as close to the pin as possible.
10.3.3 Band Gap

The band gap provides analog reference current to all the analog cells. An external resistor at RSTEXT (Terminal
10) controls the reference current.
DOCSIS/EuroDOCSIS: a 19.1KΩ, 1% default-value resistor should be connected between this terminal and DAC
analog ground (PBGR).
Other values can be used to optimize the DAC output, per application.

10.4 AGC Connections and Functions

The 4401 enables full range span for both TAGCS and AGCS control lines. By using two separate AGC registers
(IF register and RF register), the user has a full VSS-to-VDD swing on each AGC control line.
(In the 4042 device the VSS-to-VDD swing is divided between the control lines: AGS+TAGS gives the
VSS-to-VDD voltage swing).
This implementation eliminates the need for an external amplifier that increases the partial voltage span to the
required control range of each individual VGA/VATT (variable gain amplifier/variable attenuator).
Using a span of VSS-to-VDD allows for a direct connection to the VGA/VATT after a simple RC filtration stage
(shown in Figure 10-4).
Additional filtration can be used prior to the tuner connection, depending on application. If a larger span is
required, a simple level shifter can be used prior to the filtration stage.
From TNETC4401
AGC control pins To RF/IF gain
10kohm
control stages
10 nF
Figure 10-4. AGC Control Line Filtration Stage
For more information regarding the AGC configuration, please refer to Chapter 4 in the TNETC4401 DOCSIS
Cable Modem Block User’s Guide.
10.5 Layout Recommendations

1. All of the RF/IF sections in the cable modem, especially the upstream section, should be kept as far apart as
possible from any clock sources, digital-data transfer lines and switched power supplies.
2. The RF/IF path should be kept on a single layer, preferably a separate one from the digital section, and
insulated by a ground layer.
3. An option to shield the RF/IF section from the digital section should be incorporated in the initial layout to
enable debugging and analysis of any interference.
4. All signal routes should be kept as short as possible.
5. The TNETC4401 should be laid out on a solid ground plain with thermal vias, as recommended in the
package assembly section.
6. The RF downstream and upstream sections should have a direct-short ground path to the power supply
input, if designed on a separate plane.
7. The digital path should have a direct-short ground path to the power supply input, if designed on a separate
plane.
8. Power supply lines for the upstream and downstream sections should be routed away from the digital
section. All specified analog power supplies should be filtered as close to the device as possible.
9. Digital and switched power lines, prior to proper filtering, should be routed away from the upstream and
downstream sections.

10. If the power plane exists above critical sensitive lines (for example, upstream or downstream signals), an
additional capacitance between it and the GND plane (small capacitance pF-nF) can be added around these
lines to filter noise currents that flow in their environment. An area of thermal land is required underneath the
body of the PowerPAD package. The thermal land should be as large as possible (maximum package body
size, minus 2.0 mm). A solder mask area at the center of the thermal land should be available for soldering
the package thermal pad. For heat transfers from thermal land to internal and external copper planes, apply
thermal vias (13 mil diameter and 65 mil pitch). It is highly recommended that an internal ground plane be
used for heat removal.
For more details regarding the PCB design guidelines, refer to the PowerPAD Thermally Enhanced Package
document.

Chapter 11
Switching Characteristics
11.1 JTAG TEST Interface
11.1.1 Timing Requirements

Table 11-1. JTAG Test
No. Min. Typ. Max. Unit
1 tc(TCK) Cycle time, EJTAG_TCK 50 ns
2 tsu(TDIV-TCKH) Setup time, EJTAG_TDI/TMS/TRST_n valid before EJTAG_TCK↑ 10 ns
3 th(TCKH -TDIV) Hold time, EJTAG_TDI/TMS/TRST_n valid after EJTAG_TCK↑ 9 ns
4 tW(H) Pulse duration high, EJTAG_TCK 20 ns
5 tW(L) Pulse duration low, EJTAG_TCK 20 ns
Duty cycle, EJTAG_TCK 50%
11.1.2 Switching Characteristics over Recommended Operating Conditions

Table 11-2. JTAG Test
No. Min. Max. Unit
6 td(TCKL -TDOV) Delay time, EJTAG_TCK↓==to EJTAG_TDO valid 0 15 ns
4 5
1
EJTAG_TCK
(input)
6 6
EJTAG_TDO
(output)
3
EJTAG_TDI/TMS/TRST_n 2
(inputs)
Figure 11-1. JTAG TEST

11.2 EJTAG Interface
Table 11-3. EJTAG Timing Requirements

No. Min. Max. Unit
1 tc Cycle time, EJTAG_TCK 25 ns
2 tw(H) Pulse duration high, EJTAG_TCK 10 ns
3 tw(L)1 Pulse duration low, EJTAG_TCK 10 ns
4 tsu Setup time, EJTAG_TMS/EJTAG_TDI/ EJTAG_TRST valid before EJTAG_TCK↑ 10 ns
5 th Hold time, EJTAG_TMS/EJTAG_TDI/ EJTAG_TRST0 valid after EJTAG_TCK↑ 0.5 ns
Table 11-4. EJTAG Test – Switching Characteristics over Recommended Operating Conditions
No. Min. Max. Unit
6 td1 Delay time from EJTAG_TCK↓ to EJTAG_TDO valid 0 15 ns
1
2 3
EJTAG_TCK
(input)
EJTAG_TMS
EJTAG_TDI
EJTAG_TRST
(inputs)
4 5
EJTAG_TDO Z
(output)
6
1
2 3 7
EJTAG_TCK
( input)
7
EJTAG_TMS
EJTAG_TDI
(inputs)
5 6 10 7
EJTAG_TDO Z
(output)
7 8 9
EJTAG_TRST0_n
4
EJTAG_TRST1_n
(input)
Figure 11-2. EJTAG Test

11.3 Ethernet Interface
Table 11-5. RX Timing Requirements

No. Min. Max. Unit
1 tc(MII_RCLK) Cycle time, MII_RCLK 40 400 ns
2 tw(MII_RCLK L) Pulse duration, MII_RCLK low 14 ns
3 tw(MII_RCLK H) Pulse duration, MII_RCLK high 14 ns
4 tsu(MII_RXD) Setup time, MII_RXD3-MII_RXD0 valid before MII_RCLK↑ 3 ns
4 tsu(MII_RXDV) Setup time, MII_RXDV valid before MII_RCLK↑ 3 ns
4 tsu(MII_RXER) Setup time, MII_RXER valid before MII_RCLK↑ 3 ns
5 th(MII_RXD) Hold time, MII_RXD3-MII_RXD0 valid after MII_RCLK↑ 1 ns
5 th(MII_RXDV) Hold time, MII_RXDV valid after MII_RCLK↑ 1 ns
5 th(MII_RXER) Hold time, MII_RXER valid after MII_RCLK↑ 1 ns
Note:
Both MII_CRS and MII_COL are driven asynchronously by the PHY.
MII_RXD3-MII_RXD0 is driven by the PHY on the falling edge of MII_RCLK.
MII_RXD3-MII_RXD0 timing must be met during clock periods when MII_RXDV is
asserted. MII_RXDV is asserted and de-asserted by the PHY on the falling edge of
MII_RCLK. MII_RXER is driven by the PHY on the falling edge of MII_RCLK.
1
4 5
2 3
MII_RCLK
(input)
MII_RXD3-MII_RXD0
MII_RXDV
(inputs)
Figure 11-3. MII_RX Port

Table 11-6. TX Timing Requirements

No. Min. Max. Unit
1 tc(MII_TCLK) Cycle time, MII_TCLK 40 400 ns
2 tw(MII_TCLK L) Pulse duration, MII_TCLK low 14 ns
3 tw(MII_TCLK H) Pulse duration, MII_TCLK high 14 ns
Table 11-7. TX Port – Switching Characteristics over Recommended Operating Conditions

No. Min. Max. Unit
4 td(MII_TXD) Delay time, from MII_TCLK↑ to MII_TXD3-MII_TXD0 valid 6 16 ns
4 td(MII_TXEN) Delay time, from MII_TCLK↑ to MII_TXEN valid 6 16 ns
Note 2:
Both MII_CRS and MII_COL are driven asynchronously by the PHY.
The reconciliation sublayer drives MII_TXD3-MII_TXD0 synchronous to the MII_TCLK.
MII_TXEN is asserted and de-asserted by the reconciliation sublayer synchronous to the
MII_TCLK rising edge.
1
4
2 3
MII_TCLK
(input)
MII_TXD3-MII_TXD0
MII_TXEN
(outputs)
Figure 11-4. MII_TX Port
11.3.1 Switching Characteristics over Recommended Operating Conditions

Table 11-8. MII_DIO Data Input Port
No. Min. Max. Unit
1 td1 Setup time, MII_DIO valid to MII_DIOCLK↑ 10 ns
2 td2 Hold time, MII_DIOCLK↑ to MII_DIO invalid 5 ns
MII_DIOCLK
(outputs)
1 2
MII_DIO
(inputs)
Figure 11-5. MII_DIO Data Input Port

Table 11-9. MII_DIO Data Output Port

No. Min. Typ. Max. Unit
3 td3 Delay time, MII_DIOCLK↑ to MII_DIO valid 20 40 ns
4 tc Cycle time, MII_DIOCLK, fclock = 8 MHz 50 125 ns
5 tph MII_DIOCLK, high 30 ns
6 tpl MII_DIOCLK, low 30 ns
4
MII_DIOCLK
(outputs)
3
MII_DIO
(outputs)
Figure 11-6. MII_DIO Data Output Port
11.4 USB Interface
Table 11-10. USB I/O Timing Requirements

No. Min. Max. Unit
1 tc 2 cycle time 166.5 ns
I/O
Figure 11-7. USB I/O Timing Requirements

Table 11-11. USB I/O – Switching Characteristics over Recommended Operating Free-Air Temperature Range
(Full Speed)
No. Parameter Test Conditions Min. Max. Unit
4 tr Rise time, USB_DP/USB_DN Between same two reference points (10% and 90%), 4 20 ns
CL = 50 pF, RL = 1.5 kΩ=
5 tf Fall time, USB_DP/USB_DN Between same two reference points (10% and 90%), 4 20 ns
CL = 50 pF, RL = 1.5 kΩ=
VO(CRS) Voltage output signal crossover 1.3 2 V
4, 5 tr = tf
USB_DN VOH
VO(CRS) 90%
USB_DP 10%
VOL
(I/Os)
Figure 11-8. USB I/O

11.5 I2C Master Interface

2
Table 11-12. I C Master – Switching Characteristics over Recommended Operating Conditions
No. Parameter Min. Max. Unit
0 fc Clock frequency, IIC_SCL 0 400 kHz
1 tw(H) Pulse duration, IIC_SCL, high 0.6 µs
2 tw(L) Pulse duration, IIC_SCL, low 1.3 µs
3 tr Rise time,(transition time) IIC_SCL and IIC_SDA 300 ns
4 tf Fall time, ,(transition time) IIC_SCL and IIC_SDA 300 ns
5 td1 Delay time, IIC_SDA valid to IIC_SCL↑ 100 ns
6 td2 Delay time, IIC_SCL↓ to IIC_SDA invalid 0 ns
7 td3 Delay time, IIC_SDA↑ (stop condition) to IIC_SDA↓ (start condition), bus free time 1.3 µs
8 td4 Delay time, IIC_SCL↑ to IIC_SDA↓ (start condition) 0.6 µs
9 td5 Delay time, IIC_SDA↓ (start condition) to IIC_SCL↓ 0.6 µs
10 td6 Delay time, IIC_SCL↑ to IIC_SDA↑ (stop condition) 0.6 µs
11 tsu Setup time, IIC_SDA 0.1 µs
CL Load capacitance for each bus line 400 pF
Notes:
Exact timing is dependent on the IIC_SCL period (clock cycle time). This value is chosen
by the programmed value in the clock divider register, which is a percentage of the
IIC_CLK period. For more details, see the TNETC4400/4401 User's Guide.
Both IIC_SCL and IIC_SDA are tested under 4.7KΩ pull-up resistors to 3.3 V.
1 2 3 4
IIC_SCL
(output)
5 6
IIC_SDA
(output)
Figure 11-9. IIC_SCL and IIC_SDA
IIC_SCL
(output) 1 2 8 9
IIC_SDA
(output)
IIC_SDA
(input)
Figure 11-10. Acknowledge

IIC_SCL
(output)
8 10
9 7
IIC_SDA
(output)
Start Condition Stop Condition
Figure 11-11. Start and Stop Condition
11.6 VLYNQ Interface
Table 11-13. VLYNQ Timing Parameters

No. Parameter Min. Max. Unit
1 Clock period (Tperiod), VLYNQ_CLK 8 No limit ns
2 Pulse duration, VLYNQ_CLK high 3.2 4.8 ns
3 Pulse duration, VLYNQ_CLK low 3.2 4.8 ns
4 Delay time, VLYNQ_CLK ↑ to VLYNQ_TXDx invalid 2.1 ns
5 Delay time, VLYNQ_CLK ↑ to VLYNQ_TXDx valid 7 ns
6 Setup time, VLYNQ_RXDx before VLYNQ_CLK ↑ -0.75 ns
7 Hold time, VLYNQ_RXDx after VLYNQ_CLK ↑ 2.2 ns
Notes:
Table 11-13 assumes that the difference in the board delay for VLYNQ_CLK and any
VLYNQ_TXDx pin is less than 0.25 ns (used for the Rx hold time margin). It also
assumes that the total board delay for VLYNQ_CLK plus any VLYNQ_TXDx signal is less
than 1.00 ns (used for maximum VLYNQ_CLK to VLYNQ_TXDx valid delay time).
Maximum pin loading is assumed to be 15 pF.
5 6 4,7 3 2
VLYNQ_CLK
VLYNQ_TXD
VLYNQ_RXD
Figure 11-12. VLYNQ Timing

11.7 External Memory Interface
Table 11-14. Synchronous DRAM Read – Switching Characteristics over Recommended Operating
Conditions
No. Parameter Half Rate Full Rate Unit
Min. Max. Min. Max.
0 tct Cycle time, EM_SDCLK 8 8
1 td1 Delay time, EM_SDCLK↑ to EM_CE3_n-CE0_n/SDRAS_n/SDCAS_n/SDWE_n 5.5 5.5 ns
Valid
2 td2 Delay time, EM_SDCLK↑ to EM_A23- EM_A0 valid 5.5 5.5 ns
3 td3 Delay time, EM_SDCLK↑ to EM_A23- EM_A0 invalid 1 1 ns
4 td4 Delay time, EM_SDCLK↑ to EM_WE_SDQM0,1↓ (mask) 5.5 5.5 ns
5 td5 Setup time, EM_D15-EM_D0 valid to EM_DSCLK↑ 3 2 ns
6 td6 Hold time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 1.5 1.5 ns
1 2 3 4 5 6 7 8 9 10 11 12 13 14
EM_SDCLK
(output)
EM_CE3_n-_CE0_n
- 1
SDRAS_n/
SDCAS_n/ Active NOP* NOP* Read Read NOP* NOP* NOP* Read NOP* NOP* DA*
SDWE_n
(outputs) 2 3
EM_A23-0
- Row A§ B§ C§
(output)
EM_WE_SDQM0-1 4
(output)
5
6
EM_D15-0
- Data Data Data Data Data Data
(input) A B0 B3 C0 C1 C2
CAS Latency = 2
Burst Length = 4
* No operation (NOP)
* Deactivate (DA) can be referred to as precharge.
§ A, B, C = Column A, column B, column C
Figure 11-13. Synchronous DRAM Read

Table 11-15. Synchronous DRAM Write – Switching Characteristics over Recommended Operating Conditions
Min. Max. Min. Max.
0 tct Cycle time, EM_SDCLK 8 8
1 td1 Delay time, EM_SDCLK↑ to EM_CE3_n-CE0_n/SDRAS_n/SDCAS_n/SDWE_n 5.5 5.5 ns
Valid
2 td2 Delay time, EM_SDCLK↑ to EM_A23-EM_A0 valid 5.5 5.5 ns
3 td3 Delay time, EM_SDCLK↑ to EM_A23-EM_A0 invalid 1 1 ns
4 td4 Delay time, EM_SDCLK↑ to EM_WE_SDQM0,1↓ (mask) 5.5 5.5 ns
5 td5 Min Prop time, EM_D15-EM_D0 valid to EM_SDCLK↑ 1 1 ns
6 td6 Max Prop time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 5.5 5.5 ns
1 2 3 4 5 6 7 8 9 10 11 12 13 14
EM_SDCLK
(output)
EM_CE3_n-CE0_n/ 1
SDRAS_n/
SDCAS_n/ Active NOP* NOP* Write Write NOP* NOP* NOP* Write NOP* NOP* DA*
SDWE_n
(outputs)
2 3
EM_A23-0 Row A§ B§ C§
(output)
4
EM_WE_SDQM0-1
-
(output)
5 6
EM_D15-0 Data Data Data Data Data Data

(output) A B B3 C0 C1 C2
CAS Latency = 2
Burst Length = 4
* No operation NOP)
(
* Deactivate (DA) can be referred to as precharge.
§ A, B, C = Column A, column B, column C.
Figure 11-14. Synchronous DRAM Write

Table 11-16. Asynchronous Memory Read (No Wait)

Min. Max. Min. Max.
1 td1 Delay time, EM_SDCLK↑ to EM_CE3_n- EM_CE0_n ↓ 5.5 5.5 ns
2 td2 Delay time, EM_SDCLK↑ to EM_CE3_n- EM_CE0_n ↑ 1 1 ns
5 td5 Delay time, EM_SDCLK↑ to EM_OE_n ↓ 5.5 5.5 ns
6 td6 Delay time, EM_SDCLK↑ to EM_OE_n ↑ 1.3 ns
7 td7 Setup time, EM_D15-EM_D0 valid to EM_SDCLK↑ 3.2 2 ns
8 td8 Hold time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 1.6 1.6 ns
Setup = 2 Cycles
EM_SDCLK
(output)
1 Strobe = 7 Cycles 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
-
(output)
8
7
EM_D15-0 High Z
(input)
5 6
EM_OE_n
(output)
High
SDRAM_WE_n
(output)
Read Setup* Read Strobe* Read Hold§

* Programmable from 1 -16 clock periods (cycles)
§ Programmable from 1 8- clock periods (cycles)
NOTE A: Values in asynchronous configuration and control register:
Read setup = 1
Read strobe = 6
Read hold = 0
Figure 11-15. Asynchronous Memory Read (No Wait)

Table 11-17. Asynchronous Memory Read (Wait)

Min. Max. Min. Max.
5 td5 Delay time, EM_SDCLK↑ to EM_OE_n ↓ 5.5 5.5 ns
6 td6 Delay time, EM_SDCLK↑ to EM_OE_n ↑ 1.3 ns
7 td7 Delay time, EM_D15-EM_D0 valid to EM_SDCLK↑ 3.2 2 ns
8 td8 Delay time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 1.6 1.6 ns
9 td9 Setup time, EM_WAIT_n↓ to EM_SDCLK↑ 3 ns
10 td10 Delay time, EM_SDCLK↑ to EM_WAIT_n↑ 3 ns
Not Ready =
Setup = 2 Cycles* Strobe = 5 Cycles* 2 Cycles
EM_SDCLK
(output)
1 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
(output)
8
7
High Z
EM_D15-0
(input)
SDRAM_WE_n High
(output)
10
9
EM_WAIT_n
(input)
5 6
EM_OE_n
(output)
Read Setup* Read Strobe* Read Hold§

* Programmable from 1 -16 clock periods
* Programmable from 1 -64 clock periods
§ Programmable from 1 -8 clock periods
Read setup = 1
Read strobe = 4
Read hold = 0
Figure 11-16. Asynchronous Memory Read (Wait)

Table 11-18. Asynchronous Memory Write (No Wait)

Min. Max. Min. Max.
5 td5 Delay time, EM_SDCLK↑ to EM_D15-EM_D0 valid 3.2 2 ns
6 td6 Delay time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 1.6 1.6 ns
Setup = 2 Cycles
EM_SDCLK
(output)
1 Strobe = 7 Cycles 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
(output)
5 6
EM_D15-0
High Z
(output)
EM_OE_n High
(output)
SDRAM_WE_n 7 8
(output)
Write Setup* Write Strobe* Write Hold§
* Programmable from -116 clock periods (cycles)

* Programmable from -164 clock periods (cycles)
§ Programmable from -18 clock periods (cycles)
Write setup = 1
Write strobe = 6
Write hold = 0
Figure 11-17. Asynchronous Memory Write (No Wait)

Table 11-19. Asynchronous Memory Write (Wait)

Min. Max. Min. Max.
5 td5 Delay time, EM_SDCLK↑ to EM_D15-EM_D0 valid 5.5 5.5 ns
6 td6 Delay time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 1.3 ns
7 td7 Delay time, EM_SDCLK↑ to SDRAM_WE_n↓ 5.5 5.5 ns
8 td8 Delay time, EM_SDCLK↑ to SDRAM_WE_n↑ 5.5 5.5 ns
9 td9 Delay time, EM_WAIT_n↓ to EM_SDCLK↑ 3 ns
10 td10 Delay time, EM_SDCLK↑ to EM_WAIT_n↑ 3 ns
Not Ready =
Setup = 2 Cycles Strobe = 5 Cycles 2 Cycles
EM_SDCLK
(output)
1 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
(output)
5 6
EM_D15-0 High Z
(output)
EM_OE_n High
(output)
7 8
SDRAM_WE_n
(output)
10
EM_WAIT_n 9
(input)
Write Setup* Write Strobe* Write Hold§

§ Programmable from 1 -8 clock periods (cycles)
Write setup = 1
Write strobe = 4
Write hold = 0
Figure 11-18. Asynchronous Memory Write (Wait)

Chapter 12
Parameter Measurement
Information
IOL
Tester-Pin Electronics
Output
50 Ω= Under
Vref Test
CT† = 60 pF
IOH
†
Typical distributed load circuit capacitance
Figure 12-1. Tester-Pin Electronics
12.1 Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.
Vref = 1.5 V
Figure 12-2. Input and Output Voltage Reference Levels for Timing Measurements


Chapter 13
Mechanical Data
Figure 13-1. Mechanical Package Diagram


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TNETC4401

ADVANCE INFORMATION concerns new products in the sampling or

Version 1.2 – April 2003 SPRS201 i

Copyright © 2003, Texas Instruments Incorporated

ii SPRS201 Version 1.2 – April 2003

Chapter 2: Description ..........................................................................................................2-1

Chapter 3: Memory Map........................................................................................................3-1

Chapter 4: Functional Overview...........................................................................................4-1

Version 1.2 – April 2003 SPRS201 iii

Chapter 5: Clock Management............................................................................................. 5-1

Chapter 6: Power Management............................................................................................ 6-1

Chapter 7: Initialization ........................................................................................................ 7-1

Chapter 8: Terminal Descriptions........................................................................................ 8-1

Chapter 9: Electrical Specifications .................................................................................... 9-1

Chapter 10: System Design Considerations..................................................................... 10-1

iv SPRS201 Version 1.2 – April 2003

Chapter 11: Switching Characteristics ..............................................................................11-1

Chapter 12: Parameter Measurement Information............................................................12-1

Chapter 13: Mechanical Data..............................................................................................13-1

Version 1.2 – April 2003 SPRS201 v

vi SPRS201 Version 1.2 – April 2003

Version 1.2 – April 2003 SPRS201 vii

viii SPRS201 Version 1.2 – April 2003

•= MIPS Processor •= 10/100 Base-T Ethernet Interface Module

Version 1.2 – April 2003 SPRS201 1-1

•= DES Module •= Three 16-bit Timers with 12-bits Pre-scale

1-2 SPRS201 Version 1.2 – April 2003

Version 1.2 – April 2003 SPRS201 2-1

2.1 Functional Block Diagram

External Memory Controller

High-speed Crossbar - 125Mhz

Power Managment Module

Figure 2-1. TNETC4401 Functional Block Diagram

2-2 SPRS201 Version 1.2 – April 2003

The TNETC4401 includes the following modules:

Version 1.2 – April 2003 SPRS201 2-3

2-4 SPRS201 Version 1.2 – April 2003

Table 3-1. Memory Map

Version 1.2 – April 2003 SPRS201 3-1

Device Start End Allocated Masters That Can

Note: The master interfaces in the TNETC4401 are as follows:

3-2 SPRS201 Version 1.2 – April 2003

4.1 MIPS Processor

Version 1.2 – April 2003 SPRS201 4-1

Figure 4-1 shows the block diagram of 4Kc core.

Multiply/Divide Instruction EJTAG

Figure 4-1. 4Kc Core Block Diagram

The core consists of required and optional blocks, as follows:

The five stages are:

4-2 SPRS201 Version 1.2 – April 2003

Figure 4-2. 4Kc Core Pipeline

4.1.1 I Stage (Instruction Fetch)

4.1.2 E Stage (Execution)

4.1.3 M Stage (Memory Fetch)

Version 1.2 – April 2003 SPRS201 4-3

4.1.4 A Stage (Align)

4.1.5 Writeback (W Stage)

4.2 Peripheral Modules

4.2.1 External Memory Controller (EMIF)

Table 4-1. Chip-Select Assignments

Memory Port Memory Type

4-4 SPRS201 Version 1.2 – April 2003