1942
7, JULY 2009
A Low-Complexity, Low-Phase-Noise, Low-Voltage
Phase-Aligned Ring Oscillator in 90 nm
Digital CMOS
Jonathan Borremans, Member, IEEE, Julien Ryckaert, Member, IEEE, Claude Desset, Member, IEEE,
Maarten Kuijk, Member, IEEE, Piet Wambacq, Member, IEEE, and Jan Craninckx, Senior Member, IEEE
Abstract—An 8-phase phase-aligned ring oscillator in 90 nm dig-
ital CMOS is presented that operates up to 2 GHz. The low-com-
plexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz,
while a flat in-band phase noise below 120 dBc Hz is achieved,
in close agreement with the presented theory. The circuit occupies
an area of 0.008 mm2 .
Index Terms—Clock multiplier, CMOS, low-voltage, realign-
ment, ring oscillator.
I. INTRODUCTION
NCOURAGED by their appealing low-area, flexibility
E and scaling-friendly properties, all-digital transceiver ICs
emerge in low-cost digital CMOS. Unfortunately, these systems
are hampered by the VCO inductor, often required to meet the
stringent phase noise requirements, for example in wireless
applications. As a result, a thick RF top metal layer is usually
required for the area-greedy inductor, and the concept of a
true all-digital transceiver is obstructed. Similarly, the limited
tuning range of inductor-based oscillators is a showstopper for
wideband systems.
Inductor-less ring oscillators can provide a solution to truly
all-digital implementations, however, these are hindered by
poor phase-noise performance. Attempting to lower phase noise
in ring oscillators, scaling up the current consumption is not
an option. Achieving wireless phase noise specifications would
require exuberant power consumption, which is undesirable in
wireless, portable devices. Interestingly, techniques have been
suggested—mainly for wireline applications—to lower the
phase noise of inductorless ring oscillators. These techniques
use the principle of injection locking to a clean reference
frequency [1]–[3], to reduce the jitter, and therefore the phase
noise.
In this work, we investigate how aligning oscillators to a
clean reference lowers the close-in phase noise. We present
Manuscript received November 18, 2008; revised March 03, 2009. Current
version published June 24, 2009.
J. Borremans, J. Ryckaert, C. Desset, and J. Craninckx are with IMEC, 3001
Leuven, Belgium (e-mail: borreman@imec.be).
P. Wambacq is with IMEC, 3001 Leuven, Belgium, and also with the Vrije
Universiteit Brussel, Department ETRO, Belgium.
M. Kuijk is with the Vrije Universiteit Brussel, Department ETRO, Belgium.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2009.2020231
0018-9200/$25.00 © 2009 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO.
a low-complexity low-power 8-phase phase-aligned ring os-
cillator (PARO) operating up to 2 GHz. At this frequency, it
achieves a flat close-in phase noise lower than 120 dBc Hz at
offset frequencies down from 1 MHz, while consuming 13 mW.
Similar performance is achieved operating at 400 MHz with a
power consumption of 1.8 mW. The proposed low-complexity
oscillator circuit is sub-1 V compatible and takes advantage
of the high speed of downscaled CMOS. Quantitative and
intuitive theory on the impact of realignment on phase noise is
presented.
This work, which extends the work in [10] with more theory,
measurements and discussion, is organized as follows. First, the
general low-complexity topology is introduced in Section II.
Next, simple, intuitive, implementation-independent theory is
presented in Sections III and IV. Section V handles on the im-
plementation. Finally, the measurements are presented and ap-
plication and conclusions follow.
II. PHASE-ALIGNED OSCILLATORS
Jitter in a free-running oscillator accumulates over time, re-
sulting in a drift of the phase in time (random walk), expressed
as phase noise in the frequency domain (Fig. 1). As an illustra-
tion, Fig. 2 shows the simulated evolution of the RMS jitter in a
ring oscillator, as a function of the number of cycles. It can be
seen that the jitter increases with a slope, with being
the accumulation of oscillation cycles. In fact, it has been shown
in [8] that the jitter is given by
(1)
In this equation, is the PSD of the free-running VCO,
the oscillation frequency, and the time after which the
jitter is evaluated. After a longer number of cycles, the slope
increases due to -noise (see Fig. 2), which is not modeled by
(1).
The driving idea of phase-aligned oscillators is to truncate this
accumulating jitter process by aligning the oscillator phase to a
clean clock edge with period . At each realigning edge, the
phase error accumulation of the oscillator is reset, after which
jitter starts building up again. To illustrate this principle, a mea-
surement of such an event is shown in Fig. 3, using a very low
realignment frequency. This measurement was taken with an os-
cilloscope where a large number of snapshots are overlaid. At
the reference edge (and some delay), the oscillation is restarted.
BORREMANS et al.: A LOW-COMPLEXITY, LOW-PHASE-NOISE, LOW-VOLTAGE PHASE-ALIGNED RING OSCILLATOR IN 90 nm DIGITAL CMOS
Fig. 1. Conceptual phase evolution over time in (a) an unlocked oscillator,
(b) an oscillator in a typical PLL, and (c) a realigned VCO.
Fig. 2. Simulated jitter as a function of number of oscillation cycles in a ring
0
oscillator, using a behavioral model operating at 1 GHz, with 100 dBc=Hz
phase noise at 1 MHz offset.
Fig. 3. Exaggerated illustration of jitter truncation on a measurement of
a phase-realigned oscillator. At the reference edge (and some delay), the
oscillator is reset, and so is the jitter.
Clearly, while a lot of jitter is present before realignment, after
realignment, the edges are clean.
Due to the repetitive correction, the phase deviation over time
remains limited to that within a reference clock period, and so
does the average jitter. Equivalently, as will be shown further,
the phase noise is reduced down from an offset equal to the
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1943
Fig. 4. (a)-(c) Typical implementations of aligned oscillators, and (d) proposed
implementation.
reference frequency, similar as within the loop bandwidth of a
typical PLL. A key advantage of the technique is that the re-
alignment frequency can be chosen much higher than the loop
bandwidth of a typical PLL. Indeed, in the latter system noise
and stability issues prevent choosing a high bandwidth. There-
fore, in realigned oscillators, phase noise can be lowered down-
wards from much higher offset frequencies. However, since the
realignment is a repetitive process in nature, the spectrum suf-
fers from spurious tones at multiples of the reference frequency
offset.
Different implementations have been proposed for realigned
oscillators, more generically called clock multipliers. A basic
solution, injection locking (Fig. 4(a) [1]) benefits simplicity, but
suffers from incomplete realignment. As a result, since the re-
alignment has no full control, phase noise is only moderately
lowered. A more elaborate technique (Fig. 4(c) [3]) injects a
clean edge by multiplexing the oscillator’s edge with the clean
one, at each reference time. Complete realignment is achieved,
but the timing and circuit complexity is increased, including
loops, counters and multiplexers. Especially at high frequen-
cies, the timing of these loops is complicated and challenging
[3]. A yet different technique consists of an open loop delay
chain, where edges are combined to form the high-frequency
clock (Fig. 4(b) [2]). This solution requires increased care over
matching yielding high power consumption, also due to the mul-
tiplexer block.
In this work, we propose a simple modified architecture
(Fig. 4(d)) that alleviates timing issues. A reference edge is
converted into a pulse that briefly disables and restarts the os-
cillator to reset it. We exploit the property that a ring oscillator
starts up immediately when an edge is injected. This solution
requires no loops, nor complex circuitry. Therefore, this limits
the sources for noise, jitter, power and area consumption.
III. PHASE NOISE OF ALIGNED OSCILLATORS
It is instructive to catch the influence of the realignment on the
phase noise of an oscillator quantitatively. While noise theory
of realigned systems has been presented, mostly from the PLL
perspective (e.g., [1]), we aim to present an implementation-
independent—and perhaps more intuitive—theory. To this end,
we determine the PSD of the realigned oscillator.
Because of the repetitive nature of the realignment, we can
treat the phase error in the system as a cyclostationary process
1944 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009

Fig. 6. Illustration of the autocorrelation function of the phase during the re-
alignment process.

valid for the interval , which is illustrated in

Fig. 6. For the autocorrelation since
there is no correlation. The phase noise power spectral density
(PSD) can now be calculated:

(6)

where denotes the Fourier transform and is the offset pul-

sation from the carrier. We obtain

(7)

In this equation, we recognize as the PSD of a free run-

Fig. 5. Illustration of jitter truncation over time and offset frequency. ning VCO, which is achieved when the realignment frequency
goes to zero (no realignment, ).
with period ([7]). We assume that the phase error at time We can find the Taylor expansion for (7) for small offset fre-
, , can be modeled as a random variable with a zero-mean quencies ( ):
Gaussian distribution with variance where is
the time interval between and the previous realignment in-
stance (see Fig. 5) and the variance of the phase error. is
a proportional constant. The phase noise power spectral density
(PSD) – which is our main interest – can be calculated as the (8)
Fourier transform of the autocorrelation function of
this process. which shows that the level of the phase noise plateau is propor-
The autocorrelation can be found by averaging over the cy- tional to revealing a 20 dB roll-off per decade of increase
clostationary period, as in the realignment frequency. For a fixed realignment frequency,
the phase noise flattens towards low offset frequencies ( )
(2) with a corner frequency around (Fig. 5). Prac-
tically, when a flat phase noise of for example 120 dBc Hz is
desired up to at least 10 MHz, this could be achieved with a
where denotes the expectation value of . We can evaluate
ring oscillator with 128 dBc Hz phase noise at a 100 MHz
the expectation value as
offset, realigned at this last frequency. Doubling the reference
frequency, halves the phase noise.
(3)

for (or thus before realignment), since IV. SPURIOUS PERFORMANCE IN PHASE-ALIGNED
where is an inno- OSCILLATORS
vation, independent of the previous value because of the above
Unfortunately, due to the repetitive and intrusive nature of the
assumptions. For , we find
realignment, spurs are introduced. Several sources for spurious
performance—observed as deterministic jitter—are apparent in
(4)
realigned oscillators.
since after realigning the oscillator, there is no more correlation • Frequency offset: when the realigned oscillator’s fre-
between phases before and after realignment. Substituting (3) quency has an offset from an integer multiple of the
and (4) in (2) and solving the integral, we find the autocorrela- reference frequency – in other words, when the oscillator
tion as is not perfectly in lock – spurs occur since the last carrier
period in a reference period is different from all other
periods. This systematic error expressed as spurs causes
(5) deterministic jitter. Thus, an adequate loop (a simple FLL

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BORREMANS et al.: A LOW-COMPLEXITY, LOW-PHASE-NOISE, LOW-VOLTAGE PHASE-ALIGNED RING OSCILLATOR IN 90 nm DIGITAL CMOS 1945

Fig. 7. Phase-aligned ring oscillator block diagram and timing scheme.

Fig. 8. (a) Ring oscillator realignment pulser block diagram, (b) delay cell, and (c) transistor-level implementation of the delay cell.

is sufficient) around the oscillator to make an exact
multiple of is required to lower the spurs.
• Parasitic mixing: integrated circuits on a chip suffer from
parasitic reference-and-carrier coupling, creating mixing
terms at [5]. Proper design should emphasize
on increasing the isolation between reference and carrier to
lower this type of spurious performance.
Mismatch of delay elements in delay line based implementa-
tions (e.g., Fig. 4(c)) which also causes spurs due to duty-cycle
modulation, is not an issue in our ring oscillator-based imple-
mentation, where every cycle experiences the same mismatch.
Phase noise of the oscillator also causes phase jumps due to the
realignment, but stochastically, these jumps average out, and are
not a source of spurs.
V. A LOW-COMPLEXITY PHASE-ALIGNED OSCILLATOR
In this section, we discuss the implementation details of the
low-complexity PARO according to the topology of Fig. 4(d).
The core oscillator (Fig. 7) consists of four stages, which el-
egantly provides four differential 45-degree phase-shifted sig-
nals. These phases can be particularly useful in for example lin-
earized-LO mixers that reduce the spurious response [9], [4].
The alignment operation is achieved exploiting the property
that a ring oscillator starts up immediately when an edge is in-
jected. At the reference edge, a pulse of width is created
that disables one stage, opening the loop to prevent the running
edge from being propagated (Fig. 7). This pulse should be wider
than the jitter, and narrower than half of the oscillator’s period
to allow for adequate operation. By disabling the stage as
such, we avoid a disruptive edge to propagate through the loop,
which may cause racing effects with two edges. Delayed by a
time a pulse forces the output of the cell to the dif-
ferential supply rails, which restarts the oscillation.
Once the clean edge is injected in the loop, the falling edges
of and re-enable the delay cell and release its output. Con-
veniently, the alignment control signals are thus merely two de-

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1946
Fig. 9. Chip micrograph.
layed pulses and created at the reference edge. Notice that
the simplicity in the realignment control is also beneficial since
it reduces the number of sources for noise.
The pulses should only be narrower than (250 ps @
2 GHz) and can fairly easily be created in contemporary CMOS
as depicted in Fig. 8(a). A single-ended reference edge is con-
verted into a pulse, using a variable delay cell and a NAND op-
eration. Next, the single-ended pulse is converted into a differ-
ential one using an additional delay stage. Two-stage regenera-
tion removes the delay between both signals to turn the pulse in
a pure differential one. The output serves as the control voltage
, while an additional delay stage delivers . In the generation
of these control pulses, only a few delay cells are used, which
limits the jitter added to the reference. In our design, both the
pulse’s slew rate and width are tunable to adapt both the realign-
ment strength and open-loop duration.
In this design the oscillator is completely stopped and
restarted rather than being steered through injection locking
(e.g., [1]). Therefore we achieve complete realignment. In con-
trast with solutions in literature (e.g., [3]), the proposed timing
scheme is simpler (inherently no feedback) and compliant with
sub-1 V operation (see measurements). The latter is mostly
thanks to the relaxed timing requirements, and the low number
of stacked devices. Notice that the simplicity also lowers the
number of sources for noise. Keeping the realignment circuitry
chain short is crucial to avoid jitter being built up in the refer-
ence. For the same reason, this circuitry consumes a relevant
fraction of the power.
VI. IMPLEMENTATION AND MEASUREMENTS
The circuit has been realized in a 90 nm digital CMOS
process, at a 1 V supply voltage. Since there is a direct correla-
tion between voltage swing and phase noise, a lowered supply
voltage requires more current to retrieve low phase noise. The
chip, with an active area of only 0.008 mm (Fig. 9) has been
measured mounted on a PCB.
The free-running VCO has a tuning range of 0.96 to 2 GHz at
1 V, and 210 to 400 MHz at 0.5 V. The measured I-Q imbalance
is around 2 over the whole tuning range.
Fig. 10 shows spectrum plots of the PARO, running at
960 MHz, realigned at 20 MHz and 320 MHz. From these
spectra, it can be seen how the reference spurs, due to the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009
Fig. 10. Measured spectrum of the locked oscillator, running at 960 MHz, re-
0
aligned at 20 MHz (left) and 320 MHz (right). Spurs are at 40 dBc.
Fig. 11. Measured phase noise of the PARO running at 2 GHz for different
realignment frequencies (noted next to the curve), as well as the measured phase
noise of the reference source. Towards lower offset frequencies, the reference
source limits the phase noise.
realignment, can be pushed farther off (where they may be
less harmful), increasing the reference frequency. The latter
will also benefit the phase noise, since noise is truncated from
higher offset frequencies.
In both cases, the spurs are found at 40 dBc. Similar spur
values have been measured at every frequency of operation.
Some modifications may improve the spurious performance.
During measurement, the oscillator has been manually tuned to
be a multiple of the reference frequency, since a PLL was not
available. Such PLL may achieve better lock, and lower spurs,
as discussed in Section IV. Also, spurious tones are known to
appear due to insufficient isolation between reference and car-
rier frequency [5]. All blocks in the PARO operate at a single
supply. Running the realignment circuitry at a different supply
may improve isolation, and thus lower spurious performance.
Fig. 11 shows the shaped phase noise spectrum for different
realignment frequencies, at 2 GHz operation. Clearly, increasing
the realignment frequency pushes the phase noise down. For
2 GHz and 950 MHz operation, Fig. 12 plots the phase noise
versus the realignment frequency. The 20 dB/decade roll-off
confirms the expected theoretical improvement from (8). At low
frequency offsets, the noise hits the noise floor of the source
used in this experiment. Similarly, the noise floor of the spec-
trum analyzer is almost reached.
At a supply of 0.5 V, the performance of the oscillator, now
running at a lower frequency, is not deteriorated. Its phase noise
BORREMANS et al.: A LOW-COMPLEXITY, LOW-PHASE-NOISE, LOW-VOLTAGE PHASE-ALIGNED RING OSCILLATOR IN 90 nm DIGITAL CMOS
TABLE I
PERFORMANCE COMPARISON (* INCLUDES A PLL, ** INCLUDES OUTPUT BUFFERS, *** MEASURED AT THE FLAT PHASE-NOISE REGION OF THE SOURCE)
Fig. 12. Measured phase noise vs. the realignment frequency operating at 2
GHz and 957 MHz. The phase noise at 100 kHz is limited by the reference
source.
is similar as when operating at a 1 V supply, while the circuit
consumes very low power (1.8 mW). This demonstrates that
the technique is robust and is compatible with low voltage and
low power applications. Fig. 3 illustrates the jitter truncation
by realignment on a real-time capture around the realignment
instant, on a high-frequency digitizing oscilloscope with high
persistency, running at a 0.5 V supply.
Table I lists a performance summary. The proposed PARO
achieves a combination of the lowest phase noise at the highest
frequency, for the lowest complexity and a low power consump-
tion (although other solutions include a PLL), on the lowest
area, with the most phases available. Further, the PARO needs
a lower reference frequency than other solutions that achieve
similar phase noise. It should be noted that at 100 kHz offset,
the phase noise is limited by the reference source available to
the authors. A reference source with higher spectral purity will
lower phase noise at these offset frequencies.
VII. APPLICATION AND CONCLUSIONS
In this work, we presented a low-complexity, phase-aligned
ring oscillator. Very low phase noise is achieved: flat
120 dBc Hz in-band phase noise for a low-power ring
oscillator. Fig. 13 illustrates the phase noise of the free-running
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1947
Fig. 13. Measured phase noise of the PARO running at 1.076 GHz free-run-
ning, and realigned at 40 MHz. Also indicated are some mask requirements of
different standards, scaled to the operating frequency.
oscillator at 1.076 GHz. Clearly, this oscillator can never meet
the mask specifications. Note that the filtering effect of a PLL’s
bandwidth cannot suppress the phase noise at 1 MHz offset.
Fig. 13 also shows the phase noise with the realignment at
40 MHz turned on, showing significant improvement. Also
plotted in Fig. 13 are the spectral mask requirements of some
standards, scaled to the frequency of operation (in this case
scaled to 1 GHz). Clearly, while the non-realigned oscillator
was incapable of meeting the WLAN requirements, the re-
aligned oscillator is able to do so. As such, an inductorless
oscillator may one day be used for WLAN-like applications.
Some issues are however unaddressed. The spurious per-
formance may cause ill performance. However, using a high
reference frequency—while even beneficial for the phase
noise—pushed the spurs father off the reference, where they
may be less harmful, or can be more easily filtered. Sec-
ondly, only integer multiples of the reference frequency can
be synthesized. The oscillator can still be useful in a block
downconversion scheme, where all bands are down converted
1948
simultaneously. These can be simultaneously digitized, al-
lowing for concurrent operation and filtering in the digital
domain (e.g., [11]).
While application in wireless radios may require further de-
velopment, the presented low-complexity PARO is still a very
good low-jitter clock multiplier, which is readily applicable in
the applications of [1]–[6].
In conclusion, a low-complexity, low-phase noise,
low-voltage reference-aligned ring oscillator has been pre-
sented, along with theory. While the circuit is readily compat-
ible with the applications of [1]–[3], it may also be a possible
step on the path towards a true all-digital wireless transceiver
in plain digital CMOS.
ACKNOWLEDGMENT
The authors would like to thank G. Van der Plas for the tech-
nical discussions.
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[11] L. J. Breems, R. Rutten, R. H. M. van Veldhoven, and G. van der Weide,
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Jonathan Borremans (S’06–M’08) received the
M.Sc. and Ph.D. degrees in electrical engineering at
the Vrije Universiteit Brussel in Brussels, Belgium,
in 2004 and 2008, respectively, in collaboration with
IMEC, Belgium.
He joined IMEC’s wireless group, where his re-
search interests are analog, mixed-signal and RF cir-
cuit design for multi-standard radios and millimeter-
wave applications, in advanced CMOS technologies.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009
Julien Ryckaert (S’06–M’07) received the M.Sc.
degree in electrical engineering from the University
of Brussels (ULB), Belgium, in 2000 and the Ph.D.
degree from the Vrije Universiteit Brussel (VUB) in
2007.
He joined IMEC, Leuven, Belgium, in 2000 as
an RF designer for WLAN transceivers. From 2003
on, he worked as system architect for low-power
low data rate ultra-wideband transceivers in which
he completed his Ph.D. He is now heading a project
on innovative wireless transceiver architectures for
cognitive radio. He has authored or co-authored about 30 articles in various
IEEE conferences and journals.
Claude Desset (S’94–M’97) was born in Bastogne,
Belgium, in 1974. He graduated (summa cum
laude) as an electrical engineer from the Université
catholique de Louvain (UCL), Louvain-la-Neuve, in
1997, and a Ph.D. degree from the same university
in 2001, funded by the Belgian national fund for
scientific research (FNRS). His doctoral research
mainly included joint source-channel coding for
image transmissions, focusing on unequal error
protection, global optimization of a transmission
chain, and image reconstruction from incomplete
data. He also worked in channel coding, especially bit error rate approximation
of error-correcting codes and code selection for specific applications.
In 2001, he joined IMEC, Leuven, Belgium, to work as a Senior Researcher
in the design of ultra-low-power wireless communication systems. He focused
on body area networks, developing ultra-wideband solutions and optimizing
the power at system level by considering both air interface and front-end ar-
chitecture. He also worked in MIMO communications, link adaptation, and
turbo coding/processing. Since 2006, he works in a cross-disciplinary team tack-
ling power-performance optimization of wireless terminals by tuning all the
components to the current conditions and requirements in order to achieve the
system-wide optimum.
Maarten Kuijk (M’95) was born in Canada in 1965.
He received the Ph.D. degree in electrical engi-
neering from the Vrije Universiteit Brussels (VUB),
Belgium, in 1993 on the subject of optoelectronic
thyristor devices in III-V semiconductors.
In 1994, he became Assistant Professor at the
VUB in the field of integrated electronics and
optoelectronics and was additionally appointed Re-
search Associate for the fund for scientific research
Flanders (FWO-V) in 1997. In 2000, he became a
Professor in electrical engineering at the ETRO de-
partment of the VUB. His current research topics include electrical and optical
interconnects devices and building blocks, optical components and sensors,
CMOS and SiGe-BICMOS circuits. He has authored or co-authored more than
60 international refereed publications, holding 16 international patents with
six patents pending. He co-founded the VUB spin-off EqcoLogic that sells
equalizer circuits in CMOS for a number of leading electrical communication
standards.
Piet Wambacq (S’89–M’91) received the M.Sc. de-
gree in electrical engineering and the Ph.D. degree
from the Katholieke Universiteit Leuven, Belgium,
in 1986 and 1996, respectively.
Since 1996, he is with IMEC, Heverlee, Belgium,
working as a principal scientist on RF CMOS design
for wireless applications. He is a Lecturer at the Uni-
versity of Brussels (Vrije Universiteit Brussel). He
has authored or coauthored two books and more than
150 papers in editedbooks, international journals, and
conference proceedings.
Dr. Wambacq has been an Associate Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS from 2002 to 2004. He is the co-recipient of the Best
BORREMANS et al.: A LOW-COMPLEXITY, LOW-PHASE-NOISE, LOW-VOLTAGE PHASE-ALIGNED RING OSCILLATOR IN 90 nm DIGITAL CMOS 1949

Paper Award at the Design, Automation and Test Conference (DATE) in 2002 2002, he joined IMEC, Leuven, Belgium, where he currently is the Chief Sci-
and 2005. He is a member of the ESSCIRC technical program committee. entist of the analog wireless research group. His research focuses on the design
of RF transceiver front-ends for software-defined radio (SDR) systems, covering
all aspects of RF, analog and data converter design.
Dr. Craninckx has authored and co-authored more than 50 papers, several
Jan Craninckx (S’92–M’98–SM’07) received the book chapters and has published one book in the field of analog and RF IC de-
M.S. and Ph.D. degrees in microelectronics from sign. He is the inventor of 10 patents, and is a member of the Technical Program
the ESAT-MICAS Laboratories of the Katholieke Committee for both the ISSCC and ESSCIRC conferences.
Universiteit Leuven, Belgium, in 1992 and 1997,
respectively. His Ph.D. work was on the design
of low-phase-noise CMOS integrated VCOs and
synthesizers.
From 1997 to 2002, he worked with Alcatel Mi-
croelectronics (now part of STMicroelectronics) as a
Senior RF Engineer on the integration of RF trans-
ceivers for GSM, DECT, Bluetooth and WLAN. In

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