MEMORY

Choosing DDR memory

power supply IC
By Norman Chan
Marketing Manager

WS Wong
System Engineer

Freescale Semiconductor Inc.

DDR memory is important and

widely used because applica-
tions requiring fast processing of
large amounts of data—be it a
computer, a server or a gaming
system—require RAM. Its charac-
teristics allow volatile information
to be held and accessed in a fast
and direct way as demanded by
computer systems today.
CPU clock rates have grown
exponentially over the years, and
this has fuelled a corresponding
Figure 1: Data transfer rate has gotten much faster from the first SDRAM devices in 1997 to the DDR3 SDRAM in 2006.
growth in the clock rates of RAM
devices. The evolution of DRAM
devices is shown in Figure 1.
DDR DRAM allows data to be
fetched on both the rising and
falling edges of the clock cycle,
thus doubling the effective trans-
fer rate of the ICs. This is in con-
trast to the older single data rate
SDRAM that fetches data on only
one edge of the clock cycle. For
example, a 100MHz DDR DRAM
would achieve a peak transfer
rate equal to that of a 200MHz
clock. Because of this, DDR1 tech-
nology allowed for data transfer
rates of up to 400MHz. As seen in Figure 2: Shown is the stub series-termination-logic topology for DDR SDRAM.
the diagram, the latest standard
DDR3 brings data transfer rates of
Items DDR3 SDRAM DDR2 SDRAM DDR SDRAM
up to 1.6Gbit/s.
Clock frequency 400/533/667/ 800MHz 200/266/333/400MHz 100/133/166/200MHz
Aside from PC applications,
Transfer data rate 800/1066/1333/ 1600Mbps 400/533/667/800Mbps 200/266/333/400Mbps
DDR DRAM devices are widely
used in high-speed and memory- I/O width x4/x8/x16 x4/x8/x16 x4/x8/x16/x32
demanding applications such Prefetch bit width 8-bits 4-bits 2-bits
as graphic cards, blade servers, Clock input Differential clock Differential clock Differential clock
networking devices and com- Burst length 8, 4 (Burst chop) 4, 8 2, 4, 8
munication devices. The por- Data strobe Differential data strobe Differential data strobe Single data strobe
table device market segment, in Supply voltage 1.5V 1.8V 2.5V
particular, demands both higher Interface SSTL_15 SSTL_18 SSTL_2
speed and lower operating volt- /CAS latency (CL) 5, 6, 7, 8, 9, 10 clock 3, 4, 5 clock 2, 2.5, 3 clock
ages from DRAM modules. More On die termination (ODT) Supported Supported Unsupported
and more portable electronic Component package FBGA FBGA TSOP(II) / FBGA / LQFP
gadgets provide for graphics
and video capability that need Table 1: Shown is a comparison of the DDR memory standards.

EE Times-Asia | February 16-29, 2008 | eetasia.com 


VDDQ
Controller
Figure 3: The power source of VTT needs both sink current and source current.
DRAM modules. These include
handheld game consoles, smart
phones, digital cameras and GPS
devices. In these applications,
power consumption needs to be
kept as low as possible to increase
battery runtime.
The difference
The main differences between
DDR1, DDR2 and DDR3 standards
for SDRAM are shown in Table
1. Notice that DDR1, DDR2 and
DDR3 are powered up with sup-
ply voltages of 2.5-, 1.8- and 1.5V
respectively. This is less than the
supply voltage of 3.3V required
by SDRAM chipsets. In addi-
5V or 3.3V
VDDQ
VREF
MC34716
VTT
Figure 4: VTT for the data bus is generated within the memory via ODT (on-die termination) by VDDQ.
 eetasia.com | February 16-29, 2008 | EE Times-Asia
VTT
Terminal resistor
VREF
Stub resistors
tion, DDR3 uses 16 percent less
power than DDR2. Both DDR2
and DDR3 devices have power-
saving features such as smaller
page sizes and an active power
down mode. Furthermore, DDR
memory interfaces use the stub
series-termination-logic (SSTL)
topology, which improves noise
immunity, increases power-sup-
ply rejection and reduces power
dissipation due to a lower-volt-
age rail. One more point worth
noting is that DDR3 and DDR2
SDRAM support On-Die Termina-
tion, which is not supported by
DDR1. These features and power
consumption advantages make
Terminal resistance for the
address bus control signal is
needed basically even
with DDR2
Memory
controller
VDDQ
DDR SDRAM
– 18) define the V DDQ , V TT and
+ specifications to meet noise
them especially suitable for use in
notebook computers, servers and
low-power mobile applications.
In summary, the main dif-
ferences between SDRAM and
DDR SDRAM are found in power
supply voltage, interface and
data transfer frequency. The DDR
SDRAM system requires three
power supply voltage sources:
VDDQ, VTT and VREF, as shown in
Table 2.
These three types of power
supply voltage are needed be-
cause while DDR technology
doubles the data-transfer rate
without doubling the clock rate
and while avoiding PCB design
… built-in for data
…
Data bus
…
Address bus control signal
and layout complexity, the SSTL
topology was introduced to
improve noise immunity, in-
crease power-supply rejection
and reduce power dissipation
for a lower-voltage rail. The
JEDEC standards JESD8-9A (for
SSTL_2) and JESD 8-15 (for SSTL_
VREF, as well as driver/receiver
margins at V DDQ = 2.5V for
DDR1 and VDDQ =1.8V for DDR2,
respectively.
SSTL interface
The SSTL topology of DDR memo-
ry is shown in Figure 2. The inter-
face of SSTL_2 has the following
features:
• DDR memory has a push-pull
output buffer, while the input
receiver is a differential stage
requiring a reference bias
midpoint, VREF. Therefore, it
requires an input voltage ter-
mination capable of sourcing
as well as sinking current.
• Between any output buffer
from the driving chipset and
the corresponding input re-
ceiver on the memory module,
we must terminate a routing
trace or stub with resistors.
The current flow direction of
the VTT power source changes
Terminal
resistance
bus (ODT)
ODT
DDR2
SDRAM
as the state of the bus changes.
Thus, the power source of V TT
needs both sink current and
source current as illustrated with
red and blue arrows in Figure 3.
Since the V TT supply must
sink and source current at ½
V DDQ , a standard switching
power supply cannot be used
without a shunt to allow for the
supply to sink current. Further-
more, as each data line is con-
nected to VTT with relatively low
impedance, the supply must be
extremely stable. Any noise on
this supply can go directly onto
the data lines.
The bus signal swings across
VTT voltage around the center.
When the bus signal voltage
Figure 5: The MC34716 is an example of a DDR memory power supply IC from Freescale Semiconductor Inc.
exceeds the threshold voltage of
the comparator, it will output an
inverted image of the signal. In 　 SDRAM DDR1 DDR2 DDR3
this system, the threshold voltage
of the comparator is the VREF volt- Power supply
VDDQ = 2.5V VDDQ = 1.8V VDDQ = 1.5V
age provided by the power supply 3.3V VTT = 1/2 x VDDQ VTT = 1/2 x VDDQ VTT = 1/2 x VDDQ
voltage
VREF = 1/2 x VDDQ VREF = 1/2 x VDDQ VREF = 1/2 x VDDQ
source. As there is hysteresis in
the comparator, the image of the Interface LVTTL SSTL_2 SSTL_18 SSTL_15
signal will have a time shift.
Data transfer The same as 2 times that 2 times that operational 2 times that operational
frequency operational frequency operational frequency frequency frequency
Typical connection
An example of how the DDR
bus is connected for a typical Table 2: DDR SDRAM systems require three power supply sources.
DDR2 system is shown in Figure
4. VTT for the data bus is gener- the memory is sufficiently short— • What power conversion ef- pability and voltage tracking
ated within the memory via ODT for example, below 63.5mm—the ficiency can the DDR memory features that are specific to
(on-die termination) by V DDQ . terminal resistance is not needed power supply IC offer? Most DDR memory devices?
However, it is still necessary to and consequently no VTT supply vendors provide efficiency of • How will the package size of
supply VTT from power source IC is required. at least 90 percent and above. the power supply IC affect the
to the address bus control signal. Higher efficiency translates size of the end product? This
For DDR2 memory, the terminal Selection process to less loss of precious power is particularly important for
resistances for the data buses are One must weigh the costs against sources coming from batter- space-constrained applica-
built-in, but terminal resistance performance, as well as consider ies in portable products. tions like portable consumer
for the address bus control signal other technical requirements in- • Is the switching frequency products.
is still needed as it is in the case of cluding input voltages and output sufficiently high? Higher fre- • Are there extensive controls
DDR1. VTT supply is derived from currents in choosing a DDR mem- quency means smaller-value and interfaces that can offer
the power supply chip—here ory power supply IC. Assuming external inductors and ca- the designer the flexibility of
marked as MC34716. that the electrical specification is pacitors can be used, and the many control and protection
Note when the conductor already fixed, the choices of DDR device would be smaller. functions? This would allow
length of the address bus control power supply ICs depend on the • Does the power supply IC for easy implementation of
signal between the controller and following factors: provide sink and source ca- complex designs.

EE Times-Asia | February 16-29, 2008 | eetasia.com