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PRELIMINARY
DS12C887
Real Time Clock
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DS12C887
OPERATION
The block diagram in Figure 1 shows the pin connec- The following paragraphs describe the function of each
tions with the major internal functions of the DS12C887. pin.
CS
POWER
VCC SWITCH VCC
AND PERIODIC INTERRUPT/SQUARE WAVE
WRITE POK SELECTOR
VBAT
PROTECT
SQUARE SQW
WAVE OUT
CS
IRQ
RESET
REGISTERS A,B,C,D
DS
DOUBLE
R/W BUFFERED
CLOCK/ CLOCK, CALENDAR,
CALENDAR AND ALARM RAM
AS BUS UPDATE
INTERFACE
ADO–
AD7
BCD/
BINARY
INCREMENT
USER RAM
MOT
113 BYTES
CENTURY BYTE
POWER–DOWN/POWER–UP VCC falls below 4.25 volts, the chip select input is inter-
CONSIDERATIONS nally forced to an inactive level regardless of the value of
The Real Time Clock function will continue to operate CS at the input pin. The DS12C887 is, therefore, write–
and all of the RAM, time, calendar, and alarm memory protected. When the DS12C887 is in a write–protected
locations remain nonvolatile regardless of the level of state, all inputs are ignored and all outputs are in a high
the VCC input. When VCC is applied to the DS12C887 impedance state. When VCC falls below a level of
and reaches a level of greater than 4.25 volts, the device approximately 3 volts, the external VCC supply is
becomes accessible after 200 ms, provided that the switched off and an internal lithium energy source sup-
oscillator is running and the oscillator countdown chain plies power to the Real Time Clock and the RAM
is not in reset (see Register A). This time period allows memory.
the system to stabilize after power is applied. When
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DS12C887
SIGNAL DESCRIPTIONS
GND, VCC – DC power is provided to the device on VCC, Motorola bus timing is selected. When connected
these pins. VCC is the +5 volt input. When 5 volts are to GND or left disconnected, Intel bus timing is selected.
applied within normal limits, the device is fully accessi- The pin has an internal pull-down resistance of approxi-
ble and data can be written and read. When VCC is mately 20KΩ.
below 4.25 volts typical, reads and writes are inhibited.
However, the timekeeping function continues unaf- SQW (Square Wave Output) – The SQW pin can out-
fected by the lower input voltage. As VCC falls below 3 put a signal from one of 13 taps provided by the 15 inter-
volts typical, the RAM and timekeeper are switched nal divider stages of the Real Time Clock. The fre-
over to an internal lithium energy source. The timekeep- quency of the SQW pin can be changed by
ing function maintains an accuracy of ±1 minute per programming Register A as shown in Table 1. The SQW
month at 25°C regardless of the voltage input on the signal can be turned on and off using the SQWE bit in
VCC pin. Register B. The SQW signal is not available when VCC
is less than 4.25 volts typical.
MOT (Mode Select) – The MOT pin offers the flexibility
to choose between two bus types. When connected to
0 0 0 0 None None
0 0 0 1 3.90625 ms 256 Hz
0 0 1 0 7.8125 ms 128 Hz
0 0 1 1 122.070 s 8.192 kHz
0 1 0 0 244.141 s 4.096 kHz
0 1 0 1 488.281 s 2.048 kHz
0 1 1 0 976.5625 s 1.024 kHz
0 1 1 1 1.953125 ms 512 Hz
1 0 0 0 3.90625 ms 256 Hz
1 0 0 1 7.8125 ms 128 Hz
1 0 1 0 15.625 ms 64 Hz
1 0 1 1 31.25 ms 32 Hz
1 1 0 0 62.5 ms 16 Hz
1 1 0 1 125 ms 8 Hz
1 1 1 0 250 ms 4 Hz
1 1 1 1 500 ms 2 Hz
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DS12C887
AD0–AD7 (Multiplexed Bidirectional Address/Data mode the R/W pin has the same meaning as the Write
Bus) – Multiplexed buses save pins because address Enable signal (WE) on generic RAMs.
information and data information time share the same
signal paths. The addresses are present during the first CS (Chip Select Input) – The Chip Select signal must
be asserted low for a bus cycle in the DS12C887 to be
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the cycle. accessed. CS must be kept in the active state during DS
Address/data multiplexing does not slow the access time and AS for Motorola timing and during RD and WR for
of the DS12C887 since the bus change from address to Intel timing. Bus cycles which take place without
data occurs during the internal RAM access time. asserting CS will latch addresses but no access will
Addresses must be valid prior to the falling edge of AS/ occur. When VCC is below 4.25 volts, the DS12C887
ALE, at which time the DS12C887 latches the address internally inhibits access cycles by internally disabling
from AD0 to AD6. Valid write data must be present and the CS input. This action protects both the real time
held stable during the latter portion of the DS or WR clock data and RAM data during power outages.
pulses. In a read cycle the DS12C887 outputs 8 bits of IRQ (Interrupt Request Output) – The IRQ pin is an
data during the latter portion of the DS or RD pulses. The active low output of the DS12C887 that can be used as
read cycle is terminated and the bus returns to a high an interrupt input to a processor. The IRQ output remains
impedance state as DS transitions low in the case of low as long as the status bit causing the interrupt is pres-
Motorola timing or as RD transitions high in the case of ent and the corresponding interrupt–enable bit is set. To
Intel timing. clear the IRQ pin the processor program normally reads
the C register. The RESET pin also clears pending
AS (Address Strobe Input) – A positive going address interrupts.
strobe pulse serves to demultiplex the bus. The falling
edge of AS/ALE causes the address to be latched within When no interrupt conditions are present, the IRQ level is
the DS12C887. The next rising edge that occurs on the in the high impedance state. Multiple interrupting devices
AS bus will clear the address regardless of whether CS can be connected to an IRQ bus. The IRQ bus is an open
is asserted. Access commands should be sent in pairs. drain output and requires an external pull–up resistor.
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DS12C887
In a typical application RESET can be connected to control and status. All 128 bytes can be directly written
VCC. This connection will allow the DS12C887 to go in or read except for the following:
and out of power fail without affecting any of the control
registers. 1. Registers C and D are read–only.
2. Bit 7 of Register A is read–only.
ADDRESS MAP 3. The high order bit of the seconds byte is read–only.
The address map of the DS12C887 is shown in
Figure 2. The address map consists of 113 bytes of user The contents of four registers (A,B,C, and D) are
RAM, 11 bytes of RAM that contain the RTC time, calen- described in the “Registers” section.
dar, and alarm data, and four bytes which are used for
0 00 0 SECONDS
2 MINUTES
13 0D
14 0E 3 MINUTES ALARM
4 HOURS
8 MONTH
9 YEAR
10 REGISTER A
11 REGISTER B
12 REGISTER C
127 7F 13 REGISTER D
50 CENTURY
TIME, CALENDAR AND ALARM LOCATIONS of Register B must be set to the appropriate logic level.
The time and calendar information is obtained by read- All ten time, calendar, and alarm bytes must use the
ing the appropriate memory bytes. The time, calendar, same data mode. The set bit in Register B should be
and alarm are set or initialized by writing the appropriate cleared after the data mode bit has been written to allow
RAM bytes. The contents of the ten time, calendar, and the real time clock to update the time and calendar
alarm bytes can be either Binary or Binary–Coded Deci- bytes. Once initialized, the real time clock makes all
mal (BCD) format. Before writing the internal time, cal- updates in the selected mode. The data mode cannot
endar, and alarm registers, the SET bit in Register B be changed without reinitializing the ten data bytes.
should be written to a logic one to prevent updates from Table 2 shows the binary and BCD formats of the ten
occurring while access is being attempted. In addition time, calendar, and alarm locations. The 24–12 bit can-
to writing the ten time, calendar, and alarm registers in a not be changed without reinitializing the hour locations.
selected format (binary or BCD), the data mode bit (DM) When the 12–hour format is selected, the high order bit
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DS12C887
of the hours byte represents PM when it is a logic one. minutes, and seconds alarm locations, the alarm inter-
The time, calendar, and alarm bytes are always acces- rupt is initiated at the specified time each day if the alarm
sible because they are double buffered. Once per enable bit is high . The second use condition is to insert
second the eleven bytes are advanced by one second a “don’t care” state in one or more of the three alarm
and checked for an alarm condition. If a read of the time bytes. The “don’t care” code is any hexadecimal value
and calendar data occurs during an update, a problem from C0 to FF. The two most significant bits of each byte
exists where seconds, minutes, hours, etc. may not cor- set the “don’t care” condition when at logic 1. An alarm
relate. The probability of reading incorrect time and cal- will be generated each hour when the “don’t care” bits
endar data is low. Several methods of avoiding any pos- are set in the hours byte. Similarly, an alarm is gener-
sible incorrect time and calendar reads are covered ated every minute with “don’t care” codes in the hours
later in this text. and minute alarm bytes. The “don’t care” codes in all
three alarm bytes create an interrupt every second.
The three alarm bytes can be used in two ways. First,
when the alarm time is written in the appropriate hours,
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DS12C887
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DS12C887
internal copy of the buffer. This feature allows time to progress. The UIP bit will pulse once per second. After
maintain accuracy independent of reading or writing the the UIP bit goes high, the update transfer occurs 244 µs
time, calendar, and alarm buffers and also guarantees later. If a low is read on the UIP bit, the user has at least
that time and calendar information is consistent. The 244 µs before the time/calendar data will be changed.
update cycle also compares each alarm byte with the Therefore, the user should avoid interrupt service rou-
corresponding time byte and issues an alarm if a match tines that would cause the time needed to read valid
or if a “don’t care” code is present in all three positions. time/calendar data to exceed 244 µs.
There are three methods that can handle access of the The third method uses a periodic interrupt to determine
real time clock that avoid any possibility of accessing if an update cycle is in progress. The UIP bit in Register
inconsistent time and calendar data. The first method A is set high between the setting of the PF bit in Register
uses the update–ended interrupt. If enabled, an inter- C (see Figure 3). Periodic interrupts that occur at a rate
rupt occurs after every up date cycle that indicates that of greater than tBUC allow valid time and date informa-
over 999 ms are available to read valid time and date tion to be reached at each occurrence of the periodic
information. If this interrupt is used, the IRQF bit in Reg- interrupt. The reads should be complete within 1
ister C should be cleared before leaving the interrupt ( t PI/ + tBUC) to ensure that data is not read during the
2
routine. update cycle.
UIP BIT IN
REGISTER A
tBUC
UF BIT IN
REGISTER B
t PI/ t PI/
2 2
PF BIT IN
REGISTER C
tPI
REGISTERS for access when the UIP bit is zero. The UIP bit is read
The DS12C887 has four control registers which are only and is not affected by RESET. Writing the SET bit in
accessible at all times, even during the update cycle. Register B to a one inhibits any update transfer and
clears the UIP status bit.
REGISTER A
MSB LSB DV0, DV1, DV2
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 These three bits are used to turn the oscillator on or off
UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 and to reset the countdown chain. A pattern of 010 is the
only combination of bits that will turn the oscillator on
and allow the RTC to keep time. A pattern of 11X will
UIP enable the oscillator but holds the countdown chain in
The Update In Progress (UIP) bit is a status flag that can
reset. The next update will occur at 500 ms after a pat-
be monitored. When the UIP bit is a one, the update
tern of 010 is written to DV0, DV1, and DV2.
transfer will soon occur. When UIP is a zero, the update
transfer will not occur for at least 244 µs. The time, cal-
endar, and alarm information in RAM is fully available
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DS12C887
RS3, RS2, RS1, RS0 each second that the three time bytes equal the three
These four rate–selection bits select one of the 13 taps alarm bytes including a “don’t care” alarm code of binary
on the 15–stage divider or disable the divider output. 11XXXXXX. When the AIE bit is set to zero, the AF bit
The tap selected can be used to generate an output does not initiate the IRQ signal. The RESET pin clears
square wave (SQW pin) and/or a periodic interrupt. The AIE to zero. The internal functions of the DS12C887 do
user can do one of the following: not affect the AIE bit.
SET
When the SET bit is a zero, the update transfer functions DM
normally by advancing the counts once per second. The Data Mode (DM) bit indicates whether time and cal-
When the SET bit is written to a one, any update transfer endar information is in binary or BCD format. The DM bit
is inhibited and the program can initialize the time and is set by the program to the appropriate format and can
calendar bytes without an update occurring in the midst be read as required. This bit is not modified by internal
of initializing. Read cycles can be executed in a similar functions or RESET. A one in DM signifies binary data
manner. SET is a read/write bit that is not modified by while a zero in DM specifies Binary Coded Decimal
RESET or internal functions of the DS12C887. (BCD) data.
PIE 24/12
The periodic interrupt enable PIE bit is a read/write bit The 24/12 control bit establishes the format of the hours
which allows the Periodic Interrupt Flag (PF) bit in Reg- byte. A one indicates the 24–hour mode and a zero indi-
ister C to drive the IRQ pin low. When the PIE bit is set to cates the 12–hour mode. This bit is read/write and is not
one, periodic interrupts are generated by driving the affected by internal functions of RESET.
IRQ pin low at a rate specified by the RS3–RS0 bits of
Register A. A zero in the PIE bit blocks the IRQ output
DSE
from being driven by a periodic interrupt, but the Peri- The Daylight Savings Enable (DSE) bit is a read/write bit
odic Flag (PF) bit is still set at the periodic rate. PIE is not which enables two special updates when DSE is set to
modified by any internal DS12C887 functions, but is one. On the first Sunday in April the time increments
cleared to zero on RESET. from 1:59:59 AM to 3:00:00 AM. On the last Sunday in
October when the time first reaches 1:59:59 AM it
changes to 1:00:00 AM. These special updates do not
AIE
The Alarm Interrupt Enable (AIE) bit is a read/write bit occur when the DSE bit is a zero. This bit is not affected
which, when set to a one, permits the Alarm Flag (AF) bit by internal functions or RESET.
in register C to assert IRQ. An alarm interrupt occurs for
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DS12C887
IRQF PF AF UF 0 0 0 0
UF
The Update Ended Interrupt Flag (UF) bit is set after
IRQF each update cycle. When the UIE bit is set to one, the
The Interrupt Request Flag (IRQF) bit is set to a one one in UF causes the IRQF bit to be a one which will
when one or more of the following are true: assert the IRQ pin. UF is cleared by reading Register C
or a RESET.
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1 BIT 0 THROUGH BIT 3
These are unused bits of the status Register C. These
That is, IRQF = PF • PIE + AF • AIE + UF • UIE. bits always read zero and cannot be written.
Any time the IRQF bit is a one, the IRQ pin is driven low.
REGISTER D
All flag bits are cleared after Register C is read by the
MSB LSB
program or when the RESET pin is low.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VRT 0 0 0 0 0 0 0
PF
The Periodic Interrupt Flag (PF) is a read–only bit which
VRT
is set to a one when an edge is detected on the selected
The Valid RAM and Time (VRT) bit is set to the one state
tap of the divider chain. The RS3 through RS0 bits
by Dallas Semiconductor prior to shipment. This bit is
establish the periodic rate. PF is set to a one indepen-
not writable and should always be a one when read. If a
dent of the state of the PIE bit. When both PF and PIE
zero is ever present, an exhausted internal lithium
are ones, the IRQ signal is active and will set the IRQF
energy source is indicated and both the contents of the
bit. The PF bit is cleared by a RESET or a software read
RTC data and RAM data are questionable. This bit is
of Register C.
unaffected by RESET.
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DS12C887
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
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DS12C887
NOTES:
1. All voltages are referenced to ground.
4. Applies to the AD0–AD7 pins, the IRQ pin,and the SQW pin when each is in the high impedance state.
7. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. However,
post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used
to prevent damage to the crystal.
012899 12/17
DS12C887
1.1 KW
D.U.T.
50 pF
680W
AS
tASD
tCYC
PWEL PWEH
DS
tRWS tRWH
R/W
tCS tCH
CS
tAHL tDSW
tASL tDHW
AD0–AD7
WRITE
tASL
tAHL tDHR
AD0–AD7
READ
tDDR
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DS12C887
ALE PWASH
(AS PIN)
tASD
RD
(DS PIN)
tASD
tASED
PWEH
PWEL
WR
(R/W PIN)
tCS
tCH
CS
tAHL
AD0–AD7
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DS12C887
ALE PWASH
(AS PIN)
tASD
tASED
PWEH
RD PWEL
(DS PIN)
tASD
WR
(R/W PIN)
tDDR
tCS
tCH
CS
tAHL
tASL tDHR
AD0–AD7
DS
tRWL
RESET
IRQ
tIRDS tIRR
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DS12C887
4.50V
3.2V
tF tR
tPD tREC
CS
DATA RETENTION
CURRENT SUPPLIED tDR
FROM INTERNAL
LITHIUM ENERGY CELL
(tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention tDR 10 years
NOTE:
The real time clock will keep time to an accuracy of +1 minute per month during data retention time for the period of tDR.
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
012899 16/17
DS12C887
1 12
A
C E
F J
D K G H
B
11 EQUAL SPACES AT
±
.100 .010 TNA
012899 17/17