IMPORTANT QUESTION IN FIRST THREE UNITS OF VLSI DESIGN

Dt:5/3/11.
Unit 1:
1. With neat sketches, explain in detail, all the steps involved in electron lithography process.
2. (a) What are the steps involved in the nMOS fabrication?
(b) In what way PMOS fabrication is different from nMOS fabrication.
(c) Which fabrication is preferred and why?
3. With neat sketches explain BICMOS fabrication process
4. Describe probe testing in VLSI design process
5.write in detail fabrication of pmos?
6.explain the fabrication of cmos in p-well process?
Unit.2
1. (a) Define the threshold voltage of a MOS device and explains its significance.
(b) Explain the effect of threshold voltage on MOSFET current equation.
2. (a) Derive an equation for Transconductance of an n channel enhancement MOS- FET operating in active region.
(b) A PMOS transistor is operated in triode region with the following parameters.
VGS=- 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, μnCox =95μA/V 2. Find its drain current and drain source
resistance.
3. (a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics.
4. a) Derive the relationship between drain to source current ids and drain to source voltage Vds in non saturation and
saturation region
b) Sketch the ids versus Vds graph for enhancement mode device.
5. In the inverter circuits, what is meant by Zpu and Zpd? Derive the required ratio between Zpu and Zpd if nMOS
inverter is to be driven from another nMOS inverter?
(a) Explain nMOS inverter and latch up in CMOS circuits?
6. (a) Find gm and rds for an n-channel transistor with
VGS = 1.2V; Vtn = 0.8V; W/L = 10; unCox = 92uA/V2and VDS = VeffThe out put impedance constant.
λ = 95.3 × 10^−3V^−1
Unit.3:
1. a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter.
b) What are the effects of scaling on Vt?
c) What are design rules? Why is metal- metal spacing larger than poly –poly spacing.
2. Draw the stick diagram and layout for
(a) NMOS inverter.
(b) P-Well CMOS inverter.
3. Draw the CMOS representation stick diagram and layout for a two Input EX-NOR gate.
4. (a) Draw the following transistors using lambda based design rules
i. NMOS enhancement
ii. NMOS depletion
iii. PMOS enhancement.
(b) Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rules.
5. Draw the stick diagram and mask layout for a CMOS two input NOR gate and stick diagram of two input NAND
gate.
6. (a) Double metal MOS process rules.
(b) Design rules for P- well CMOS process.
7. Design a stick diagram for the CMOS logic shown below Y = not(AB + CD)