ECE 369 - Fundamentals of Computer Architecture

Register file implementation in Verilog

¸ Register File
ß Two read register addresses and one write register address (5 bits each)
ß Writing into a register occurs during positive clock edge.
ß Reading of registers is not clock driven.

¸ Verilog implementation
ß You can declare 32 32-bit registers (r0, r1, … , r31)
ß Use switch statement
ß Remember that when register $0 is read, it always reads 0

¸ Verilog model definition

module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister, WriteData,

RegWrite, Clk, ReadData1, ReadData2);
input [4:0] ReadRegister1, ReadRegister2; // Two registers to be read
input [4:0] WriteRegister; // Register address to write into
input [31:0] WriteData; // Data to be written into WriteRegister
input RegWrite; // RegWrite control signal. Data is written only when this signal is enabled
output [31:0] ReadData1, ReadData2;
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 ECE 369 - Fundamentals of Computer Architecture

Data memory implementation in Verilog

¸ We will use a modified register file for memory access

ß In reality, memory is implemented differently
¸ Assume that your memory has 32 words (128 bytes)
ß We need 7-bits to address memory (byte-addressing)
¸ Writing to a memory location will occur during positive clock
¸ Memory read is not controlled by clock

¸ Verilog implementation
ß Implement the 32 words in memory as 32 32-bit registers
ß Note that an address of 0000100 refers to register r1.

module DataMemory(Address, WriteData, MemRead, MemWrite, Clk, ReadData);

input [6:0] Address; // 7-bit address to memory.
input [31:0] WriteData; // Data to be written into WriteRegister
input MemRead; // Data in memory location Address is read if this control is set
Input MemWrite; // WriteData is written in Address during positive clock edge if this control
is set
output [31:0] ReadData; // Value read from memory location Address

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 ECE 369 - Fundamentals of Computer Architecture

Single-cycle datapath

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ECE 369 - Fundamentals of Computer Architecture

Multi-cycle datapath

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 ECE 369 - Fundamentals of Computer Architecture

Control for multi-cycle implementation

¸ Value of control signals is dependent upon:

ß What instruction is being executed
ß Which step is being performed

¸ Use the information we’ve accumulated to specify a finite state

machine
ß Specify the finite state machine graphically, or
ß Use micro-programming

¸ Implementation can be derived from specification

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 ECE 369 - Fundamentals of Computer Architecture

Deciding the control

¸ In each clock cycle, decide all the action that needs to be taken

¸ The control signal can be 0 and 1 or x (don’t care)

¸ Make a signal an x if you can to reduce control

ß But any action that may destroy any useful value should not be allowed

¸ Control Signal required

ß ALU: SRC1 (1 bit), SRC2(2 bits), operation (Add, Sub, or from FC)
ß Memory: address (I or D), read, write, data clocked in IR or MDR
ß Register File: address (rt or rd), data (MDR or ALUOUT), read, write
ß PC: PCwrite, PCwrite-conditional, PC data (PC+4, branch, jump)

¸ Some of the control signal can be implied (register file read are values in A
and B registers (actually A and B need not be registers at all)

¸ Explicit control vs indirect control (derived based on input like what

instruction is being executed, or what function code field is) bits
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 ECE 369 - Fundamentals of Computer Architecture

Graphical specification
¸ How many state bits do we
require?

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ECE 369 - Fundamentals of Computer Architecture

PLA Implementation

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 ECE 369 - Fundamentals of Computer Architecture

ROM implementation
¸ ROM = "Read Only Memory"
ß Values of memory locations are fixed ahead of time
¸ A ROM can be used to implement a truth table
ß If the address is m-bits, we can address 2m entries in the ROM.
ß Our outputs are the bits of data that the address points to.

0 0 0 0 0 1 1
0 0 1 1 1 0 0
m n 0 1 0 1 1 0 0
0 1 1 1 0 0 0
1 0 0 0 0 0 0
m is the "height", and n is the "width" 1 0 1 0 0 0 1
1 1 0 0 1 1 0
1 1 1 0 1 1 1

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 ECE 369 - Fundamentals of Computer Architecture

ROM implementation

¸ How many inputs are there?

ß 6 bits for opcode, 4 bits for state = 10 address lines
(i.e., 210 = 1024 different addresses)
¸ How many outputs are there?
ß 16 datapath-control outputs, 4 state bits = 20 outputs

¸ ROM is 210 x 20 = 20K bits (and a rather unusual size)

¸ Rather wasteful, since for lots of the entries, the outputs are the
same
ß i.e., opcode is often ignored

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 ECE 369 - Fundamentals of Computer Architecture

ROM vs PLA
¸ Break up the table into two parts
ß 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM
ß 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
ß Total: 4.3K bits of ROM
¸ PLA is much smaller
ß Can share product terms
ß Only need entries that produce an active output
ß Can take into account don't cares
¸ Size is (#inputs x #product-terms) + (#outputs x #product-terms)
ß For this example = (10x17)+(20x17) = 460 PLA cells

¸ PLA cells usually about the size of a ROM cell (slightly bigger)

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