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000
110
010
100
011
001
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A A A A A A A A A A A A
BC 0 X BC X 1 BC 1 0 BC X X BC 0 1 BC X X
BC 0 X BC X 1 BC 1 0 BC X X BC X X BC 0 1
BC 0 X BC X 1 BC X X BC 1 1 BC X X BC 1 1
BC 1 X BC X 0 BC X X BC 0 1 BC 0 0 BC X X
The minimized Boolean expressions are as follows.
J A = B.C , K A = B + C , J B = A , K B = A + C , J C = A.B and K C = A + B .
Step-5: Implement the combinational circuits using the final expressions.
Clock-In
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D Q
Q3 D Q
Q2 D Q
Q1 D Q Q0
_ _ _ _
CLOCK CP Q CP Q CP Q CP Q
0 1 2 3 4 5 6 7
Q3 Q2 Q1 Q0 CLOCK
CLOCK
pulse 1000
1 0 0 0 0
Q3 0 1 0 0 1
0 0 1 0 2 0100
0001
Q2 0 0 0 1 3
1 0 0 0 4
0 1 0 0 5 0010
Q1
0 0 1 0 6
0 0 0 1 7
Q0 - - - - -
Fig.: Four-bit ring counter – logic circuit, waveforms, truth table and state transition diagram.
Assuming a starting state of Q3=1 and Q2=Q1=Q0=0.
After first pulse, the 1 has shifted from Q3 to Q2 so that the counter is in the 0100 state.
The second pulse produces the 0010 state.
The third pulse produces the 0001 state.
On the fourth clock pulse, the 1 from Q0 is transferred to Q3, resulting in the 1000 state, which is, of course, the initial
state.
Subsequent pulses cause the sequence to repeat.
This counter functions as a MOD-4 counter, since it has four distinct states before the sequence repeats. A MOD-N
ring counter can be constructed using N flip-flops connected in the ring-counter arrangement.
To operate properly, a ring counter must start off with only one FF in the 1 state and all the others in the 0 state.
Since the starting states of the FFs will be unpredictable on power-up, the counter must be preset to the required
starting state before clock pulses are applied. One way to do this is to apply a momentary pulse to the asynchronous
PRE input of one of the FFs and to the CLR input of all other FFs.
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1 2 3 4 5 6 7 Q2 Q1 Q0 CLOCK
000
pulse
CLOCK
0 0 0 0
1 0 0 1 001
Q2 1 1 0 2 100
1 1 1 3
Q1 0 1 1 4
0 0 1 5
011
0 0 0 6 110
Q0
1 0 0 7
1 1 0 8
- - - 111
Fig.: MOD-6 Johnson counter – logic circuit, waveforms, truth table and state transition diagram.
The MOD number of a Johnson counter will always be equal to twice the number of FFs. Thus, it is possible to
construct a MOD-N counter by connecting N/2 flip-flops in a Johnson-counter arrangement.
Digital Clock:
The 60-Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of 60pps. This 60pps
waveform is fed into a MOD-60 counter that is used to divide the 60pps down to 1pps. The 1pps signal is fed into the
BCD counter of SECONDS section. The MSB of the BCD counter is used as the CLK of the MOD-6 counter.
The BCD counter advances one count per second. After 9 seconds the BCD counter recycles to 0, which triggers the
MOD-6 counter and causes it to advance one count. This continues for 59s, at which point the MOD-6 counter is at
the 101 (=510) and the BCD counter is at 1001 (=910), so that the display reads 59. The next pulse recycles the BCD
counter to 0, which in turn recycles the MOD-6 counter to 0.
The output of the MOD-6 counter in the SECONDS section has a frequency of 1ppm. This signal is fed to the
MINUTES section, which counts and displays minutes from 0 through 59.
The output of the MOD-6 counter in the MINUTES section has a frequency of 1pph. This signal is fed to the HOURS
section, which counts and displays hours from 1 through 12.
60Hz 60pps 1pps
Pulse shaper CTR DIV60
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BCD
MOD-2 0 0 0 1
74HC112 P3 P2 P1 P0
1pph
CPU
X J 1
Presettable
CLK MR BCD counter
CPD 1
74HC192
X K 1
CLR Q3 Q2 Q1 Q0
PL
Display Decoder/display
Tens of hours, 0-1
Units of hours, 0-9
Fig.: Detailed circuitry for the HOURS section.
As the HOURS section never goes to the 0 state, it needs special circuitry that includes –
(I) a 74192 BCD counter to count units of hours. It counts only between 0000 and 1001. It is used to count up in
response to the 1pph signal coming from the MINUTES section. The INVERTER on the CPU input is needed as
we want it to respond to the NGT that occurs when the MINUTES section recycles back to 0.
(II) a single FF to count tens of hours.
The incoming pulses advance the BCD counter once per hour. When the BCD counter is in the 1001 (=910) state and
the next input pulse occurs, it will recycle back to 0000. The NGT at Q3 will toggle flip-flop X from 0 to 1. This
produces a numeral 1 on the X display and a numeral 0 on the BCD display so that the combined display show 10 for
10 o’clock.
The next two pulses advance the BCD counter so that 11 and 12 are displayed at 11 o’clock and 12 o’clock,
respectively. The next pulse advances the BCD counter to 0011 (=310). In this state, the counter’s Q1 and Q0 outputs
are both HIGH, and X is still HIGH. Thus, the NAND gate output goes LOW and activates the CLR of flip-flop X and
the PL input of the 74192 BCD counter. This clears X to 0 and presets the BCD counter to 0001. The result is a
display of 01 for 1 o’clock.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]
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