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Ref. No............................ September 19, 2010


Dated, the………………………….

Counter with Arbitrary Sequences:


There are several techniques for designing counters that follow a given arbitrary sequence. Here, a commonly used
technique has been discussed in detail for designing synchronous counters using J-K flip-flops or D flip-flops. We will
illustrate the design procedure with an example of designing a three-bit counter that goes through the sequence –
[CBA]=000010011001100110000010….
Step-1: Determine the number of flip-flops required for the purpose. Identify the undesired states.
In the present case, the number of flip-flops required is 3 and the undesired states are 101 and 111.
Step-2: Draw the state transition diagram showing all possible states including the ones that are not desired. The
undesired states should be depicted to be transiting to any of the desired states. Choosing the 000 state for the
purpose, the state transition diagram looks like –
101 111

000

110
010

100
011

001

Fig.: State transition diagram.


Step-3: Draw the excitation table for the counter, listing the present states, the next states corresponding to the
present states and the required logic status of the flip-flop inputs. Excitation table for the present example is shown
below.
Present state Next state Inputs
C B A C B A JC KC JB KB JA KA
0 0 0 0 1 0 0 X 1 X 0 X
0 0 1 1 0 0 1 X 0 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 0 0 1 0 X X 1 X 0
1 0 0 1 1 0 X 0 1 X 0 X
1 0 1 0 0 0 X 1 0 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 0 0 0 X 1 X 1 X 1
Step-4: Design the logic circuits for generating JA, KA, JB, KB, JC and KC inputs from available A, A , B, B , C and C
outputs.
For our example, the Karnaugh maps for JA, KA, JB, KB, JC and KC are respectively shown below.

Lec-24, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &


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KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
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Ref. No............................ September 19, 2010


Dated, the………………………….

A A A A A A A A A A A A
BC 0 X BC X 1 BC 1 0 BC X X BC 0 1 BC X X
BC 0 X BC X 1 BC 1 0 BC X X BC X X BC 0 1
BC 0 X BC X 1 BC X X BC 1 1 BC X X BC 1 1
BC 1 X BC X 0 BC X X BC 0 1 BC 0 0 BC X X
The minimized Boolean expressions are as follows.
J A = B.C , K A = B + C , J B = A , K B = A + C , J C = A.B and K C = A + B .
Step-5: Implement the combinational circuits using the final expressions.

FF-C FF-B FF-A


C B A
Q J Q J Q J
_ CP _ CP _ CP
Q K Q K Q K
C R B R A R

Clock-In

Fig.: Counter with an arbitrary sequence.


[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Shift Register Counters:


Shift register has no specified sequence of states. If the serial output of a shift register is fed back to the serial input,
the circuit exhibits a specified sequence of states. The resulting circuits are known as shift register counters.
Depending upon the nature of the feedback, there are two types of shift register counter –
(1) Ring counter and
(2) Johnson counter.

(1) Ring Counter:


A ring counter is obtained from a shift register by directly feeding back the true output of the output flip-flop to the
data input terminal of the input flip-flop.
If D flip-flops are being used to construct the shift register, the ring counter, also called a circulating register, can be
constructed by feeding back the Q output of the output flip-flop back to the D input of the input flip-flop.
If J-K flip-flops are being used, the Q and Q outputs of the output flip-flop are respectively fed back to the J and K
inputs of the input flip-flop.

Lec-24, Pg-02 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &


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Ref. No............................ September 19, 2010


Dated, the………………………….

D Q
Q3 D Q
Q2 D Q
Q1 D Q Q0
_ _ _ _
CLOCK CP Q CP Q CP Q CP Q

0 1 2 3 4 5 6 7
Q3 Q2 Q1 Q0 CLOCK
CLOCK
pulse 1000
1 0 0 0 0
Q3 0 1 0 0 1
0 0 1 0 2 0100
0001
Q2 0 0 0 1 3
1 0 0 0 4
0 1 0 0 5 0010
Q1
0 0 1 0 6
0 0 0 1 7
Q0 - - - - -

Fig.: Four-bit ring counter – logic circuit, waveforms, truth table and state transition diagram.
Assuming a starting state of Q3=1 and Q2=Q1=Q0=0.
After first pulse, the 1 has shifted from Q3 to Q2 so that the counter is in the 0100 state.
The second pulse produces the 0010 state.
The third pulse produces the 0001 state.
On the fourth clock pulse, the 1 from Q0 is transferred to Q3, resulting in the 1000 state, which is, of course, the initial
state.
Subsequent pulses cause the sequence to repeat.
This counter functions as a MOD-4 counter, since it has four distinct states before the sequence repeats. A MOD-N
ring counter can be constructed using N flip-flops connected in the ring-counter arrangement.
To operate properly, a ring counter must start off with only one FF in the 1 state and all the others in the 0 state.
Since the starting states of the FFs will be unpredictable on power-up, the counter must be preset to the required
starting state before clock pulses are applied. One way to do this is to apply a momentary pulse to the asynchronous
PRE input of one of the FFs and to the CLR input of all other FFs.

(2) Johnson Counter:


The Johnson or twisted-ring counter is constructed by having an inverse feedback in a shift register. A three-bit
Johnson counter is shown in the following figure where the Q0 output is connected back to the D input of Q2.
On each positive clock-pulse transition, the level at Q2 shifts into Q1, the level at Q1 shifts into Q0 and the inverse of
the level at Q0 shifts into Q2. Assuming that all FFs are initially 0, we have the following important points –
(I) This counter has six distinct states – 000, 100, 110, 111, 011 and 001 before it repeats the sequence. Thus,
it is a MOD-6 Johnson counter.
(II) The waveform of each FF is a square wave at one-sixth the frequency of the clock. The FF waveforms are
shifted by one clock period with respect to each other.
Q2 Q1
D Q
_
D Q
_
D Q
_
Q0
CLOCK CP Q CP Q CP Q

Lec-24, Pg-03 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &


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Ref. No............................ September 19, 2010


Dated, the………………………….

1 2 3 4 5 6 7 Q2 Q1 Q0 CLOCK
000
pulse
CLOCK
0 0 0 0
1 0 0 1 001
Q2 1 1 0 2 100
1 1 1 3
Q1 0 1 1 4
0 0 1 5
011
0 0 0 6 110
Q0
1 0 0 7
1 1 0 8
- - - 111

Fig.: MOD-6 Johnson counter – logic circuit, waveforms, truth table and state transition diagram.
The MOD number of a Johnson counter will always be equal to twice the number of FFs. Thus, it is possible to
construct a MOD-N counter by connecting N/2 flip-flops in a Johnson-counter arrangement.

Digital Clock:
The 60-Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of 60pps. This 60pps
waveform is fed into a MOD-60 counter that is used to divide the 60pps down to 1pps. The 1pps signal is fed into the
BCD counter of SECONDS section. The MSB of the BCD counter is used as the CLK of the MOD-6 counter.
The BCD counter advances one count per second. After 9 seconds the BCD counter recycles to 0, which triggers the
MOD-6 counter and causes it to advance one count. This continues for 59s, at which point the MOD-6 counter is at
the 101 (=510) and the BCD counter is at 1001 (=910), so that the display reads 59. The next pulse recycles the BCD
counter to 0, which in turn recycles the MOD-6 counter to 0.
The output of the MOD-6 counter in the SECONDS section has a frequency of 1ppm. This signal is fed to the
MINUTES section, which counts and displays minutes from 0 through 59.
The output of the MOD-6 counter in the MINUTES section has a frequency of 1pph. This signal is fed to the HOURS
section, which counts and displays hours from 1 through 12.
60Hz 60pps 1pps
Pulse shaper CTR DIV60

MOD-2 BCD 1pph MOD-6 BCD 1ppm MOD-6 BCD


(one FF) counter counter counter counter counter

Display Decoder/ Decoder/ Decoder/ Decoder/ Decoder/


display display display display display
0-1 Tens 0-9 Units 0-5 Tens 0-9 Units 0-5 Tens 0-9 Units
Hours section Minutes section Seconds section
Fig.: Block diagram of a digital clock.

Lec-24, Pg-04 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
`~ivjvcbx t Telephone :
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dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &


COMMUNICATION ENGINEERING
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UNIVERSITY OF DHAKA
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Ref. No............................ September 19, 2010


Dated, the………………………….

BCD
MOD-2 0 0 0 1

74HC112 P3 P2 P1 P0
1pph
CPU
X J 1
Presettable
CLK MR BCD counter
CPD 1
74HC192
X K 1
CLR Q3 Q2 Q1 Q0
PL

Display Decoder/display
Tens of hours, 0-1
Units of hours, 0-9
Fig.: Detailed circuitry for the HOURS section.
As the HOURS section never goes to the 0 state, it needs special circuitry that includes –
(I) a 74192 BCD counter to count units of hours. It counts only between 0000 and 1001. It is used to count up in
response to the 1pph signal coming from the MINUTES section. The INVERTER on the CPU input is needed as
we want it to respond to the NGT that occurs when the MINUTES section recycles back to 0.
(II) a single FF to count tens of hours.
The incoming pulses advance the BCD counter once per hour. When the BCD counter is in the 1001 (=910) state and
the next input pulse occurs, it will recycle back to 0000. The NGT at Q3 will toggle flip-flop X from 0 to 1. This
produces a numeral 1 on the X display and a numeral 0 on the BCD display so that the combined display show 10 for
10 o’clock.
The next two pulses advance the BCD counter so that 11 and 12 are displayed at 11 o’clock and 12 o’clock,
respectively. The next pulse advances the BCD counter to 0011 (=310). In this state, the counter’s Q1 and Q0 outputs
are both HIGH, and X is still HIGH. Thus, the NAND gate output goes LOW and activates the CLR of flip-flop X and
the PL input of the 74192 BCD counter. This clears X to 0 and presets the BCD counter to 0001. The result is a
display of 01 for 1 o’clock.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

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