Introduction to VLSI Design, VLSI I, Fall 2010

3. Implementing Logic in CMOS 1

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3. Implementing Logic in CMOS

J. A. Abraham

Department
60 of Electrical and Computer Engineering
The University of Texas at Austin
EE 382M, VLSI I
Fall 2010
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September 13, 2010

ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 1 / 30

Static CMOS Circuits

N- and P-channel Networks

mm 40 60 implement80logic functions
100 120
N- and P-channel networks
Each network connected between Output and VDD or VSS
Function defines path between the terminals

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 1 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 2

Duality in CMOS Networks

Straightforward way of constructing static CMOS circuits is to
implement
mm dual N- 40and P- networks
60 80 100 120
N- and P- networks must implement complementary
functions
Duality sufficient for correct operation (but not necessary)
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 2 / 30

Constructing Complex Gates

mm F = (A40
Example: · B) + (C · 60
D) 80 100 120
1 Take uninverted function F = (A · B) + (C · D) and derive
N-network
2 Identify AN D, OR components: F is OR of AB, CD
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3 Make connections of transistors

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 3 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 3

Construction of Complex Gates, Cont’d

4 Construct P-network
mm 40 by 60 80 100
10 120
12
taking complement of
N-expression (AB + CD),
which gives the
expression,
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(A + B) · (C + D)
5 Combine P and N circuits

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 4 / 30

Layout of Complex Gate

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AND-OR-INVERT (AOI) gate

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60

Note: Arbitrary shapes are not

80 allowed in some nanoscale
design rules
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 5 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 4

Example of Compound Gate

F = (A + B + C) · D)
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10 120
12
Note:
N- and P- graphs are duals of each
other
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In this case, the function is the
complement of the switching
function between F and GND
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Question: Does it make any
difference to the function if the
transistor with input D is connected
between the parallel A, B, C,
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transistors and GND?
What about the electrical behavior?
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 6 / 30

Example of More Complex Gate

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OU T = (A + B) · (C + D) · (E + F + (G · H))
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 7 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 5

Exclusive-NOR Gate in CMOS

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Note:80designs such as these should be checked very carefully for

correct behavior using circuit simulation

ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 8 / 30

Pseudo nMOS Logic

Based on the old NMOS technology where a “depletion” transistor
was used as a pullup resistor
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What happens when there is no path from Z to ground (i.e., Z =
1)?
What happens when there is a path from Z to ground (i.e., Z = 0)?
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 9 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 6

Duality is Not Necessary for a CMOS Structure

Functions realized by N and P networks must be complementary,
and one of them must conduct for every input combination
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F = a·b+a·b+a·c+c·d+a·b

60 The N and P networks are

NOT duals, but the switching
functions they implement
are complementary
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 10 / 30

Example of Complex CMOS Gate

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40 F=

G=
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 11 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 7

Signal Strength

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Voltages represent digital logic values
Strength of signal:
How close it approximates ideal voltage
V40DD and GN D rails are strongest 1 and 0
nMOS transistors pass a strong 0
But degraded or weak 1
pMOS transistors pass a strong 1
60 But degraded or weak 0

Therefore, nMOS transistors are best for the “pull-down”

network
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 12 / 30

Pass Transistors and Transmission Gates

Transistors can be used as switches; however, they could produce
degraded outputs
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Transmission gates pass both 0 and 1 well

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 13 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 8

Pass Transistor Logic

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“Pull-Up” Circuit
Used to restore degraded logic 1 from output of nMOS pass
transistor
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 14 / 30

Pass Transistor Logic – Better Layout

Group
mm 40
similar transistors, 60 can be in80the same well
so they 100 120

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 15 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 9

Tristates

Tristate Buffer produces Z (high impedance) when not enabled

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EN A Y
0 0 Z
0 1 Z
1 400 0
1 1 1

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Non-Restoring Tristate
Transmission gate acts as a tristate buffer
Only two transistors, but nonrestoring
Noise
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 16 / 30

Tristate Inverter

Tristate inverter produces restored output, but complements signal

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 17 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 10

Multiplexers

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S D1 D0 Y
0 X 0 0
0 X 1 1
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1 0 X 0
1 1 X 1

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How many transistors are needed?

80 (The better design uses 3 NAND
gates and 1 inverter)

ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 18 / 30

Transmission Gate MUX

Nonrestoring
mm MUX40 60 80 100 120
Uses two transmission
gates =⇒ only 4
transistors
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Inverting MUX – adds an inverter
Uses compound gate AOI22
Alternatively, a pair of tristate inverters (same thing)
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 19 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 11

4:1 Multiplexer

A 4:1 MUX chooses one of 4 inputs using two selects

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Two levels of 2:1 MUXes
Alternatively, four tristates

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 20 / 30

D Latch

Basicmm
Memory Element
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When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
40 Q holds its old value independent of D
a.k.a., transparent latch or level-sensitive latch

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 21 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 12

D Latch, Cont’d

mm
D Latch Design: 40 60 80 100 120
MUX chooses
between D and
old Q
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D Latch
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Operation

ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 22 / 30

D Flip-Flop (D-Flop)

Another common storage element

mm 40 D is copied
When CLK rises, 60 to Q 80 100 120
At all other times, Q holds its value
positive edge-triggered flip-flop or master-slave flip-flop
Built
40 from “master” and “slave” D latches

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 23 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 13

D Flip-Flop Operation

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 24 / 30

Race Condition – Hold Time Failure

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Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
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Called hold-time failure or race condition

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 25 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 14

Non-Overlapping Clocks

A simple way to prevent races

This works as40long as non-overlap
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exceeds 100 120
Used in safe (conservative) designs
Industry does not generally use this approach – managing
skew more carefully instead
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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 26 / 30

Gate Layout

Building a library of standard cells

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Layout can be time consuming
One solution is to have layouts of commonly used functions
(Inverter, NAND, OR, MUX, etc.), designed to fit together
very
40 well

Standard cell design methodology

VDD and GN D should abut (standard height)
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Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
One of the large industry suppliers is ARM (which purchased
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ARTISAN)

ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 27 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 15

Examples of Standard Cell Layout

NAND3
Inverter
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Horizontal N-diffusion and P-diffusion strips

80 Polysilicon gates
Vertical
Metal1 VDD rail at top, Metal1 GN D rail at bottom
32λ by 40λ
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 28 / 30

Wiring Tracks and Well Spacing

mmTrack is the
Wiring 40 space 60 Example,
80 well spacing:
100 wells 120
required for a wire must surround transistors by
Example, 4λ width, 4λ spacing 6λ
from neighbor = 8λ pitch Implies 12λ between opposite
Transistors
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also consume one transistor flavors
wiring track Leaves room for one wire track

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 29 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
3. Implementing Logic in CMOS 16

Example of Area Estimation

Estimate
mmarea by counting
40 60 Estimating80area of O3AI
100 120
wiring tracks Sketch a stick diagram and estimate
Multiply by 8 to express in λ area

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ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS J. A. Abraham, September 13, 2010 30 / 30

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 13, 2010