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DATA SHEET
For a complete data sheet, please also download:
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification 1998 Jun 04
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
FEATURES DESCRIPTION
• 8-bit serial input The 74HC/HCT595 are high-speed Si-gate CMOS devices
• 8-bit serial or parallel output and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
• Storage register with 3-state outputs
standard no. 7A.
• Shift register with direct clear
The “595” is an 8-stage serial shift register with a storage
• 100 MHz (typ) shift out frequency register and 3-state outputs. The shift register and storage
• Output capability: register have separate clocks.
– parallel outputs; bus driver Data is shifted on the positive-going transitions of the
– serial output; standard SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the STCP
• ICC category: MSI.
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
APPLICATIONS storage register.
• Serial-to-parallel data conversion The shift register has a serial input (DS) and a serial
• Remote control holding register. standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
TYP.
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V
SHCP to Q7’ 16 21 ns
STCP to Qn 17 20 ns
MR to Q7’ 14 19 ns
fmax maximum clock frequency SHCP, STCP 100 57 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 115 130 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.
1998 Jun 04 2
Philips Semiconductors Product specification
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
74HC595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HC595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC595DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HC595PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74HCT595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HCT595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PINNING
handbook, halfpage 11 12
handbook, halfpage
Q1 1 16 VCC SHCP STCP
9
Q7'
Q2 2 15 Q0
15
Q0
Q3 3 14 DS 1
Q1
Q4 4 13 OE 2
Q2
595 14 3
Q5 5 12 STCP DS Q3
4
Q4
Q6 6 11 SHCP
5
Q5
Q7 7 10 MR 6
Q6
GND 8 9 Q7' 7
Q7
MLA001 MR OE
10 13
MLA002
1998 Jun 04 3
Philips Semiconductors Product specification
handbook, halfpage 13
OE EN3
12
STCP C2
10
MR R SRG8
11
SHCP C1/
14 15
DS 1D 2D 3 Q0
1
Q1
2
Q2
3
Q3
4
Q4
5
Q5
6
Q6
7
Q7
9
Q7'
MSA698
14 DS
11 SHCP
8-STAGE SHIFT REGISTER
10 MR
Q7 ' 9
12 STCP
8-BIT STORAGE REGISTER
Q0 15
Q1 1
Q2 2
Q3 3
13 OE
3-STATE OUTPUTS Q4 4
Q5 5
Q6 6
Q7 7
MLA003
1998 Jun 04 4
Philips Semiconductors Product specification
DS D Q D Q D Q Q7'
FF0 FF7
CP CP
R R
SHCP
MR
D Q D Q
LATCH LATCH
CP CP
STCP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MLA010
1998 Jun 04 5
Philips Semiconductors Product specification
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTON
SHCP STCP OE MR DS Q7’ QN
X X L L X L NC a LOW level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear. Parallel outputs in high-impedance
OFF-state
↑ X L H H Q6’ NC logic high level shifted into shift register stage 0. Contents
of all shift register stages shifted through, e.g. previous
state of stage 6 (internal Q6’) appears on the serial output
(Q7’)
X ↑ L H X NC Qn’ contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
↑ ↑ L H X Q6’ Qn’ contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
Notes
1. H = HIGH voltage level; L = LOW voltage level
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Z = high-impedance OFF-state; NC = no change
X = don’t care.
1998 Jun 04 6
Philips Semiconductors Product specification
handbook,
SHfull
CPpagewidth
DS
STCP
MR
OE
Q0
high-impedance OFF-state
Q1
Q6
Q7
Q 7'
MLA005 - 1
1998 Jun 04 7
Philips Semiconductors Product specification
1998 Jun 04 8
Philips Semiconductors Product specification
1998 Jun 04 9
Philips Semiconductors Product specification
1998 Jun 04 10
Philips Semiconductors Product specification
1998 Jun 04 11
Philips Semiconductors Product specification
AC WAVEFORMS
tW
tPLH tPHL
90%
Q7' OUTPUT VM(1)
10%
Fig.7 Waveforms showing the clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and
maximum shift clock frequency.
tsu 1/fmax
tW
tPLH tPHL
Qn OUTPUT VM(1)
MSA700
Fig.8 Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse
width and the shift clock to storage clock set-up time.
1998 Jun 04 12
Philips Semiconductors Product specification
tsu tsu
th th
DS INPUT VM(1)
MLB196
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
MR INPUT VM(1)
tW trem
tPHL
MLB197
Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay
and the master reset to shift clock (SHCP) removal time.
1998 Jun 04 13
Philips Semiconductors Product specification
90%
OE INPUT VM(1)
10%
tPLZ tPZL
Qn OUTPUT
LOW-to-OFF VM(1)
OFF-to-LOW 10%
tPHZ tPZH
90%
Qn OUTPUT
HIGH-to-OFF VM(1)
OFF-to-HIGH
Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
1998 Jun 04 14
Philips Semiconductors Product specification
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
D ME
seating plane
A2 A
A1
L
c
Z e w M
b1
(e 1)
b
16 9 MH
pin 1 index
E
1 8
0 5 10 mm
scale
UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.40 0.53 0.32 21.8 6.48 3.9 8.25 9.5
mm 4.7 0.51 3.7 2.54 7.62 0.254 2.2
1.14 0.38 0.23 21.4 6.20 3.4 7.80 8.3
0.055 0.021 0.013 0.86 0.26 0.15 0.32 0.37
inches 0.19 0.020 0.15 0.10 0.30 0.01 0.087
0.045 0.015 0.009 0.84 0.24 0.13 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
92-10-02
SOT38-1 050G09 MO-001AE
95-01-19
1998 Jun 04 15
Philips Semiconductors Product specification
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
95-01-23
SOT109-1 076E07S MS-012AC
97-05-22
1998 Jun 04 16
Philips Semiconductors Product specification
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
D E A
X
c
y HE v M A
16 9
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 8 detail X
w M
e bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
94-01-14
SOT338-1 MO-150AC
95-02-04
1998 Jun 04 17
Philips Semiconductors Product specification
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
94-07-12
SOT403-1 MO-153
95-04-04
1998 Jun 04 18
Philips Semiconductors Product specification
1998 Jun 04 19
Philips Semiconductors Product specification
DEFINITIONS
1998 Jun 04 20
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