1

2
3
40
39
38
8-bit
Microcontrolle
4 37
5 36
6 35

r
7 34
8 33
9 32

Features 10 31

• Compatible with MCS-51™ Products

11
12
13
30
29
28
with 4K Bytes
• 4K Bytes of In-System Reprogrammable Flash Memory
Flash
14 27
15 26
– Endurance: 1,000 Write/Erase Cycles 16 25
17 24
• Fully Static Operation: 0 Hz to 24 MHz 18 23
• Three-level Program Memory Lock 19
20
22
21
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes

Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash programmable and erasable read only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conven-
tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides
a highly-flexible and cost-effective solution to many embedded control applications.

PDIP
Pin Configurations
P1.0 VCC
P1.1 P0.0 (AD0)
P1.2 P0.1 (AD1)
P1.3 P0.2 (AD2)
P1.4 P0.3 (AD3)
P1.5 P0.4 (AD4)
P1.6 P0.5 (AD5)
P1.7 P0.6 (AD6)
RST P0.7 (AD7)
PQFP/TQF (RXD) P3.0 EA/VPP

P (TXD) P3.1
(INT0) P3.2
ALE/PROG
PSEN
(INT1) P3.3 P2.7 (A15)
(T0) P3.4 P2.6 (A14)
(T1) P3.5 P2.5 (A13)
(WR) P3.6 P2.4 (A12)
(RD) P3.7 P2.3 (A11)
XTAL2 P2.2 (A10)
XTAL1 P2.1 (A9)
33 PO.4 (AD4) GND P2.0 (A8)
P1.5 1 32 P0.5 (AD5)
P1.6 2 31 P0.6 (AD6)
P1.7 3 30 P0.7 (AD7) PLCC
RST 4 29 EA/VPP
(RXD) P3.0 5 28 NC
NC 6 27 ALE/PROG
(TXD) P3.1 7 26 PSEN
(INT0) P3.2 8 25 P2.7 (A15)
(INT1) P3.3 9 24 P2.6 (A14)
(T0) P3.4 10 23 P2.5 (A13)
P1.5 7 39 PO.4 (AD4)
P1.6 8 38 P0.5 (AD5)
P1.7 9 37 P0.6 (AD6)
RST 10 36 P0.7 (AD7)
(RXD) P3.0 11 35 EA/VPP
NC 12 34 NC
(TXD) P3.1 13 33 ALE/PROG
(INT0) P3.2 14 32 PSEN
(INT1) P3.3 15 31 P2.7 (A15)
(T0) P3.4 16 30 P2.6 (A14)
(T1) P3.5 17 29 P2.5 (A13)

Rev. 0265G–02/00
 PORT 0 DRIVERS PORT 2 DRIVERS

Block Diagram RAM ADDR. PORT 0 PORT 2

REGISTER RAM LATCH LATCH FLASH

P0.0 - P0.7 P2.0 - P2.7

VCC

GND
PROGRAM
B STACK
ACC ADDRESS
REGISTER POINTER
REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM
PSW COUNTER

TIMING
AND INSTRUCTION DPTR
CONTROL REGISTER

PORT 1 PORT 3
LATCH LATCH

OSC
PSEN PORT 1 DRIVERS PORT 3 DRIVERS
ALE/PROG
EA / VPP
RST
P1.0 -
P1.7

AT89C51
P3.0 - P3.7

2

The AT89C51 provides the following standard features: 4K
bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock cir-
cuitry. In addition, the AT89C51 is designed with static logic
for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The
Power-down Mode saves the RAM contents but freezes
the oscillator disabling all other chip functions until the next
hardware reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode P0 has internal
pullups.
Port 0 also receives the code bytes during Flash program-
ming, and outputs the code byt es during program
verification. External pullups are required during program
verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
AT89C51
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, it uses strong internal pullups
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
Port 3 also receives some control signals for Flash
pro-
gramming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash
programming.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency, and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE