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EARLY OUTPUT LOGIC BASED FILTER BANK STRUCTURE
CONCEPT OF EARLY OUTPUT LOGIC
DIMS is the approach usually taken to create QDI circuits. It allows logic to be
constructed without the need for matched delays. Unfortunately DIMS gates are
large, slow and power-hungry as shown in figure 3.1, due to the C-elements which
are required to ensure that the output only rises when all inputs are valid and fall only
when they return to NULL.
A1
C
A0
X1
C
X0
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C
B1
B0
Figure 3.1 DIMS OR gate
Table 3.1 and table 3.2 shows the output of DIMS and early output OR gates
(Brej.C.F, 2003). Here A and B are the inputs to the gate.
The early output gate outputs early in two cases (marked with a *). Although
this is beneficial because the result arrives at its destination sooner, it does not
ensure that all inputs have arrived.
Table 3.1 DIMS behavior

A
B 0 N 1
0 0 N 1
N N N N
1 1 N 1
Table 3.2 Early output OR gate behavior

A
B 0 N 1
0 0 N 1
N N N 1*
1 1 1* 1
A DIMS gate has the following properties:
1) Outputs NULL when all inputs are NULL.

2) Executes the required logical operation.
3) Only outputs a valid value when all inputs are valid.
4) Only returns to NULL when all inputs are NULL.
The early output has properties 1 and 2 only, so some other mechanism must be
provided to ensure correct operation.
GUARDING
Property 3 ensures that only when all inputs into a stage are valid, then the
result will become valid. In an early output logic system, this is undesirable, as early
output logic generates results as soon as sufficient inputs have arrived to determine
the output. Here, the requirement is that all the inputs must have been asserted
before they can be acknowledged. Figure 3.2 shows an example of an early output
pipeline stage. Here, Ri, Ro are the request signals; Ai, Ao are the acknowledge
signals; Vo is the Valid signal. Two levels of C-element are used to guarantee
operation. The first C-elements (C1 and C2) are adjacent to the output latches; these
‘guarding’ C-elements produce an acknowledge when the output latches have
captured the input data – the timing of which is implicit in the (black) data signals –
and all the contributing input stages have output valid data. These then signal an
acknowledgement to the input latches. This ensures that a latch will not receive an
acknowledge until it is ready and rises its output data.
Figure 3.2 Early Output Pipeline Stage

The second set of C-elements ensures that in all the latches, the data has
been sent to have acknowledged before the input latch may change. These C-
elements also ensure that all relevant latches achieve a NULL state in between data
values. This mechanism requires a ‘valid’ (Vo) signal to accompany the data
assertion. In a four-phase, dual-rail system this may simply be provided by an OR of
the input bits.
EARLY OUTPUT GATES
Logic gates such as AND and OR have a 50% probability of generating a

result with only one of their inputs present.
The structure of a two input early output OR gate (Charles Brej, 2005) is
demonstrated in figure3.3. The OR gate generates an early output when either of two
inputs are 1. To complete the set of input states the AND gate generates an output
when both inputs are valid but they are not covered by the early output set (both are
0).
Figure 3.3 Two input early output OR gate
This combination can be used to create any dual-rail early output AND/OR
gate with or without inversions on inputs and outputs. The structure of a two input
early output AND gate is demonstrated in figure 3.4.
Figure 3.4 Two input early output AND gate.
The AND/OR gates output one value when all inputs are in a particular state
and output the other value in all other input combinations. Any inversions of inputs or
outputs can be performed by swapping the wires representing 1 and 0.
DUAL-RAIL FULL ADDER USING EARLY OUTPUT GATES

A dual-rail full adder using early output gates is shown in the figure 3.5.
Figure 3.5 Dual-rail full adder using early output gates.

Here, early output AND gate, early output OR gate and EXOR gates were
used. The dual-rail full adder using early output gates does not use any C-elements.
This reduces the longer computing time and area overhead for filter design to
implement 2-D DWT, when compared to the dual-rail full adder using C-elements.
DUAL-RAIL BOOTH MULTIPLIER USING EARLY OUTPUT GATES

An 8x8 dual-rail booth multiplier using early output gates is proposed and is
shown in the figure 3.6.
Figure 3.6 8x8 Dual-rail booth multiplier using early output gates.
In this booth multiplier, a1, a0, b1, b0 are the inputs to the booth encoder,
yout1, yout0 and ovf1 and ovf0 are the outputs and overflow bit of 16 bit fulladder3.
Then sum11, sum10 and k11, k10 are the sum and carry of the 16 bit full adder1
while, sum21, sum20 and k21, k20 are sum and carry of the 16 bit full adder 2
respectively. Here, dual-rail full adder using early output gates is used in designing
16-bit full adder, which in turn used for adding the partial products generated from the
booth encoder.The decision to use a Radix-4 modified Booth algorithm is that in
radix-4, the number of partial products is reduced to n/2. So, this 8x8 dual-rail booth
multiplier is further extended to 16x8 dual-rail booth multiplier as shown in the figure
3.7.
Figure 3.7 16x8 Dual-rail booth multiplier using early output gates
Though Wallace Tree structure multipliers could be used, the multiplier array
becomes very large and requires large numbers of logic gates and interconnecting
wires which makes the chip design large and slows down the operating speed.
Booth multiplier which scan strings of three bits with the algorithm given below:
● Extend the sign bit 1 position if necessary to ensure that n is even.
● Append a 0 to the right of the LSB of the multiplier.
● According to the value of each vector, each partial product will be 0, +y, -y, +2y or
-2y.
BASIC FILTER STRUCTURE FOR IMPLEMENTING 2-D DWT
The basic filter structure (Volnei A.Pedroni, 2005) using early output logic is
shown in the figure 3.8. Here, D (delay) represents a register (flip-flops), a triangle is
a multiplier, and a circle represents an adder.
+
x[n]
y[n]
C1
C2
C3
C0
D
+
D
+
D
x[n-1]
x[n-2]
x[n-3]
Figure 3.8 Basic filter structure for 2-D DWT.
In this filter structure, dual-rail full adder using early output gates and dual-rail booth
multiplier using early output gates were used for implementing 2-D DWT.
REFERENCES
1. Balasubramanian.P and Edwards.D.A. (2008), ‘A Delay Efficient Robust Self-Timed

Full Adder’, Proc. 3rd IEEE Intl.Design and Test Workshop, pp.129-134.
2. Brej.C.F. (2003), ‘Early Output Logic using Anti-Tokens’, 12th International Workshop
on Logic and Synthesis.
3. Chaitali Chakrabarti, Mohan Viswanath, and Robert M. Owens (1996), ‘Architectures

for Wavelet Transforms: A Survey’, Journal of VLSI signal processing, Vol.14, pp.171-
192.
4. Charles Brej and Doug Edwards (2009), ‘Forward and Backward Guarding in Early
Output Logic’, 12th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, pp.226-229.
5. Charles Brej (2005), ‘Early Output Logic and Anti-tokens’, Ph.D. thesis, University of
Manchester.
6. Isidro Urriza, Jose I. Artigas, Jose I. Garcia, Luis A. Barragan and Denis Navarro
(1998), ‘VLSI Architecture for Lossless Compression of Medical Images Using the
Discrete Wavelet transform’, Design Automation and Test in Europe (DATE’98),
pp.196.
7. Jens Sparso (2006), ‘Asynchronous Circuit Design A Tutorial’, Technical University of

Denmark.
8. Keshab K.Parhi (1999), ‘VLSI Digital Signal Processing Systems, Design and
Implementation’, John Wiley and sons, Inc.
9. Mansouri.A, Ahaitouf.A, and Abdi.F. (2009), ‘An Efficient VLSI Architecture and FPGA
Implementation of High-Speed and Low Power 2-D DWT for (9, 7) Wavelet Filter’,
International Journal of Computer Science and Network Security, Vol.9, No.3, pp 50-
60.
10. Min-An Song, Lan-Da Van, Ting-Chun Huang, and Sy-Yen Kuo (2004), ‘A
Generalized Methodology for Low-Error and Area-Time Efficient Fixed-Width
Booth Multipliers’, The 47th IEEE International Midwest Symposium on
Circuits and Systems, pp 9-12.
11. Po-Cheng Wu and Liang-Gee Chen (2001), ‘ An Efficient Architecture for Two-
Dimensional Discrete Wavelet Transform’, IEEE Transactions on Circuits and
Systems for Video Technology, Vol.11, No.4, pp.536-545.
12. Rafael C.Gonzalez and Richard E.Woods (2002), ‘Digital Image Processing’, Pearson
Education, Asia, II Edition.
13. Seetharaman.G, Venkataramani.B and Lakshminarayanan.G. (2008), ‘VLSI

implementation of Hybrid wave-pipelined 2D-DWT using lifting scheme’, Hindawi
Publishing Corporation, VLSI Design, pp.1-8.
14. Senthilkumar.A and Natarajan.A.M. (2008), ‘Design of High Speed Asynchronous

Pipelined FIR Filter Using Quasi Delay Insensitive Reduced Slack Pre- charged Half
Buffer’, International Journal of Applied Science and Engineering, pp.181-197.
15. Tinku Acharya and Chaitali Chakrabarti (2006), ‘A Survey on Lifting-based

Discrete Wavelet Transform Architectures’, Journal of VLSI Signal Processing,
pp.321-339.
16. Volnei A.Pedroni (2005), ‘Circuit Design with VHDL’, Prentice-Hall of India Private
Limited.

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EARLY OUTPUT LOGIC BASED FILTER BANK STRUCTURE

CONCEPT OF EARLY OUTPUT LOGIC

Figure 3.1 DIMS OR gate

Table 3.1 DIMS behavior

Table 3.2 Early output OR gate behavior

A DIMS gate has the following properties:

1) Outputs NULL when all inputs are NULL.

Figure 3.2 Early Output Pipeline Stage

EARLY OUTPUT GATES

Logic gates such as AND and OR have a 50% probability of generating a

Figure 3.3 Two input early output OR gate

Figure 3.4 Two input early output AND gate.

DUAL-RAIL FULL ADDER USING EARLY OUTPUT GATES

Figure 3.5 Dual-rail full adder using early output gates.

DUAL-RAIL BOOTH MULTIPLIER USING EARLY OUTPUT GATES

BASIC FILTER STRUCTURE FOR IMPLEMENTING 2-D DWT

Figure 3.8 Basic filter structure for 2-D DWT.

1. Balasubramanian.P and Edwards.D.A. (2008), ‘A Delay Efficient Robust Self-Timed

3. Chaitali Chakrabarti, Mohan Viswanath, and Robert M. Owens (1996), ‘Architectures

7. Jens Sparso (2006), ‘Asynchronous Circuit Design A Tutorial’, Technical University of

13. Seetharaman.G, Venkataramani.B and Lakshminarayanan.G. (2008), ‘VLSI

14. Senthilkumar.A and Natarajan.A.M. (2008), ‘Design of High Speed Asynchronous

15. Tinku Acharya and Chaitali Chakrabarti (2006), ‘A Survey on Lifting-based

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