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Before looking at register operations, I'd like to point out some of the block
diagrams of registers that we'll be using.
Not shown in the above illustration is that we can refer to any group of bits
in a register, not only the upper or lower half. For example, in a 16 bit
register named R we could refer to the 8 bits exactly in the middle as
R(4-11).
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CSC 201 - Introduction to Computer Organization
Microoperations
I will now discuss each of the above types of microoperations and give a
couple of examples. I'll also give listings of all the varieies of operations
that we'll be using under each of the types.
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CSC 201 - Introduction to Computer Organization
Arithmetic Microoperations
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CSC 201 - Introduction to Computer Organization
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CSC 201 - Introduction to Computer Organization
Logic Microoperations
Some examples are, suppose R1 and R2 are 8 bit registers. Suppose the
contents of R1 are 11011011 and we want to "clear" the leftmost 4 bits (that
is convert them to 0). To do this we could set R2 to equal 00001111, then
the operation R1 ←R1 ∧ R2 will convert R1 to 00001011 as desired.
Suppose that instead of changing the 4 leftmost digits of R1 to 0, we want to
set them to 1. To do this, let R2 = 11110000 then R1 ←R1 ∨ R2 will
convert R1 to 11111011. You can do similar masking with XOR ... simply
go through both involved registers bit by bit doing XOR on the two bits.
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CSC 201 - Introduction to Computer Organization
Shift Microoperations
There are six shift microoperations shl that shifts the bits of a register one
place left and shr that shifts the bits of a register one place right; cil that
shifts the bits of a register one place left with the leftmost bit being circled
back to the right and cir that works similarly but to the right; ashl that shifts
all bits except the sign bit of a register to the left but not into the sign bit and
ashr that shifts all bits excluding the sign bit to the right.
Eight-bit examples
Symbolic After shift:
Type designation Source R2 Destination R1
shift left R1 ← shl R2 10011110 00111100
shift right R1 ← shr R2 10011110 01001111
circular shift left
R1 ← cil R2 10011110 00111101
circular shift right
R1 ← cir R2 10011110 01001111
arithmetic shift left
R1 ← ashl R2 10011110 10111100
arithmetic shift right
R1 ← ashr 10011110 10001111
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CSC 201 - Introduction to Computer Organization
The logic diagram that would premit something like this to happen might
looks like the following:
Notice that in the logic diagram on the previous page, data is loaded into
register RO only if K1 = 1 or K2 = 1. However, what is loaded into R0
depends on K1. If K1 = 1 then the multiplexer feeds R1 through to R0. But
if K1 = 0 then it is R2 that is let through to R0.
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CSC 201 - Introduction to Computer Organization
In a typical digital system, we may have many registers. We will also want
it to be possible for the contents from any register to be transferred to any
other register. To do this, every register would need to have its own
dedicated multiplexer, for example
This may be okay if the number of registers is not too large. But as we
develop systems with larger number of registers, the fact that each has to
have it's own dedicated multiplexer soon will show that this plan may not be
the best one.
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CSC 201 - Introduction to Computer Organization
The lines in red is the bus, since the data on it is accessible to all three
registers R0, R1 and R2.
To see how this works, consider the following table :
Select Load
Register Transfer S1 S0 L2 L1 L0
R0 ← R2 1 0 0 0 1
R0 ← R1, R2 ← R1 0 1 1 0 1
R0 ← R1, R1 ← R0 not possible
So, even though there may be some things we cannot do with a bus-based
transfer system and can do with a multiplexer-based transfer system, the bus-
based system is so much more efficient that this is the approach most
frequently used for many parts of a computer.
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CSC 201 - Introduction to Computer Organization
Memory Transfer
For the purpose of this course, memory transfer will refer to either a transfer
of data from one word in memory to some register, or a transfer of data from
one register to some word in memory.
For example, if register AR contains the address of the word in memory that
we are interested in and DR is the register from which we will transfer data
to memory or the register that will receive the data from memory then the
following transfer statement
read:DR ←M[AR]
transfers the data from the memory word whose address is in AR to register
DR when read = 1. The statement
write:M[AR] ← DR
transfers the data from register DR to the memory word whose address is in
AR when write = 1.
On some digital systems there are two registers that are attached to memory.
They are the address register AR which will hold the address of the word in
memory that we want ot use, and the data register DR that will hold the data
that either will be written into memory or read from memory.
An alternative approach is to use an address bus and a data bus. This way
memory can be accessed by a variety of registers. You will not have to first
move the contents of R1, for example, to AR then use AR to access the
appropriate word in memory. Rather you can use R1 as the address register
for memory. Examples:
read:R3 ← M[R2]
transfers data from the memory word whose address is in R2 to register R3
when read = 1 and
write:M[R7] ← R0
transfers data from R0 to the memory word whose address is in R7.
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