Thin Solid Films 517 (2009) 1710–1714

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Thin Solid Films

j o u r n a l h o m e p a g e : w w w. e l s e v i e r. c o m / l o c a t e / t s f

Analysis and simulation of the post-breakdown leakage current in electrically

stressed TiO2/SiO2 gate stacks
E. Miranda a,⁎, J. Tinoco b, I. Garduno c, M. Estrada c, A. Cerdeira c
a
Departament d'Enginyeria Electrònica, Universitat Autònoma de Barcelona, Edifici Q, 08193, Bellaterra, Spain
b
Microwave Laboratory, Université Catholique de Louvain, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, Belgium
c
Sección de Electrónica del Estado Sólido, Depto. Ingeniería Eléctrica, CINVESTAV-IPN, Av. IPN, 2508, CP 07730, D.F. México, México

a r t i c l e i n f o a b s t r a c t

Article history: The post-breakdown leakage current in electrically stressed metal-oxide-semiconductor structures with thin
Received 23 July 2007 stacked layers of titanium dioxide (TiO2) over silicon dioxide (SiO2) was investigated. The samples were
Received in revised form 7 July 2008 obtained by plasma oxidation at room temperature. Multiple dielectric breakdowns were induced by the
Accepted 26 August 2008
application of successive high-field voltage ramps. The resulting current–voltage characteristics were
Available online 9 September 2008
simulated using an equivalent electrical circuit model consisting in a diode with series and parallel
Keywords:
resistances, which is solved using the Lambert W function. We show that after the first breakdown event the
MOS current that flows through the non-damaged gate stack area may still play a major role in determining the
High-κ shape of the post-breakdown current–voltage characteristic. Similarities and differences with previous
Reliability studied systems are discussed.
Oxide breakdown © 2008 Elsevier B.V. All rights reserved.

1. Introduction reducing the overall dielectric constant of the stack. A comprehensive

In recent years, a wide variety of materials with high dielectric
constant (high-κ) such as HfO2, Ta2O5, Al2O3, La2O3, and TiO2 among
others, have been proposed as potential replacements for conven-
tional SiO2 as gate insulators in MOS (Metal-Oxide-Semiconductor)
field-effect transistors [1]. The idea behind this change is that these
alternative dielectrics will help to reduce the tunnelling current and
thus standby power consumption while retaining oxide capacitance
values suitable for device operation in accordance with MOS scaling
rules. Although the conduction properties of many high-κs have been
extensively reviewed in literature, much less is known about their
electrical behaviour after the occurrence of one or several breakdown
(BD) events. The interest about this issue resides in the fact that
deposited high-κ dielectrics are trap-rich materials in which the
occurrence of early failure events has been demonstrated to be a
serious concern [2,3]. Moreover, the smaller band gap that exhibits
these materials respect to SiO2 also poses a warning from the
reliability viewpoint because of the larger tunnelling currents [4]. In
particular, we choose to investigate TiO2 not only for its remarkable
dielectric properties (κ ~ 80–110 [1]) but because Ti is totally
compatible with current CMOS fabrication facilities [5]. Our samples
are MOS capacitors with TiO2 films deposited on top of a thin
interfacial film of SiO2, the latter used as a transition layer between the
main gate dielectric and the Si substrate. The presence of this layer
ensures good interface properties but with the disadvantage of
⁎ Corresponding author.
E-mail address: enrique.miranda@uab.es (E. Miranda).
study of the electron transport mechanism in the fresh samples
utilized in this work can be found in [6]. There, we showed that for
gate voltages lower than 1 V, the conduction characteristics are
consistent with thermoionic emission over a potential barrier 0.85 eV
height. Here, we extend the aforementioned analysis and show that
Fowler–Nordheim (FN) tunnelling is a plausible conduction mechan-
ism for larger biases [4,5,7]. This current is used to generate traps
within the insulator and to cause the breakdown of the dielectric layer.
We will focus the attention on the post-BD current–voltage (I–V)
characteristics and propose an equivalent electrical circuit model
consisting of a diode with series and parallel resistances. Two extreme
situations that summarize the behaviour exhibited by our samples
will be analyzed: first, the case in which the contribution of the
current that flows through the non-damaged device area is compar-
able with the localized leakage current described by the diode-like
model, and second, the case in which the former current plays
absolutely no role. For this latter situation, it is shown that in certain
cases a resistive loss path must be added to the model in order to
account for the right shape of the experimental characteristics. The
fact that similar behaviours have been reported for a number of thin
dielectric materials seems indicative that diode-like conduction may
be considered the signature of post-BD electron transport.
2. The samples
Measurements were performed on MOS capacitors fabricated on
0.1 Ωcm n-type (100) silicon wafers. The SiO2 layer was obtained by
room temperature plasma oxidation (RTPO) of silicon in an N2O

0040-6090/$ – see front matter © 2008 Elsevier B.V. All rights reserved.
doi:10.1016/j.tsf.2008.08.186
 E. Miranda et al. / Thin Solid Films 517 (2009) 1710–1714
Fig. 1. Capacitance–voltage curve for the Cr–TiO2/SiO2–Si structure. tTiO2 and tSiO2 are the
thickness of the TiO2 and SiO2, respectively. The area of the device is 8.1 × 10− 4 cm2.
atmosphere using a parallel-plate reactor. The thickness of this first
layer was estimated in 2.5 nm following the procedure described in [6].
The 10 nm-thick TiO2 layer was also obtained by RTPO of sputtered
5 nm-thick metallic titanium layers. The process was carried out in an
O2 atmosphere at room temperature. With these values the total
estimated physical thickness is 12.5 nm with an equivalent oxide
thickness (EOT = tSiO2 + (κSiO2/κTiO2) tTiO2) of approximately 3.28 nm.
Chromium and aluminium were deposited as metal gate and back
contact, respectively. Finally, the samples were annealed at 350 °C in
H2. The area of the devices is 8.1 × 10− 4 cm2. Fig. 1 shows the
capacitance–voltage (C–V) curve used to extract the permittivity of
the TiO2 layer (κTiO2 ≈ 50). The EOT obtained from this C–V curve is
3.3 nm, which agrees well with estimated. For further experimental
details about the growth conditions of the two dielectric layers see
references [6,8].
Fig. 2. Set of experimental I–V characteristics obtained after successive voltage sweeps
(solid lines). The symbols correspond to the fresh I–V characteristic. The area of the
device is 8.1 × 10− 4 cm2.
1711
3. The post-breakdown model
Fig. 2 shows a sequence of post-BD I–V characteristics obtained
after the application of successive high-field voltage sweeps to the
same sample. The lowest curve (solid circles) corresponds to the fresh
I–V characteristic, which, as shown below, we associate with a FN-type
conduction model. Each sweep starts at zero gate voltage and ends
with the occurrence of a current jump. No sign of degradation is
detected if several voltage sweeps are run before the first current
jump. The details of the BD events are illustrated in Fig. 3. Each jump is
associated with the opening of a new BD path across the stacked layer.
Since we are not addressing our study from the statistical viewpoint
and we are only interested in some distinctive features of the post-BD
I–Vs, we will only analyze in detail two conduction characteristics
which are representative of the observed phenomenon. We will refer
to these curves as type A and B because of their shapes (see Fig. 2).
Type A characteristic corresponds to a single BD event and exhibits an
exponential current increase followed by a remarkable reduction of
slope. Notice that, at the highest biases (Vgate N 2 V), the fresh I–V is less
than one order of magnitude lower than the curve labelled as type A.
This means that both current components have to be considered for
Fig. 3. Details of the breakdown events shown in Fig. 2.
Fig. 4. Normalized differential conductance as a function of the applied bias for the
curves FN (solid circles), A (open circles) and B (open squares) shown in Fig. 2. The
arrows indicate the onset of the series resistance effect.
1712 E. Miranda et al. / Thin Solid Films 517 (2009) 1710–1714
Fig. 5. FN plot for the fresh I–V characteristic. C1 and C2 are the fitting parameters used
in Eq. (1). RFN is the series resistance correction. The area of the device is 8.1 × 10− 4 cm2.
simulation. On the other hand, type B characteristic corresponds to
multiple dielectric breakdowns and shows a small deviation in the
low voltage region (Vgate b 0.5 V) followed by the same change of trend
mentioned before. In this latter case, the current flowing through the
non-damaged device area is low enough to be neglected for practical
purposes. Contrary to what is observed for curve A, a detailed analysis
of curve B reveals the presence of a parallel resistive path in the low-
voltage region. The effect of the series resistances on the fresh I–V
characteristic and on the two selected post-BD curves is illustrated in
Fig. 4 using the power exponent method [9], i.e. a plot of the
normalized differential conductance g = dlnI/dlnV as a function of the
applied voltage. First, notice the change of conduction mechanism in
the curve corresponding to the fresh sample around 0.8 V as well as
the reappearance of this latter component in curve A for voltages
above 2 V. The increase of g for curve A can be explained by the fact
that for Vgate N 2 V, the slope of the post-BD I–V characteristic becomes
progressively dominated by the background current component,
which exhibits a higher value of g. Second, the reduction in height
and shift of the peak for the type B curve is indicative of the presence
of a parallel resistance path [9].
For the region of the fresh I–V characteristic relevant to our study
(Vgate N 1 V), we assume a FN model:
IFN ¼ C1 ðV−IFN RFN Þ2 exp ½−C2 =ðV−IFN RFN Þ
where C1 and C2 are constants and RFN is a series resistance. Notice
that this is an implicit equation for the tunnelling current IFN that
must be solved numerically. The parameters in Eq. (1) can be extracted
Fig. 6. Equivalent circuit model for post-BD conduction. The box labelled IFN
corresponds to the current flowing through the sample prior to the BD event.
D represents a diode and RS and RP are series and parallel resistances, respectively.
Fig. 7. Normalized differential conductance–voltage characteristic calculated using
Eq. (5). The dashed line corresponds to the exponential regime, whereas the dotted line
corresponds to the resistance limit.
from the FN plot as shown in Fig. 5. RFN is obtained by minimizing the
linear correlation coefficient associated with the experimental data,
whereas C1 and C2 are obtained by the least-squares method. Within
this approach, C1 and C2 are effective parameters that cannot be
straightforwardly correlated to the actual height of the stack barrier
because of the combined dielectric system SiO2/TiO2. Since the
analysis of the tunnelling current in terms of potential drops and
effective masses in both dielectrics is out of the scope of this work, we
emphasize that Eq. (1) should be only considered as a suitable
representation for the current in the fresh sample. However, taking
into account the continuity of the displacement electric field at the
SiO2/TiO2 interface, the flatband voltage and band bending corrections
as well as the potential drop in the series resistance, Eq. (1) would be
consistent with FN conduction through the TiO2 layer for voltages
above 1 V. Notice that there is a large spread in the reported values for
ð1Þ
Fig. 8. Fitting of the post-BD I–V characteristics. Solid circles correspond to the current
flowing through the fresh sample, while open symbols are post-BD measurements. The
model parameters for the solid lines are: type A: I0 = 2 × 10− 9 A, n = 2.06, RS = 925 Ω,
RP = ∞, and type B: I0 = 4 × 10− 6 A, n = 3.67, RS = 75 Ω, RP = 4.7 KΩ. The area of the device is
8.1 × 10− 4 cm2.
 E. Miranda et al. / Thin Solid Films 517 (2009) 1710–1714 1713

Fig. 9. Details of the experimental and simulated I–V characteristics: a) high bias range and b) low bias range. Symbols correspond to experimental data and lines are simulations. The
dashed line in a) is obtained using solely Eq. (1) with the parameters of curve type A in Fig. 7. The solid line is the total current. The dashed line in b) is obtained with the parameters of
curve type B in Fig. 7 but with RP = ∞. The area of the device is 8.1 × 10− 4 cm2.

the conduction band offset between SiO2 and TiO2, from 2 eV in [10] to On the contrary, for large applied voltages, it can be shown that W
2.4 eV in [5]. (X) becomes a linear function of V, i.e. W[X(V)] = a + (nVT)− 1 V, where a
In order to capture the diode-like behaviour and in view of the is a constant. Then, Eq. (5) reads:
study reported in [11] for the normalized differential conductance, we
V
propose the equivalent circuit model illustrated in Fig. 6. According to g≈ h iV!
!∞
1 ð7Þ
this scheme, the post-BD current component IBD is given by the nVT 1 þ a þ ðnVT Þ−1 V
expression:


  Both limits of Eq. (5) are illustrated in Fig. 7 and the overall
V−IBD RS V−IBD RS behaviour is in total agreement with the experimental curves shown
IBD ¼ I0 exp −1 þ ð2Þ
nVT RP in Fig. 4.
The total current that flows through the device is thus calculated as
where I0 is a constant, VT = 26 mV the thermal voltage, n the ideality IT = IFN + IBD, where IFN is the current in the fresh sample and IBD the
factor, and RS and RP series and parallel resistances, respectively. post-BD current given by Eqs. (1) and (3), respectively. Simulation
Eq. (2) has analytic solution in terms of the Lambert W function, i.e. results are shown by the solid lines in Fig. 8. The fitting details for the
the solution of the transcendental equation W(x)exp[W(x)] = x [12]: type A curve are illustrated in Fig. 9a. Notice that while Eq. (3) predicts
   a linear I–V characteristic for Vgate N 1 V (g ≈ 1), the experimental curve
nVT I 0 RS RP RP ðV þ I0 RS Þ V−I0 RP
IBD ¼ W exp þ ð3Þ remarkably departs from this trend. In fact, the post-BD curve exhibits
RS nVT ðRS þ RP Þ nVT ðRS þ RP Þ RS þ RP the shape of the fresh I–V characteristic in agreement with the circuit
topology of Fig. 6. The effect of including or not the parallel resistance
For the sake of simplicity, let us analyze the particular case in path in the case of type B curve is shown in Fig. 9b. As the applied bias
which RP = ∞. If we neglect the −1 in Eq. (2) we can obtain an analytic is increased, the leakage current enters into the exponential regime
expression for g. We calculate the derivative of the Lambert W but soon after it becomes linear with the applied voltage because of
function using the property: the potential drop across RS.

dW W ð xÞ
¼ ð4Þ 4. Discussion
dx x½1 þ W ðxÞ

so we obtain: The expression for the post-BD I–V characteristic introduced in the
previous Section (Eq. (2)) is an extension of a previous model
 
−1
dlnIBD V I 0 RS V þ I0 RS developed for broken down ultra-thin SiO2 films [11]. In that report,
g¼ ≈ 1þW exp ð5Þ the tunnelling current flowing through the non-damaged device area
dlnV nVT nVT nVT
was not considered and no current contribution associated with a
This function is plotted in Fig. 7. For gate voltages lower than 0.2 V, parallel leakage path was detected. Now, these features have been
W(X) bb 1, where X is the argument of W in Eq. (5). In this case, g is taken into account in order to capture the details of the conduction
linearly related to the applied voltage: characteristics. Particularly noteworthy is that the observed behaviour
for the TiO2/SiO2 stack closely resembles what we have measured in
V another high-κ dielectric such as lanthanum oxide (La2O3) [13]. The
g≈ ð6Þ
nVt model parameters (I0, n, RS and RP) found for La2O3 and the TiO2/SiO2
1714 E. Miranda et al. / Thin Solid Films 517 (2009) 1710–1714
Fig. 10. Comparison of post-BD curves obtained in the TiO2/SiO2 samples and in the
La2O3 samples (data from Ref. [13]).
systems are quite comparable, which seems to indicate that the diode-
like behaviour is rather insensitive to the specific features of the
insulating material (see Fig. 10). However, it is worth emphasizing that
these similarities do not imply at all that the current flowing through
the non-damaged gate stack is irrelevant for the description of the
post-BD current as clearly demonstrated in the previous Section.
There, we showed that the leakage current that flows through the
localized spot can be of the same order of magnitude than the current
flowing through the rest of the device area and this should be taken
into account if an accurate modelling of the gate current is required.
We have also found that the way the BD event takes place in SiO2 and
in the system TiO2/SiO2 during a voltage sweep is very similar, namely
by abrupt jumps in the I–V characteristics (see Fig. 3). This is different
from what is observed in La2O3, which exhibits a kind of progressive
breakdown. We surmise that the difference may arise from the
presence of the SiO2 layer, which, because of its lower permittivity, is
able to withstand most of the applied field before exhibiting the
current runaway. Finally, we have found for type A curve an ideality
factor n ≈ 2, which is within the range expected for nonideal junction
diodes [11], and which supports the idea that Eq. (3) goes beyond a
convenient representation but reflects the formation of such a
physical structure after BD. This agrees well with a recent paper by
Ranjan et al. [14], who have linked the BD event in hafnium dioxide
(HfO2) with the formation of a metal-like filament across the oxide
layer. They found n b 1.3 and a Schottky barrier height in the range
0.02–0.4 eV. Neither series nor parallel resistances corrections were
included in this latter treatment. A higher value of n, and therefore a
larger departure from ideality, such as that obtained for curve type B in
Fig. 8 (n ≈ 3.6), may be attributed to the combined effect of several BD
paths.
5. Conclusion
The post-BD conduction in thin TiO2/SiO2 stacked layers obtained
by RTPO was investigated. A simple circuit model that captures the
fine details of the I–V characteristics under these circumstances,
especially those occurring at very low and high biases, has been
proposed. In view of the reported results and our past experience in
the field of dielectric BD, the presented model seems to describe the
general features of the post-BD behaviour of a wide variety of
dielectric materials. The flexibility of the model as well as the
existence of well-behaved analytical expressions for the post-BD
current and its derivative is of utmost importance in connection with
circuit simulators.
Acknowledgments
The authors acknowledge the support from CONACYT-Mexico
(Project number 39708) and MEC-Spain (Project number TEC2006-
13731-C02-01). E. Miranda thanks Prof. H. Iwai for data provision on
La2O3.
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