Digital System Design: Dr. Shoab A. Khan

Digital System Design
Introduction
Lecture 1
Dr. Shoab A. Khan

Course Information
 Prerequisites:
 Logic Design,
 Computer Architecture/Organization
 Signals and Systems/ Digital Signal Processing
 Text Book
 Digital Design of Signal Processing System by Shoab
Khan Feb 2011, John Wiley & Sons
 References
 Verilog HDL-A guide to digital design and synthesis by
Samir Palnitkar
 Advanced Digital Design With Verilog HDL by Ciletti,
Michael D.
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 2
Introduction
 Digital Design for Signal processing System focuses
 Mapping Signal Processing applications in VLSI
 Learning the transformations and tricks that results in
optimal mapping in competing design space of
● Area
● Power dissipation
● Performance
● Testabliity
 VLSI has enabled solutions to intractable
engineering problems
 Rapid advancement has led to new dimensions in
the core subject of VLSI
 VLSI has revolutionized the commercial market
Historical Perspective and Importance
 The start of digital system designs can be traced back with

the evolution of switches: Relays (1930s)
 Then came the vacuum tubes (1940s) and discrete
transistors (1950s)
 These inventions resulted in Integrated circuits (ICs)
containing transistors (1960s--present).
 IC’s originally contains about ten transistors now billions of
transistors are placed on a single piece of silicon
 This capability empowers designers to create solutions that
once believed to be computationally intractable
 This makes the subject of digital design interesting to learn
 The techniques learnt in the course can be used in

designing digital systems covering a wide spectrum of
digital signal processing (DSP) and other applications
Digital Systems in DSP Applications
Wire-line speed
encryption, compression Mobile Wireless
and routing applications
Medical
Imaging
Arial Imaging
Real Time Digital

Systems in DSP
Digital
Applications Radiographic
Image
Video
Communicatio
ns
Multimedia in
Space
digital Cameras
Imaging
Speech and Cell Phones
Applications
compression Wearable
Radars and
and recognition Computers
Communication
and Electronics
Intelligence
5
Systems
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan
Fueling the Innovation: Moore’s Law
 The advancement and growth in VLSI has been

exponential
 In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every 18 to 24 months.
 He made a prediction that semiconductor technology

will double its effectiveness every 18 months
Moore’s Law
16
Log2 of the number of components for

 Gordon Moore, founder of 15
14
13
Intel, in 1965 noted that the 12
integrated function
11
number of transistors on a 10
9
chip was doubling every 18 8
7
to 24 months and made the 6
5
prediction for future 4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Moore’s Plenary Address at ISSCC 2003
NO EXPONENTIAL IS
FOREVER . . .
BUT
WE CAN DELAY
“FOREVER”
Intel continues to ride on the Moore’s Curve
22 nm chip
Intel Itanium-2 has 1.7 Billion transistors per die

Core i5
Intel York field 8-Core (45 nm)
2,000,000,000
Quad-Core Itanium Tukwila
1,000,000,000 GT 200
RV 770
Dual-Core Itanium 2
POWER 6
Transistor count
G80
Itanium 2 with 9 MB cache K10
Core 2 Quad
Core 2 Duo
Itanium 2
Cell
100,000,000 K8
P4 Barton
Atom
K7
K6-III
10,000,000 K6 PIII
PII
1,000,000 486
K5
386
Pentium
100,000 286
8088
10,000
8080
2,300 4004
8008
Number of transistors on a die doubles every 18 months
1971 1980 1990 2000 2008 2009 2010 2011
2.9 billion transistor Chip: Intel still pushing forever
 22 Sep 2009, Intel President and

CEO Paul Otellini showing a
silicon wafer containing the first
working chips built on 22nm
technology
Intel Progress
 Intel plans to release chips based on a 22 nanometer
process technology in the second half of 2011
 The 22nm chip integrates more than 2.9 billion

transistors into an area the size of a fingernail
 This doubles the density of the current 32nm chips
 Most of Intel’s CPUs today are based on 45nm process
 By comparison, the Intel 4004 microprocessor released

in 1971 was based on 10,000nm process.
(A human hair is approximately 100,000 nanometers)
Flavors of Digital IC Technology
 Standard microprocessors
 In PCs, server class machines and embedded devices
 Memory chips (SRAM, DRAM)
 Application specific ICs (ASICs)

 custom designed to match specific application
 optimized for low-power, low-cost, high-performance
 high development cost
 Field programmable logic devices (FPGAs, CPLDs)

 Configurable logic
 short time to market
 relatively high part cost
A Typical Digital System
Consists of Hybrid
technologies
Control Panel
 ASICs
 DSPs ASIC
Controller Process
GPP/
 FPGAs ASIC µProcessor User interface
process
 Interfaces
Shared Bus
FPGA DSP DSP CODEC
FPGA
Dual Port Memeory Analog

interface
RF Interface
A new trend: Multi Core based Systems
 Applications best mapped on GPPs
 High-end computing applications demand more and

more computational power in GPPs
 Multiple cores of GPPs are being incorporated in a
single System on Chip (SoC) configuration
 Placing multiple cores of high-end processor on a single
chip improves
 performance
 high reliability
Examples of Multi Core Trend
 2001 IBM Dual-Core IBM POWER4

 2002 IBM POWER4+
 2003 HP PA-RISC 8800 Dual Core CPU
 2004 Sun Microsystems UltraSPARC IV Dual
Core CPU
 2004 IBM Dual Core POWER5
 2005  PowerPC 970 MP,
 Cell Microprocessor (8 Cores),
 Xbox 3 Cores
Multi Core Trend (Cont)
 2005 Sun UltraSPARC T1 8-Core CPU

 2005 Intel Pentium D
 2006 Intel Core Duo, Core 2 Duo
 2006 Intel 80-core teraflop processor
 2007 Intel Quad-Core CPU
 2007 Sun Rock, 8-Core CPU
 2009 Intel Yorkfield 8-Core (45 nm)
NoC Connects Multi-cores
 Network on Chip (NoC) design paradigm addresses
issues of scalability of on-chip connectivity and inter
cores communication
 Complex designs are integrating increasing number of
Multi-Processor on a single SoC (MPSoC)
 NoC offers a good solution for
 Scalable and effective infrastructure
 The NOC provides
 higher bandwidth
 low latency
 modularity
 scalability
 a high-level of abstraction to the system
NoC for Multi Core Designs
 An NoC based Multi core

SoC design PE PE PE PE
NI
 Network Interface (NI)
Controller interfaces NoC
with PEs PE PE PE PE
 Routers to route packets Router
 Links to connect routers

PE PE PE PE
PE PE PE PE Link
Example Application:Communication System
 Algorithms in a Communication transmitter and receiver
 Mapping on to a system with conventional target technologies
 ASIC, FPGA and DSP
RF Channel Speech
RX D/A DDC Demod D/A
Decoder Decoding
RF
Synthecizer
Power
Amplifier
RF Channel Speech A/D
A/D DUC Mod
TX Encoder Encoding
RF-Section RF- ASIC FPGA/ DSP Audio

Interface ASIC Interface
Power
User Display
Management
Controller Keyboard
Sim Card
Micro-Controller
Design Strategies
 GPP General purpose
 programming flexibility Flexibilty

Microprocessor
 High code and low computationally Digital Signal
intensive code mapping Processor

GPP
 High power consumption Field

Programmab
le Gate
 DSP Array
DSP
 Programming flexibility
 Computationally intensive & Non Application
Specific
Integrated
FPGA
structured code Circuit

Structured
 FPGA ASIC
Power Consumption
 Computationally intensive structured ASIC
code
 Programmability is more complex
 ASIC
 Lower cost, low power
 No flexibility of programming
 Standard algorithms
Flexibility vs Efficiency
 Efficiency verses flexibility Programmable CPU

Flexibility
tradeoff goes up
Programmable DSP
 GPP
Application Specific
 DSP Application Specific Instruction Set
Processor (ASIP)
solution
 HW based Instruction set Application
Specific Processor
of dedicated design on an
FPGA or ASIC Efficiency
Design decision and complexity
Impact of Design
Decisions
 Conceptual level design
decisions are less complex Conceptual Level
but have a grave impact on High Level
the design RT Level
 The complexity increases Gate Level
as design moves down in Transistor Level
the design cycle

Complexity
 High level design decisions

are very critical
Example: Design Partitioning and Mapping
 A Satellite burst modem receiver
 DSP maps irregular code intensive application
● Burst detection
● Parameter Estimation
● Correction loops
● Demodulation
 FPGA maps regular code intensive and interfaces
● Forward Error Correction Coding
● Glue Logic
 ASICs standard code intensive
● Digital Down Converter
 GPP maps code intensive and user interfaces
● Modem control software
● Initialization and configuration software
● User interface
ASIC DUC &

DCC RAM
From RF Board ADC DSP

Burst Detection
FPGA
Param Estimation
DAC Correction Loops
Glue Logic
To RF Board Viterbi Algorithm
DDFS
Flash
µC
SRAM
Shared
bus
I/O Bitstream
Output
INIT
!SOB or
!UW
EOB SOB
Detection
SOB &
UW
FEC &
Deframing
Estimation
!EOB
Demodulation
Example: Burst Receiver Designed in 1997-98
HSP52014 SBSRAM
From RF Board A/D
TMS320C6201
8-bit DAC & Xilinx 4062
LPF
To RF Board
DDS
FLASH
68332
49.152 MHz
SRAM
amplifier &
squarer
Sine wave
clock square wave I/O Bitstream
output Output
CARE APICTA Award Winning Software Defined
Radio Digital Signal Processing Board
Clock Generator
AD9513
3 outputs
/2
IN SPI
I-Input AD9640
AD8352 DUAL ADC SSN
Differenti 14BIT, 105 MSPS Silicon Serial Number
47
al Amp AVDD=1.8V/310mA
IN
DVDD=1.8V/34mA
Q-Input Ethernet PHY
DRVDD=3.3V/35mA
64-LFCSP_VQ DP83848I Ethernet
16-LFCSP_VQ IOVDD=3.3V/150mA Interface
AVDD=3.3V/100mA? RJ45
8 Channel ADC LQFP-48
HMC610 RSSI MCP3008 4-Bit
RSSI Analog VD=3.3V/0.5mA AUDIO SERIAL PORT
SOIC-16
x2 ASP HEADER
Interface GAIN CONTROL (6-BIT)
FPGA
20
RS232 Interface DB9
PA interface 6-Bits Output power control SPARTAN3
XC3S1500FG676I Spartan3
Filter Selection 3-Bit Rx Filter Selection - XC3S2000FG676I SUPPORTS
RS232 TRANSCEIVER
LVCMOS-1.8
MAX3232EID
T/R Switch 1-Bit T/R Control SOIC-16
VCCINT=1.2V/
DSP 2x MT47H64M16BT-5E
Sythesizer Interface 5-Bit Frequency control
470mA TMS320DM6446 1G DDR SDRAM
32BIT
VCCAUX=2.5V/ HPI / VLYNQ CVDD 1.2V/ 64M x 32
interface 1.8VD/mA?
DUAL Channel 100mA 767mA
IN LVCMOS_1.8V
AMP 14 bit , VCCO1=3.3V/mA DVDD 1.8V/
I-Output 28F256J3, 128Mb
FILTER 125 MSPS (Max) 102mA
NETWORK DAC, VCCO2=2.5V/mA 16MB Intel Strata flash
32
DVDD 3.3V/6mA 3.3V/80mA
Not DAC2904,
IN
implemente VA=3.3V/64mA
Q-Output d VD=3.3V/19.5mA
TQFP-48 OSC
EXP JTAG
16-32 IO PBGA-N361
HEADER
PLATFORM
FLASH JTAG
XCF08P 3.3VD/20mA
Digital Power
FG-676 (BGA)
167
(SMPS) Analog
1.2VD (LDO Linear PSU) FSG-48 (BGA)
IN 1.8VD 1.8VA
2.5VD 3.3VA GC5016
POWER 3.3VD Quad Wideband DUC/
IN Title: Tranceiver Board
DDC PBGA-252
Size: A Revision: 1.3
VPAD=3.3V/180mA Date: 08/04/08 Drawn by: ASK
VCORE=1.8V/420mA
Software Defined Radio
FPGAs play a key role in designing all configurable HW in an SDR
General Purpose
FPGA
Processor
DSP
Example: SoC for Carrier-class VoIP Media Gateway
 Carrier Class VoIP
Media gate performs NI
on thousands of voice DTMF LEC
C
DSP
channels NIC
R
NIC
R
NIC
R LEC
 DTMF detection and NI

NIC
N
Links
generation DTMF LEC

CDSP
R
 Line Echo NIC

R
NIC
R
NIC
R
Router
Cancellation
 Voice compression
and decompression
TDM_if/
 Multiple layers of PCIe

NIC
µC
NIC
IP_if
NIC
application-specific R R R
PEs are linked with an

NoC for inter-
processor
communication
Mixed-Signal System on Chip
 If volume production is quite

RF Interface
high Mixed Signal SoC is an
attractive design option ASIC DSP
I/O
 The SoC integrates on a single
chip System µ-
Controller controller
 RF
 Microcontroller Mem
 DSP
 ASIC logic
 on-chip RAM
 requisite interfaces
Summary
 An embedded system implementing DSP application consists

of hybrid technologies
 GPP maps code intensive part, DSP irregular computational
intensive, FPGA regular code intensive and ASIC standard
algorithm
 Mixed signal SoC are designed for complex applications if

volumes are high
 Digital design techniques enable a designer to effectively
map algorithms on FGPAs and design custom ASICs

Digital System Design: Dr. Shoab A. Khan

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Digital System Design

Dr. Shoab A. Khan

 The start of digital system designs can be traced back with

 The techniques learnt in the course can be used in

Real Time Digital

 The advancement and growth in VLSI has been

 In 1965, Gordon Moore noted that the number of

 He made a prediction that semiconductor technology

Log2 of the number of components for

Intel Itanium-2 has 1.7 Billion transistors per die

 22 Sep 2009, Intel President and

 The 22nm chip integrates more than 2.9 billion

 This doubles the density of the current 32nm chips

 Most of Intel’s CPUs today are based on 45nm process

 By comparison, the Intel 4004 microprocessor released

 Memory chips (SRAM, DRAM)

 Application specific ICs (ASICs)

 Field programmable logic devices (FPGAs, CPLDs)

FPGA DSP DSP CODEC

Dual Port Memeory Analog

 Applications best mapped on GPPs

 High-end computing applications demand more and

 2001 IBM Dual-Core IBM POWER4

 Cell Microprocessor (8 Cores),

 2005 Sun UltraSPARC T1 8-Core CPU

 An NoC based Multi core

 Routers to route packets Router

 Links to connect routers

RF-Section RF- ASIC FPGA/ DSP Audio

 programming flexibility Flexibilty

 High code and low computationally Digital Signal

intensive code mapping Processor

 High power consumption Field

structured code Circuit

 Efficiency verses flexibility Programmable CPU

but have a grave impact on High Level

the design RT Level

 The complexity increases Gate Level

as design moves down in Transistor Level

the design cycle

 High level design decisions

ASIC DUC &

From RF Board ADC DSP

From RF Board A/D

 DTMF detection and NI

generation DTMF LEC

 Line Echo NIC

 Multiple layers of PCIe

PEs are linked with an

 If volume production is quite

 An embedded system implementing DSP application consists

 Mixed signal SoC are designed for complex applications if

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