SN54/74LS181

4-BIT ARITHMETIC
LOGIC UNIT
The SN54 / 74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic, operations on two variables and a variety of
arithmetic operations. 4-BIT ARITHMETIC
• Provides 16 Arithmetic Operations Add, Subtract, Compare, Double, LOGIC UNIT
Plus Twelve Other Arithmetic Operations LOW POWER SCHOTTKY
• Provides all 16 Logic Operations of Two Variables Exclusive — OR,
Compare, AND, NAND, OR, NOR, Plus Ten other Logic Operations
• Full Lookahead for High Speed Arithmetic Operation on Long Words
• Input Clamp Diodes

J SUFFIX
CERAMIC
CONNECTION DIAGRAM DIP (TOP VIEW) 24 CASE 623-05
VCC A1 B1 A2 B2 A3 B3 G Cn+4 P A=B F3 1

24 23 22 21 20 19 18 17 16 15 14 13

N SUFFIX
PLASTIC
CASE 649-03
24
1

1 2 3 4 5 6 7 8 9 10 11 12
B0 A0 S3 S2 S1 S0 Cn M F0 F1 F2 GND ORDERING INFORMATION
NOTE: SN54LSXXXJ Ceramic
The Flatpak version SN74LSXXXN Plastic
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

LOGIC SYMBOL
2 1 23 22 21 20 19 18
PIN NAMES LOADING (Note a)
HIGH LOW A0 B0 A1 B1 A2 B2 A3 B3
7 Cn Cn+4 16
A0 – A3, B0 – B3 Operand (Active LOW) Inputs 1.5 U.L. 0.75 U.L.
S0 – S3 Function — Select Inputs 2.0 U.L. 1.0 U.L. 8 M A=B 14
M Mode Control Input 0.5 U.L. 0.25 U.L. 6 S0 G 17
Cn Carry Input 2.5 U.L. 1.25 U.L. 5 S1
4 S2 P 15
F0 – F3 Function (Active LOW) Outputs 10 U.L. 5 (2.5) U.L.
A=B Comparator Output Open Collector 5 (2.5) U.L. 3 S3 F0 F1 F2 F3
G Carry Generator (Active LOW) 10 U.L. 10 U.L.
Output
9 10 11 13
P Carry Propagate (Active LOW) 10 U.L. 5 U.L.
Output VCC = PIN 24
Cn+4 Carry Output 10 U.L. 5 (2.5) U.L. GND = PIN 12
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.

FAST AND LS TTL DATA

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 SN54/74LS181

LOGIC DIAGRAM
7 8 2 1 23 22 21 20 19 18
Cn M A0 B0 A1 B1 A2 B2 A3 B3

S0 6 5
S1 4
S2
S3 3

VCC = PIN 24
GND = PIN 12
= PIN NUMBERS

F0 F1 A=B F2 F3 P Cn+4 G
9 10 14 11 13 15 16 17

FUNCTIONAL DESCRIPTION
The SN54 / 74LS181 is a 4-bit high speed parallel Arithmetic
Logic Unit (ALU). Controlled by the four Function Select Inputs
(S0 . . . S3) and the Mode Control Input (M), it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands. The
Function Table lists these operations.
When the Mode Control Input (M) is HIGH, all internal
carries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control Input is
LOW, the carries are enabled and the device performs
arithmetic operations on the two 4-bit words. The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn+4 output, or
for carry lookahead between packages using the signals P
(Carry Propagate) and G (Carry Generate), P and G are not
affected by carry in. When speed requirements are not
stringent, the LS181 can be used in a simple ripple carry mode
by connecting the Carry Output (Cn+4) signal to the Carry Input
(Cn) of the next unit. For high speed operation the LS181 is
used in conjunction with the 9342 or 93S42 carry lookahead
circuit. One carry lookahead package is required for each
group of the four LS181 devices. Carry lookahead can be
provided at various levels and offers high speed capability
over extremely long word lengths.
The A = B output from the LS181 goes HIGH when all four F
outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A = B output is open collector and can be
wired-AND with other A = B outputs to give a comparison for
more then four bits. The A = B signal can also be used with the
Cn+4 signal to indicate A>B and A<B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one to
each operation. Thus, select code LHHL generates A minus B
minus 1 (2s complement notation) without a carry in and
generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition
(1s complement), a carry out means borrow; thus a carry is
generated when there is no underflow and no carry is
generated when there is underflow.
As indicated, the LS181 can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the operands
labeled inside the logic symbol.

FAST AND LS TTL DATA

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 SN54/74LS181

FUNCTION TABLE
MODE SELECT ACTIVE LOW INPUTS ACTIVE HIGH INPUTS
INPUTS & OUTPUTS & OUTPUTS
LOGIC ARITHMETIC** LOGIC ARITHMETIC**
S3 S2 S1 S0 (M = H) (M = L) (Cn = L) (M = H) (M = L) (Cn = H)
L L L L A A minus 1 A A
L L L H AB AB minus 1 A+B A+B
L L H L A+B AB minus 1 AB A+B
L L H H Logical 1 minus 1 Logical 0 minus 1
L H L L A+B A plus (A + B) AB A plus AB
L H L H B AB plus (A + B) B (A + B) plus AB
L H H L A⊕B A minus B minus 1 A⊕B A minus B minus 1
L H H H A+B A+B AB AB minus 1
H L L L AB A plus (A + B) A+B A plus AB
H L L H A⊕B A plus B A⊕B A plus B
H L H L B AB plus (A + B) B (A + B) plus AB
H L H H A+B A+B AB AB minus 1
H H L L Logical 0 A plus A* Logical 1 A plus A*
H H L H AB AB plus A A+B (A + B) plus A
H H H L AB AB plus A A+B (A + B) Plus A
H H H H A A A A minus 1
L = LOW Voltage Level
H = HIGH Voltage Level
**Each bit is shifted to the next more significant position
**Arithmetic operations expressed in 2s complement notation

LOGIC SYMBOLS

ACTIVE LOW OPERANDS ACTIVE HIGH OPERANDS

2 1 23 22 21 20 19 18 2 1 23 22 21 20 19 18

A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3
7 Cn Cn+4 16 7 Cn Cn+4 16
8 M A=B 14 8 M A=B 14
LS181 LS181
6 S0 4 BIT ARITHMETIC G 17 6 S0 4 BIT ARITHMETIC G 17
5 S1 LOGIC UNIT 5 S1 LOGIC UNIT
4 S2 P 15 P 15
4 S2
3 S3 F0 F1 F2 F3 3 S3 F0 F1 F2 F3

9 10 11 13 9 10 11 13

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0
VOH Output Voltage — High (A = B only) 54, 74 5.5 V

FAST AND LS TTL DATA

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 SN54/74LS181

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

Output
p LOW Voltageg 54, 74 0.25 0.4 V IOL = 4.0 mA
Except G and P 74 0.35 0.5 V IOL = 8.0 mA VCC = VCC MIN,
MIN
VOL Output G 54, 74 0.7 V IOL = 16 mA VIN = VIL or VIH
per Truth Table
54 0.6
Output P V IOL = 8.0 mA
74 0.5

VCC = MIN, IOH = MAX, VIN = VIH

IOH Output HIGH Current 54, 74 100 µA
or VIL per Truth Table
Input HIGH Current
Mode Input 20
Any A or B Input 60 µA VCC = MAX, VIN = 2.7 V
Any S Input 80
IIH Cn Input 100
Mode Input 0.1
Any A or B Input 0.3
mA VCC = MAX, VIN = 7.0 V
Any S Input 0.4
Cn Input 0.5
Input LOW Current
Mode Input – 0.4
IIL Any A or B Input – 1.2 mA VCC = MAX, VIN = 0.4 V
Any S Input – 1.6
Cn Input – 2.0
IOS Short Circuit Current (Note 2) – 20 – 100 mA VCC = MAX

Power Supply
pp y Current 54 32
See Note 1A 74 34
ICC mA
A VCC = MAX
54 35
See Note 1B
74 37
Note 1.
With outputs open, ICC is measured for the following conditions:
A. S0 through S3, M, and A inputs are at 4.5 V, all other inputs are grounded.
B. S0 through S3 and M are at 4.5 V, all other inputs are grounded.
Note 2: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

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 SN54/74LS181

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, Pin 12 = GND, CL = 15 pF)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C di i
Conditions
tPLH Propagation Delay, 18 27 M = 0 V, (Sum or Diff Mode)
ns
tPHL (Cn to Cn+4) 13 20 See Fig. 4 and Tables I and II
tPLH 17 26 M = 0 V, (Sum Mode)
(Cn to F Outputs) ns
tPHL 13 20 See Fig. 4 and Table I
tPLH 19 29 M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(A or B Inputs to G Output) ns
tPHL 15 23 (Sum Mode) See Fig. 4 and Table I
tPLH 21 32 M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(A or B Inputs to G Output) ns
tPHL 21 32 (Diff Mode) See Fig. 5 and Table II
tPLH 20 30 M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(A or B Inputs to P Output) ns
tPHL 20 30 (Sum Mode) See Fig. 4 and Table I
tPLH 20 30 M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(A or B Inputs to P Output) ns
tPHL 22 33 (Diff Mode) See Fig. 5 and Table II
tPLH 21 32 M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(AX or BX Inputs to FX Output) ns
tPHL 13 20 (Sum Mode) See Fig. 4 and Table I
tPLH 21 32 M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(AX or BX Inputs to FX Output) ns
tPHL 21 32 (Diff Mode) See Fig. 5 and Table II
tPLH 38 M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(AX or BX Inputs to FXH Outputs) ns
tPHL 26 (Sum Mode) See Fig. 4 and Table I
tPLH 38 M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(AX or BX Inputs to FXH Outputs) ns
tPHL 38 (Diff Mode) See Fig. 5 and Table II
tPLH 22 33 M = 4.5 V (Logic Mode)
(A or B Inputs to F Outputs) ns
tPHL 26 38 See Fig. 4 and Table III
tPLH 25 38 M = 0 V, S0 = S3 = 4.5 V, S1 = S2 = 0 V
(A or B Inputs to Cn+4 Output) ns
tPHL 25 38 (Sum Mode) See Fig. 6 and Table I
tPLH 27 41 M = 0 V, S0 = S3 = 0 V, S1 = S2 = 4.5 V
(A or B Inputs to Cn+4 Output) ns
tPHL 27 41 (Diff Mode)
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
tPLH 33 50
(A or B Inputs to A = B Output) ns RL = 2.0 kΩ
tPHL 41 62
(Diff Mode) See Fig. 5 and Table II

AC WAVEFORMS

INPUT 1.3 V 1.3 V

tPLH tPHL

OUTPUT 1.3 V 1.3 V

Figure 4

A INPUT 1.3 V 1.3 V

INPUT 1.3 V 1.3 V
B INPUT 1.3 V 1.3 V tPLH tPHL
tPLH tPHL 1.3 V 1.3 V
OUTPUT
OUTPUT 1.3 V 1.3 V

Figure 5 Figure 6

FAST AND LS TTL DATA

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 SN54/74LS181

SUM MODE TEST TABLE I FUNCTION INPUTS: S0 = S3 = 4.5 V, S1 = S2 = M = 0 V

Other Input
Same Bit Other Data Inputs
Input Output
Under Apply Apply Apply Apply Under
P
Parameter Test 4.5 V GND 4.5 V GND Test
tPLH Remaining
Al Bl None Cn Fl
tPHL A and B
tPLH Remaining
Bl Al None Cn Fl
tPHL A and B
tPLH Remaining
Al Bl None Cn Fl+1
tPHL A and B
tPLH Remaining
Bl Al None Cn Fl+1
tPHL A and B
tPLH Remaining
A B None None P
tPHL A and B, Cn
tPLH Remaining
B A None None P
tPHL A and B, Cn
tPLH Remaining Remaining
A None B G
tPHL B A, Cn
tPLH Remaining Remaining
B None A G
tPHL B A, Cn
tPLH Remaining Remaining
A None B Cn+4
tPHL B A, Cn
tPLH Remaining Remaining
B None A Cn+4
tPHL B A, Cn
tPLH All All Any F
Cn None None
tPHL A B or Cn+4

FAST AND LS TTL DATA

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 SN54/74LS181

DIFF MODE TEST TABLE II FUNCTION INPUTS: S1 = S2 = 4.5 V, S0 = S3 = M = 0 V

Other Input
Same Bit Other Data Inputs
Input Output
Under Apply Apply Apply Apply Under
P
Parameter Test 4.5 V GND 4.5 V GND Test
tPLH Remaining Remaining
A None B Fl
tPHL A B, Cn
tPLH Remaining Remaining
B A None Fl
tPHL A B, Cn
tPLH Remaining Remaining
Al None Bl Fl+1
tPHL B, Cn A
tPLH Remaining Remaining
Bl Al None Fl+1
tPHL B, Cn A
tPLH Remaining
A None B None P
tPHL A and B, Cn
tPLH Remaining
B A None None P
tPHL A and B, Cn
tPLH Remaining
A B None None G
tPHL A and Bl, Cn
tPLH Remaining
B None A None G
tPHL A and B, Cn
tPLH Remaining Remaining
A None B A=B
tPHL A B, Cn
tPLH Remaining Remaining
B A None A=B
tPHL A B, Cn
tPLH Remaining
A B None None cn+4
tPHL A and B, Cn
tPLH Remaining
B None A None Cn+4
tPHL A and B, Cn
tPLH All
Cn None None None Cn+4
tPHL A and B

LOGIC MODE TEST TABLE III

Other Input
Same Bit Other Data Inputs
Input Output
Under Apply Apply Apply Apply Under
P
Parameter Test 4.5 V GND 4.5 V GND Test F i IInputs
Function
tPLH Remaining S1 = S2 = M = 4.5 V
A None B None Any F
tPHL A and B, Cn S0 = S3 = 0 V
tPLH Remaining S1 = S2 = M = 4.5 V
B None A None Any F
tPHL A and B, Cn S0 = S3 = 0 V

FAST AND LS TTL DATA

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