SFF SDR DP - MBDK Tutorial

SFF SDR development
platform
Model-based design tutorial
Version 3.1—May 2010

Revision history
Version Date Modifications
1.0 2008-05-01 First edition.
1.1 2008-06-01 Corrections of erroneous information and instructions.
2.0 2009-04-14 Updated to account for releases 3.0.0 and 3.1.0 of the ADP software tools. First official
release.
3.0 2009-09-08 Updated to account for release 3.2.0 of the ADP software tools.
3.1 2010-05-12 Updated to account for release 4.1.1 of the ADP software tools.
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on the title page. There may be differences between the document and the product, if the product was
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document at any time and without notice.
ii

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iii

iv

Table of contents
Introduction.......................................................................................................................................... 1
Purpose and structure....................................................................................................................... 1
Conventions.................................................................................................................................. 1
Glossary of terms.......................................................................................................................... 2
Technical support.............................................................................................................................. 3
Requirements........................................................................................................................................ 5
Software requirements..................................................................................................................... 5
General......................................................................................................................................... 5
DSP development software........................................................................................................... 5
FPGA development software........................................................................................................ 5
Preliminary readings......................................................................................................................... 5
Accessing the platform’s documentation...................................................................................... 6
Using the platform’s DSP....................................................................................................................... 7
Targeting the DSP.............................................................................................................................. 7
Tutorial 1—Audio loopback simulation............................................................................................. 7
Goals............................................................................................................................................. 7
Creating a new model................................................................................................................... 7
Simulating the model.................................................................................................................... 10
Running the model on your platform........................................................................................... 11
Tutorial 2—Processing an audio signal with a FIR filter.................................................................... 16
Goals............................................................................................................................................. 16
Modifying an existing model......................................................................................................... 16
Running the model on your platform........................................................................................... 17
Using the platform’s FPGA..................................................................................................................... 19
Targeting the FPGA............................................................................................................................ 19
Tutorial 3—Incorporating an FPGA in a Simulink simulation............................................................ 19
Goals............................................................................................................................................. 19
Configuring the simulation parameters........................................................................................ 23
Saving the model.......................................................................................................................... 23
Running the model....................................................................................................................... 23
Observing the results.................................................................................................................... 24
Stopping and disconnecting.......................................................................................................... 24
Using the platform’s mixed processor architecture............................................................................... 25
Tutorial 4—Using VPSS for streaming application in the FPGA model.............................................. 25
v

Goals............................................................................................................................................. 25
Saving the model.......................................................................................................................... 27
Building an FPGA model................................................................................................................ 27
Tutorial 5—Using the VPSS to stream data in a DSP model.............................................................. 28
Goals............................................................................................................................................. 28
Running the model on the platform............................................................................................. 30
Using the data conversion and RF modules.......................................................................................... 33
Tutorial 6—Using the DAC in an FPGA model................................................................................... 33
Goals............................................................................................................................................. 33
Building the FPGA model.............................................................................................................. 36
Saving the model.......................................................................................................................... 36
Tutorial 7—Using the data conversion and RF modules in a DSP model.......................................... 36
Goals............................................................................................................................................. 36
Building the model........................................................................................................................ 38
Connecting to the target and running the model......................................................................... 38
Stopping and disconnecting.......................................................................................................... 39
vi
Introduction
Introduction
This document goes over one of the applicative examples supplied with the SFF SDR development
platforms. The document treats of DSP designs and FPGA designs and, once your are done, you will
be able to perform a narrow-band FM transmission to the FRS handset supplied with the low-band
platform.
Purpose and structure

This step-by-step approach can prove useful in mastering the intricacies of model-based design with
your platform. The guide includes of number of specific elements that you should understand prior to
reading it, as they will help you understand the way the information is organized.
Conventions
In a procedure containing several steps, the operations that you must perform are numbered (1, 2, 3…).
The diamond (◊) is used to indicate single-step procedures. Lowercase letters (a, b, c…) are be used to
indicate secondary steps in a complex procedure.
Capitals are used to identify keys on the keyboard (for example, ctrl+v). All software user interface
words (for example, names of menus, commands, dialog boxes, text boxes, and options) appear in bold
font style (for example, File).
The abbreviation N/A is used to indicate something that is not applicable or not available at the time of
press. The abbreviation NC is used to indicate no connection.
This symbol is used to call your attention to important information, crucial to the correct
operation of your product.
This symbol is used to call your attention to information that may prove useful in operating
your product, but is not vital to correct operation.
1
Introduction
Glossary of terms
Throughout this document, you will find references to the following terms. Refer to the following table
as to their definitions.
Table 1 Glossary of terms
Term Definition
Application programming interface (API) An application programming interface is the interface that
a computer system, library, or application provides to allow
requests for services to be made of it by other computer
programs or to allow data to be exchanged between them.
Base design Empty design or template that is incapable of data processing and
is not instantiated in the custom logic of the board’s FPGA.
Board software development kit Abbreviated BSDK, this kit gives users the possibility to quickly
become fully functional developing C/C++ or assembly code for
the DSP, and HDL code for the FPGA through an understanding of
all Lyrtech boards’ major interfaces.
Chassis Refers to the rigid framework onto which the CPU board, Lyrtech
development platforms, and other equipment are mounted. It
also supports the shell-like case—the housing that protects all the
vital internal equipment from dust, moisture, and tampering.
Computer communication development Refers to developing custom communications applications to

communicate with Lyrtech boards.
cPCI Short for CompactPCI, refers to a 3U or 6U Eurocard-based

industrial computer where the all boards are connected through a
passive PCI backplane.
cPCI chassis system Refers to the chassis-CPU board-case system.
cPCI CPU Host CPU of the cPCI chassis system, responsible for processing
and communications between the hardware in the cPCI chassis
and the remote computer connected to the cPCI chassis system.
Default design Design loaded by default on Lyrtech boards used for FPGA design.
Digital signal processing Digital signal processing is the study of signals in a digital
representation and the processing methods of these signals.
The algorithms required for DSP are sometimes performed using
specialized devices that use specialized microprocessors called
digital signal processors (DSP).
Digital signal processor (DSP) A digital signal processor is a specialized microprocessor designed
specifically for digital signal processing, generally in real time.
Example Refers to examples used to demonstrate functions or applications

supplied with the board software development kit. For this
reason, examples come in two flavors: application examples and
functional examples.
Eurocard Refers to a European standard format for printed-circuit boards

that can be connected together in a standardized subrack.
HDL Stands for hardware description language.
2
Introduction
Term Definition
Host A host is defined as the device that configures and controls a

Lyrtech board. The host may be a standard computer or the
CPU board of the cPCI chassis system where the Lyrtech board
is installed. You can develop applications on the host for Lyrtech
boards through the use of an application programming interface
(API) that comprises protocols and functions necessary to build
software applications. These API are supplied with the Lyrtech
board.
Model-based design Refers to all the Lyrtech board-specific tools and software used
for development with the boards in MATLAB and Simulink and the
Lyrtech model-based design kit(s).
Reception Any data received by the referent is a reception. Abbreviated RX.
Reference design Blueprint of an FPGA system implanted on Lyrtech boards. It is

intended for others to copy and contains the essential elements of
a working system (in other words, it is capable of data processing),
but third parties may enhance or modify the design as necessary.
Software development Refers to development performed with and for the board with
a software development kit. Software development for a board
comes in three flavors: host software development, DSP software
development, and FPGA software development.
Transmission Any data transmitted by the referent is a transmission.

Abbreviated TX.
VHDL Stands for VHSIC hardware description language.
VHSIC Stands for very-high-speed integrated circuit.
Technical support
Lyrtech is firmly committed to providing the highest level of customer service and product support.
If you experience any difficulties using our products or if it fails to operate as described, first refer to
the documentation accompanying the product. If you find yourself still in need of assistance visit the
technical support page in the Support section of our Web site at www.lyrtech.com.
3
Introduction
4
Requirements
Requirements
Before you can use your SFF SDR development platform in developing model-based designs, you must
meet the requirements outlined below.
For details about the exact software versions supported by your SFF SDR development
platform, refer to your platform’s quick start guide.
Software requirements
To complete all the tutorials in this guide, the following software must be installed on your computer:
General
• Advanced development platform (ADP) software tools
• MATLAB
• Simulink
• Signal Processing Blockset
• Signal Processing Toolbox
You should be familiar with MATLAB and Simulink before proceeding.
DSP development software

• Code Composer Studio
• Real-Time Workshop
FPGA development software

• System Generator for DSP
• ISE Foundation
Preliminary readings
Before going through this guide, we recommend that you familiarize yourself with the following, to help
you gain a working knowledge of the SFF SDR development platform’s capabilities:
• SFF SDR development platform user’s guide

• SFF SDR development platform model-based design guide
• FAQ supplied with the platform
5
Requirements
Accessing the platform’s documentation
1 On the Windows Start menu, point to All Programs.
2 Point to Lyrtech, SFF SDR, and then click Documentation.
Your default Web browser starts and displays a page containing links to all the documents supplied with
the SFF SDR development platform.
6
Using the platform’s DSP

In this chapter, you will learn how to use Real-Time Workshop and Code Composer Studio to target the
Texas Instruments DM6446 DSP of your platform.
The results presented in this chapter are only supplied for illustration purposes. They are not
intended to represent actual results.
Targeting the DSP

To target the DSP of your platform with the model-based design kit (MBDK) from Lyrtech, you must
always perform certain procedures:
1 Create a new model or modify an existing model.

2 Simulate the model.
3 Run the model on the platform.
Tutorial 1—Audio loopback simulation

Goals
• Demonstrate how to use Simulink to build a simple design and perform a simulation
• Demonstrate how to configure the audio codec
• Demonstrate how to configure a Simulink model to monitor data and perform remote operations
Creating a new model

1 Start MATLAB.
2 At the MATLAB command prompt, type simulink.
3 On the File menu, point to New, and then click Model.
4 Right-click anywhere in the model window, and then click Model Properties on the shortcut menu
that appears.
The Models Properties dialog box appears.
5 On the Callbacks tab, in the Model pre-load function group, Fs_DSP = 32000.
The Fs_DSP variable appears as 32000 when you open the model for the first time. It is the
sampling frequency of the audio path used later on in this tutorial.
Use the sample time as a relative time base. This means that specifying a Sample Time of
1 does not force the block to run at 1 Hz, it rather forces the block to run at a frequency relative to
other blocks’ Sample Time values.
7
For example, if you specify a Sample Time of 2/48000 for block A and block B has a sample time of
1/48000, block B runs twice as fast as block A. In other words, its associated code is executed twice
as fast as that of block A.
If no I/O block forces the DSP to run at a specific sample rate, the DSP runs the code as fast as
possible. In other words, the DSP is free running. However, if you insert an I/O block such as an
audio ADC block in your model, then the Sample Time is associated to the effective sample rate
configured in the block (24 kHz, for example). This means that all the other blocks having the same
sample time as the I/O block (e.g. 24 kHz) run at the same sample rate.
If you also specify a Frame Size, then the actual frame time (i.e. the time to execute a frame) is
imposed by the following formula:
Frame time = Sample Time × Frame Size
By default, the Sample Time is 1.
Using the model properties is a good way to ensure that all your parameters remain with
your .mdl file. You can also use a .mat file to save your MATLAB workspace parameters. Refer to
Simulink Help to learn more about model properties.
6 To add the Fs_DSP variable to the MATLAB workspace parameters, type Fs_DSP = 32000 at the
MATLAB command prompt.
Alternately, exit the model, and then reopen it.
7 Insert the following blocks in the new model:

Signal processing Blockset—Signal Processing Sinks
• 1 × Vector Scope
• 1 × Spectrum Scope
Lyrtech SFF SDR DP Blockset—DSP—Onboard
• 1 × DSP Options
• 1 × Audio Codec Configuration
• 2 × Audio Codec I/O
The following dialog box appears when you add the DSP Options block in your model:
Figure 1 MBDK DSP default configuration dialog box
8 Click Yes.
This configures the default simulation parameters of your SFF SDR development platform.
9 Connect the blocks as illustrated.
8
Figure 2 Connecting blocks in the model
10 Configure the blocks as follows

Audio Codec Configuration
• Sampling Frequency: 32 kHz
• Frame Size: 128
• Sample Time: 1/Fs_DSP
Audio Codec I/O
• Frame Size: 128
• Data Type: Single
• Select the Normalize ADC samples check box
• Direction: Input
Audio Codec I/O1
• Frame Size: 128
• Select the Normalize Audio Data Samples check box
• Select the Enable Data Saturation check box
• Direction: Output
11 On the Format menu, point to Port/Signal Displays, and then click Sample Time Colors.
Selecting Sample Time Colors is a good way to have an overview of the sample times
of every block in your model. In the model at hand, all the blocks become red, indicating that all
the blocks have the same sample time (i.e. they are executed at the base sample time). Refer to
Simulink Help to learn more about this function.
12 On the Format tab, point to Port/Signal Displays, and then click Port Data types.
Selecting Port Data types is a good way to have an overview of the data types of every link
in your model. Refer to Simulink Help to learn more about this function.
13 On the Format tab, point to Port/Signal Displays, and then click Signal Dimensions.
Selecting Signal Dimensions is a good way to have an overview of the dimensions of the
signals, particularly when they are frame based. Refer to Simulink Help to learn more about this
9
function.
14 Press CTRL+D on your keyboard.

Alternately, on the Edit menu, click Update Diagram.
Figure 3 Updated model
Simulating the model

1 On the model’s toolbar, configure the simulation’s stop time as 1.
2 Select the simulation’s mode as Normal.
3 Click the play button.
Two windows appear.
4 Right-click anywhere in the windows and click Autoscale on the shortcut menu that appears.
The following results are expected.
The values on the x and y axes are accurate in terms of frequency and time because the
sample time value is equal to the sample time of the audio codec sampling frequency.
Figure 4 Time domain and frequency domain simulation results
10
Running the model on your platform
To take your simulation model and implement it on the SFF SDR development platform, you must
perform the procedures outlined in this section.
Configuring the Real-Time Workshop target

1 On the model’s Simulation menu, click Configuration Parameters.
The Configuration Parameters dialog box appears.
2 Select Real-Time Workshop.

The following appear.
Figure 5 Real-Time Workshop configuration parameters
3 Verify that System target file is rt_sdr.tlc and that Template makefile is rt_sdr.tmf.
Configuring model Solver parameters

1 If not already open, on the model’s Simulation menu, click Configuration Parameters.
The Configuration Parameters dialog box opens.
2 Select Solver.
3 On the Type list, select Fixed-step.
4 On the Solver list, select discrete.
The code generated by the MBDK DSP solution runs indefinitely, regardless of the Stop
time parameter. This parameter, however, determines the default time range of Simulink scopes
when their Time range parameters are auto.
Configuring the hardware implementation model

1 If not already open, on the model’s Simulation menu, click Configuration Parameters.
The Configuration Parameters dialog box opens.
2 Select Hardware Implementation.

The following appears.
11
Figure 6 Hardware Implementation parameters
3 Make sure that the Device type is TI C6000.

4 Click OK.
The Configuration Parameters dialog box closes.
Building the model
When building a DSP model, the building folder is always your current MATLAB folder.
◊ On the toolbar of the model window, click the build button.◊

Alternately, press CTRL+B on your keyboard. You can also point to Real-Time Workshop on the
model’s Tools menu, and then click Build Model.
When the build is successful, the ### Created Executable :{model name} message appears in the
MATLAB window.
Running the model

1 Make sure that your platform is on and that an Ethernet cable is connected to its Ethernet port.
2 Press the hardware reset button.
Refer to the platform’s user’s guide for the location of this button.
3 Connect an audio source such as an MP3 player to the line in connector.
4 Connect headphones or speakers to the line out connector.
5 On the model’s Simulation menu, click External.
6 Verify that your model is configured properly:
a On the model’s Simulation menu, click Configuration Parameters.
b Expand Real-Time Workshop, and then select Interface.
c Verify that the following parameters are configured as illustrated:
12
Figure 7 Interface selection
d Click OK.
7 In the model window, click the connect to model button.
The Lyrtech development platform detection dialog box appears.
8 Select a platform that is not in a locked state, and then click Connect to Lyrtech development
platform.
Figure 8 Lyrtech development platform detection dialog box
9 When the .out file is loaded to the DSP of the platform, the model starts automatically.
Your audio signal is displayed on the time and vector scopes. Use the auto-scale feature, if
necessary. The actual aspect of the scope depends on the audio signal.
For details about targeting the DSP with the MBDK DSP solution, refer to the model-based
design guide of the SFF SDR development platform.
Observing results
The scopes react according to the signal fed to the platform. For a better real-time display quality in the
scope, proceed as follows:
1 On the Tools menu, click External mode Control Panel.
13
Figure 9 External mode control panel
2 Click Signal & Triggering.

3 In the External Signal & Triggering window, type 1 in the Duration text box.
You must not be connected to the platform to modify this parameter.
Figure 10 External Signal & Triggering
4 Click Apply.
5 Click Close.
As a rule, when frame based, the Data Logging Size (in the DSP Options block) should be
greater than the Duration value multiplied by the frame size and the number of scopes.
Saving, stopping, and disconnecting

1 Click Disconnect from target.
2 Save the model as my_tutorial1.mdl.
3 Close the model.
14
Tutorial 2—Processing an audio signal

with a FIR filter
Goals
• Demonstrate how to use the FDA design block
• Describe various data types supported by the MBDK DSP solution•
Modifying an existing model

1 Open the my_tutorial1.mdl file or the tutorial1.mdl file (if you have not completed tutorial 1).
2 Insert the following blocks in your model:
Simulink—Math Operation
• 1 × Add
Simulink—Signal Routing
• 1 × Switch
Simulink—Signal Attributes
• 1 × Data Type Conversion
Signal Processing Blockset—Filtering—Filter Designs
• 1 × Digital Filter Design
• 1 × Buttons
Figure 11 Connecting the blocks
4 Configure the blocks as follows:

Data Type Conversion block
• Output data type mode: single
• Input and output to have equal: Real World Value (RWV)
Buttons block
• Select the Button 1 check box
15
• Clear the Button 2 to Button 5 check boxes
Switch block
• Criteria for passing first input: u2 > Threshold
5 Double-click the Digital Filter Design block.
The Digital Filter Design block implements a digital FIR or IIR filter that you design with the filter
design and analysis tool (FDA Tool).
6 In the Response Type group, select Lowpass.

7 In the Design Method group, select FIR, and then select Least-square.
8 In the Filter Order group, select Specify order, and then specify 4 in the text box.
9 In the Frequency Specifications group, on the Units list, select Hz.
10 In the Frequency Specifications group, specify 32000 for Fs, 3000 for Fpass, and 3300 for Fstop.
11 In the Magnitude Specifications group, specify 10 for Wpass and 1 for Wstop.
12 Click Design Filter.
13 When the Designing filter… Done message appears at the bottom of the window, close the Digital
Filter Design window.
Running the model on your platform

To take your simulation model and implement it on the SFF SDR development platform, you must
perform the following procedures:
Building the model

◊ On the model’s Tools menu, point to Real-Time Workshop, and then click Build Model.
Alternately, you can press CTRL+B on your keyboard.
Running the model

1 Make sure that your platform is on and that an Ethernet cable is connected to its Ethernet port.

5 On the model’s Simulation menu, click Connect to target.
Alternately, you can click the connect to target button.

Alternately, press CTRL+T on your keyboard.
Observing the results

You should see and hear the differences in your signal between when you press button S5 and when
you do not (assuming that your signals are at frequencies higher than 3 kHz, as is the case of most MP3
files). Refer to the platform’s user’s guide for the button’s location.
Saving, stopping, and disconnecting

1 Click Disconnect from target.
3 Close the model.
16
Using the platform’s FPGA

In this chapter, you will learn how to use the platform’s FPGA in your models. To achieve this goal,
you will be called upon to create an FM modulator simulation with System Generator for DSP. You will
design the simulation for narrow-band FM with a 100 kHz carrier frequency. For illustration purposes,
that model is configured with an FPGA system clock of 1 MHz, shortening simulation time. The model
used in this chapter will be reused and adapted later on to demonstrate transmissions to an FRS
handset (supplied with the platform).
• Make sure that System Generator for DSP is installed on your computer before proceeding with the
• tutorials of this chapter.
• In System Generator for DSP all the data paths are always sample based, but all the data type are •
fixed point. No floating-point data types are available.
• The results presented in this chapter are only supplied for illustration purposes. They are not •
intended to represent your actual results.
Targeting the FPGA

To target the FPGA on your platform with the MBDK, you must perform certain procedures, just as with
the DSP:
1 Create a new model or modify an existing model.

2 Simulate the model.
3 Run the model on the platform.
Tutorial 3—Incorporating an FPGA in a

Simulink simulation
Goals
• Demonstrate how to use System Generator for DSP to perform a simulation.
• Demonstrate how to use the System Generator for DSP’s DDS v5_0 block.

1 Start MATLAB.
4 Right-click anywhere in the model window, and click Model Properties on the shortcut menu that
appears.
17
The Model Properties dialog box appears.
5 On the Callbacks tab, in the Model pre-load function group, type Fs_FPGA = 1e6.
The Fs_FPGA variable is created and becomes the frequency of the system clock.
The sampling frequency specified in each block is not imposed on the FPGA clock. In a
Simulink model, the sample time is merely a tag on each “step” of an algorithm. A sampling time
of 1 would produce the same bitstream file (.bit) for the FPGA. For the spectrum scope and time
scope, it is sometimes useful to see the results of the simulation in terms of clock cycles, while
sometimes it is useful to do so in terms of seconds. Using a variable allows you to switch all the
sample times of your design simultaneously. Use a sample time of 1 for clock cycle information and
a clock period cycle for the time domain and frequency domain information.
6 Insert the following blocks in the new model:

Simulink—Simulink Sink
• 1 × Scope
• 1 × Manual Switch
Signal Processing Blockset—Signal Processing Sources
• 1 × Sine Wave
• 1 × DSP Constant
Signal Processing Blockset—Signal Processing Sinks
• 1 × Spectrum Scope
Xilinx Blockset—Index
• 1 × System Generator
• 1 × Gateway In
• 2 × Gateway Out
• 1 × CMult
• 2 × Const
• 1 × AddSub
• 1 × DDS v5_0
DDS stand for direct digital synthesizer. It is the main block used in this model. Refer to
System Generator for DSP Help for details.
A constant corresponding to the carrier frequency is added to the amplitude from the
Sine Wave block, which is then sent to the data port of the DDS v5_0 block. The frequency output,
controlled by the data port, thus changes as the amplitude of the sine wave changes.
18
Figure 12 Connecting blocks in the model

• Output data type mode: int16
• Input and output to have equal: Real World Value (RWV)
Sine Wave block
• Amplitude: 2^15-1
• Frequency: 3000
• Sample Time: 1/Fs_FPGA
• Output Data Type: single
Spectrum Scope block
• On the Scope Properties tab, select the Buffer Input check box
• On the Scope Properties tab, specify Buffer Size as 2^12
• On the Axis Properties tab, specify Frequency display limits as User-defined
• On the Axis Properties tab, specify the Minimum X-limit as 90 and the Maximum X-limit as 110
System Generator block
• Simulink System Period: 1/Fs_FPGA
Gateway In block
• Number of bits: 16
• Binary point: 0
• Sample period: 1/Fs_FPGA
Gateway Out block
• Clear the Translate into output port check box
Const block
• Clear the Sampled Constant check box
DDS v5_0 block
• Function: sine and cosine
• Output Frequencies: Programmable
• Explicit Sample Period: Inferred from inputs
• Clear the Provide enable port check box
To get two inputs from one scope, double-click the scope block. In the window that
appears (below), click the parameters button. In the Axes group, modify Number of axes to 2. Click
OK.
19
Figure 13 Getting two inputs from one scope
9 In the Constant block connected to the WE of the DDS v5_0 block, select type Boolean and
constant value 1.
10 Double-click the DDS v5_0 block.
11 On the Advanced tab, specify the following:
• DDS clock rate (MHz): 1. This is the actual clock rate of your hardware clock. A lower clock
frequency means less points to calculate, thus a faster simulation. For the purposes of this
example, use 1 MHz.
• Spurious free dynamic range (dB): 16*6. This lowers the spurious in the output signal by
increasing the resolution (bits) of the output. As a rule, 1 bit equals 6 dB of SFDR.
• Frequency Resolution (Hz): 0.2. This impacts the number of bits of the input data type at the
data input port. To determine how many bits the port needs, at the MATLAB command prompt,
type ceil(log2(1e6/0.2)), indicating that the answer is 23 bits.
• Noise shaping: Phase dithering. This noise shaping technique is necessary as the SFDR is
between 60 dB and 102 dB.
12 On the 12 Implementation tab, select Block RAM.
13 Double-click the AddSub block.
14 On the Output Type tab, select User-Defined Precision, specify the output type as Signed, the
number of bits as 23, and the binary point as 0.
15 Double-click the Constant block connected to the AddSub block.
16 Select Signed, specify the constant value as (100e3/1e6)*2^23, specify the number of bits as 23,
and the binary point as 0.
The carrier frequency is configured through the Constant block connected to the AddSub
block. The value sent to the data input port is called phase increment. We want a 100 kHz carrier
frequency from a DDS with a 1 MHz clock. The relation is simple:
fout P
= inc_data_port
DDSclock Pinc_max
For details on phase incrementation and DDS, refers to System Generator for DSP Help.
17 Double-click the CMult block, specify (1.5e3/1e6)*2^(23–15) as the Value, specify the number of
bits as 16, and the binary point as 16.
The last value configures the peak frequency deviation. It is related to the frequency
modulation index. Frequency modulation (FM) conveys information by varying the frequency of
a carrier signal. The frequency modulation index indicates by how much the modulated variable
varies around its unmodulated level. The formula for the modulation index is:
20
D
b= f
fm
Where fm is the highest modulating frequency and Δf is the carrier frequency deviation. For
narrow-band FM, such as FRS, the modulation indices must be smaller than 1. Let us use 0.5.
The highest modulating frequency coming from the sine wave is 3 kHz; therefore, we need a
carrier frequency deviation of 1.5 kHz. The phase increment corresponding to 1.5 kHz is equal
to (1.5×103/1×106)×223. The peak value of our 16-bit sine wave is 215–1. We are looking for the
constant value K where:
(215 - 1) K = c 1.5 # 610 m # 2 23

3
10
Configuring the simulation parameters

1 On the model’s Simulation menu, click Configuration Parameters.
Alternately, you can press CTRL+E on your keyboard.
2 In the Simulation time group, specify 1 in the Stop time text box.
3 In Solver options section, select Variable-step as the type and discrete as the solver.
4 Click OK.
Saving the model

◊ Save the model file as my_tutorial3.mdl.
Running the model

◊ Click the play button.
System Generator for DSP produces simulation results that are bit-true and cycle-true to
the hardware it generates. To say that a simulation is bit-true means that, at the boundaries (e.g.
interfaces between the System Generator block and non-System Generator for DSP blocks), a
value produced in a simulation is identical, bit for bit, to the corresponding value produced in the
hardware.
To say that a simulation is cycle-true means that, at the boundaries, corresponding values are
produced at corresponding times. The boundaries of the design are the points where System
Generator for DSP blocks exist. When the System Generator for DSP generates hardware, the
Gateway In or Gateway Out blocks become top-level input or output ports.

On the spectrum scope, you can see a typical FM spectrum around the carrier frequency of
100 kHz. On the time scope, you can see that both DDS output signals are in quadrature with each
other.
21
Figure 14 Spectrum scope view of FM with a 0.5 spectrum index and Time scope quadrature signal
Stopping and disconnecting

1 Click the stop simulation button.
2 Close the model.
22
Using the platform’s mixed processor architecture
Using the platform’s mixed

processor architecture
In this chapter, you will use the VPSS in transferring data from a DSP to an FPGA. To do so, you will use
the platform’s codec’s synchronization mechanism and the custom registers.
Tutorial 4—Using VPSS for streaming

application in the FPGA model
Goals
• Demonstrate how to achieve codec synchronization
• Demonstrate how to use the VPSS in a DSP model
• Demonstrate how to use custom registers to receive DSP control signals

1 Start MATLAB.
that appears.
5 On the Callbacks tab, in the Model pre-load function group, type Fs_FPGA = 37.5e6.
The Fs_FPGA variable’s value is 37.5e6, which becomes the system clock’s frequency.
6 Insert the following blocks in the model.
Simulink—Sinks
• 1 × Scope
• 4 × Terminator
• 1 × Sine Wave
Lyrtech SFF SDR DP Blockset—FPGA—Onboard
• 1 × FPGA Configuration
• 1 × Custom Register
• 2 × VPSS
Xilinx Blockset—Basic Elements
• 1 × System Generator
• 3 × Const
• 1 × Mux
23
Figure 15 Connecting the blocks in the model

Sine Wave block
• Amplitude: 2^15–1
• Frequency: 3000
• Sample time: 1024/Fs_FPGA
FPGA configuration block
• Clock Source: 37.5 MHz
• Select the Synchronize Audio Codec with FPGA System Clock check box
• Clock divider: 4
Custom register block
• Register ID: 0
• Direction: Read
• Output Arithmetic Type: Unsigned
• Output Width: 1
• Binary Point: 0
VPSS block
• Direction: one RX (the one with the Sine Wave block) and one TX (the one with the scope)
• Output Arithmetic Type: Signed
• Output width: 32
• Binary Point: 0
System Generator block
• Simulink system period: 1/Fs_FPGA
Const block for the ren and wen inputs of the VPSS (2) block
• Clear the Sampled constant check box
• Type: bool
• Value: 1
Const block for input d1 of Mux block
• Type: Signed
• Value: 0
• Sample Time: 1024/Fs_FPGA
24
• For data streaming applications, configure your ren and wen as always asserted.
• Because the Synchronize Audio Codec with FPGA System Clock check box is selected in the
FPGA configuration block, the FPGA system clock and the codec clock are the same.
Saving the model

◊ Save the model as my_tutorial4.mdl.
Building an FPGA model

Before you can build an FPGA model, you must provide to the MBDK FPGA solution and
System Generator for DSP the necessary information to build the model. Proceed as follows to do so.
1 Configure the FPGA configuration block.

a On the Clock Type list, select Real-Time Hardware Implementation.
b On the Clock Source list, select the hardware clock used by the System Generator for DSP
design.
2 Configure the System Generator block to build the FPGA model.
a On the Compilation list, point to Hardware Co-Simulation, then Lyrtech, and then click
SFF SDR DP.
b In the Target directory text box, specify the folder where the generated FPGA code must
be created. This folder also contains the bitstream corresponding to your model, when the
building process is complete. The name of the bitstream is name_of_FPGA_model_evm.bit,
where name_of_FPGA_model corresponds to the name of your FPGA model.
c On the Synthesis tool list, select XST.
d On the Hardware description language list, select VHDL.
e In the FPGA clock period and Simulink system period text boxes, specify 1e9/37.5e6 or less.
3 To build the bitstream, click Generate.
The code generation process starts for each block of the FPGA model (except for Simulink I/O
blocks, only present for simulation purposes). When the code generation is complete, the
System Generator block opens a Perl session and uses ISE Foundation tools to create a bitstream
from the model’s generated code. When the process is complete, a message appears to inform you
of the fact.

This bitstream will be use with the .out of the following DSP model. Proceed to the next section.
25
Tutorial 5—Using the VPSS to stream data

in a DSP model
Goals
• Demonstrate how to use the VPSS in a DSP model
• Demonstrate how to use the Custom Register for DSP control signal
• Demonstrate how to achieve codec synchronization in a DSP model
• Demonstrate how to load a bitstream from the DSP model

1 Open the my_tutorial2.mdl file.
2 Remove the Digital Filter Design block and Switch block from the model.
3 Insert the following blocks in the model:
• Manual Switch (×1)
• Custom Register (×1)
• VPSS (×2)
Lyrtech SFF SDR DP Blockset—DSP—Miscellaneous tools
• Set bitstream (×1)
• Lyrtech priority manager (×1)
26
Custom Register block
• Register ID: 0
• Direction: Write to FPGA
• FPGA Data Type: Unsigned
• FPGA Binary Point: 0
• DSP Data Type: Int32
• Sample period: 128/Fs_DSP
Audio Codec Configuration block
• Sampling frequency: Defined with FPGA configuration block
VPBE block
• Packet size: 128
VPFE block
• Packet size: 128
• Output data type mode: int32
that appears.
7 On the Callbacks tab, in the Model pre-load function group, type Fs_DSP = 36621.
This maintains the scope accurate as this is the new sampling frequency of the codec
(37.5 MHz/1024 = 36621 Hz).
8 On the model’s Format menu, point to Block Displays, and select Sorted.
9 Update your model and make sure that VPBE is smaller than VPFE.
If it is not, open the Lyrtech priority manager block.
Figure 17 Lyrtech priority manager
Select the name the VPFE block (by default, VPSS Bus or VPSS Bus 1), and then click Down until the
block is below the VPBE block.
27
Figure 18 Lyrtech priority manager
The sorted order of blocks shows the sequence in which each part of the processing is
called. In the case of the VPBE and VPFE, it is useful because if the VPFE is performed before the
VPBE, the VPSS port becomes deadlocked.
10 Double-click Set Bitstream, and then select the bitstream created during tutorial 4.
Running the model on the platform

To take your simulation model and implement it on the SFF SDR development platform, proceed as
follows:
Building the model

◊ On the model’s Tools menu, point to Real-Time Workshop, and then click Build Model.
Before building the model, verify that the value of Fs_DSP is 36621. If it is not, save the
model as my_tutorial5.mdl, close the model, and then reopen it. Alternately, you can type Fs_DSP =
36621 at the MATLAB command prompt.
Connecting to the target and running the model

1 Make sure that the SFF SDR development platform is on and that and Ethernet cable is connected
to its Ethernet port.
Alternately, you can click the toolbar’s connect to target button.

Toggle the manual switch of the DSP model. Normally hearing audio in both switch positions indicates
that the VPSS is functioning properly. Press the S5 button of the digital processing module. This mutes
the audio signal when the manual switch is positioned for the VPFE.
28
Stopping, stopping, and disconnecting
1 Click the disconnect from target button.
3 Close the model.
29
30
Using the data conversion and RF modules
Using the data conversion and

RF modules
This chapter will help you learn how to include all three modules of your platform into your designs.
Tutorial 6—Using the DAC in an

FPGA model
Goals
• Demonstrate how to use the DAC block
• Demonstrate how to synchronize with the DAC clock

1 Open models my_tutorial3.mdl and my_tutorial4.mdl.
2 Move the DDS v5_0 block and its Constant block, the Add block, the two Gateway Out blocks, the
Spectrum Scope block, and the Scope block from the tutorial 3 model into the tutorial 4 model.
4 Remove the two Gateway Out blocks from the model.

31
Lyrtech SFF SDR DP Blockset—FPGA—Onboard
• 1 × Custom Register (×1)
Lyrtech SFF SDR DP Blockset—FPGA—Add-on hardware modules
• 2 × ADACMaster III
• 1 × RF module configuration
• 1 × RF module
6 Duplicate the Mux and Zero constant twice.

DSP Constant block
• Value: ceil((462.5625e6-432e6)/80e6*2^29)
• Register ID: 1
• Direction: Read
• Output Arithmetic Type: Unsigned
• Output Width: 29
• Binary Point: 0
ADACMaster III output (DAC) blocks
• Channel ID: One A and one B
• Binary point: 15
• Mode: DAC
Xilinx Blockset—Basic Elements
• 1 × Convert
• 2 × Upsampler
• 1 × Inverter
32
Simulink—Sinks
• 2 × Terminator
11 Configure the block as follows:

Upsampler block
• Sampling Rate: 2560
• Select the Copy samples check box
Convert block
• Type: Bool
that appears.
13 On the Callbacks tab, in the Model pre-load function group, type Fs_FPGA = 80e6.
The Fs_FPGA variable’s value is 80e6, which becomes the frequency of the system clock.
14 Double-click the DDS v5_0 block.
15 On the Basic tab, select the Negate sine check box.
16 On the Advanced tab, modify DDS clock rate to 80.
17 Double-click the AddSub block.
18 On the Output Type tab, modify the Number of bits to 29.
19 Double-click the FPGA configuration block.
20 On the FPGA system clock list, select Clock source LYRIO+ Sync Bus 1 clock.
21 Select the Synchronize audio codec with FPGA system clock check box.
22 Specify the clock source value as 80 MHz and the clock divider value as 10.
This creates a codec clock running at 31.25 kHz. For details about valid clock divider values, refer to
the FPGA configuration block’s Help.
23 Double-click the DSP Constant blocks, and then configure all the sample time values to
2560/Fs_FPGA.
24 Double-click the VPSS blocks, and then configure all the sample time values to 2560/Fs_FPGA.
25 Double-click the Sine Wave block, and then configure its sample time value to 2560/Fs_FPGA.
26 Double-click the Custom Register blocks, and then configure all the sample time values to 2560/
Fs_FPGA.
33
• The negative sine is necessary to get an upper sideband signal from the analog quadrature
modulator of the RF module. This can be ascertained with a spectrum analyzer.
• The number of bits of the DDS data import port is explained in tutorial 3.
• The mult is discarded from tutorial 3 because K’s value for FRS specifications nears 1.
Building the FPGA model

1 Double-click the System Generator block, and then specify 1e9/80e6 as the FPGA clock period.
2 Save your model as my_tutorial6.mdl.
3 In the System Generator dialog box, click Generate.
Before building the FPGA model, verify that the value of Fs_FPGA is 80000000. If it is
not, close the model, and then reopen it. Alternately, you can type Fs_FPGA = 80e6 at the MATLAB
command prompt.

The bitstream generated with the System Generator block is used with the .out file of the following
tutorial. Proceed to tutorial 7.
Saving the model

◊ Save the model as my_tutorial6.mdl.
Tutorial 7—Using the data conversion and

RF modules in a DSP model
Goals
• Demonstrate how to configure the RF module to perform an FRS transmission.
• Demonstrate how to achieve codec synchronization in a DSP model.

1 Open the my_tutorial5.mdl file (or the tutorial5.mdl file if you did not complete tutorial 5).
• 1 × Custom Register
Lyrtech SFF SDR DP Blockset—DSP—Add-on hardware modules
• 1 × RF module
• 1 × ADACMaster III control
34
that appears.
4 On the Callbacks tab, in the Model pre-load function group, type Fs_DSP = 31250.
This maintains the scope accurate because this is the new sampling frequency of the codec
(80 MHz/2560 = 31250 Hz).
5 Open the my_tutorial2.mdl file (or the tutorial2.mdl file if you did not complete tutorial 2).
6 Drag the Digital filter design tool block from the my_tutorial2.mdl to the my_tutorial5.mdl (or from
tutorial2.mdl to tutorial5.mdl, according to your situation).
7 Double-click the Digital filter design tool block, and then modify the Fs value for 31250.

• Register ID: 1
• Direction: Write to FPGA
• FPGA Data Type: Unsigned
• FPGA Binary Point: 0
• DSP Data Type: Int32
RF module block
• Select the TX check box
• TX base frequency: 432 MHz
• Reference Clock Source: Onboard 10 MHz
VPBE and VPFE blocks
• Data Type: Int32
Audio Codec I/O In block
• Clear the Normalize Audio Data Samples check box
35
Audio Codec I/O Out block
• Clear the Normalize Audio Data Samples check box
• Clear the Enable Data Saturation check box
ADACMaster III control block
• On the DAC tab, select the Enable DAC check box.
• On the DAC tab, on the Operation Mode list, select Full Bypass.
• On the Clock and PLL tab, ADC/DAC Clock Source: Use PLL
• On the Clock and PLL tab, PLL Reference Time Base: External
• On the Clock and PLL tab, Additional Reference Time Value: 10
• On the Clock and PLL tab, Required clock for ADC, FPGA design, and DAC: 80
• On the Advanced tab, Sample time: 128/Fs_DSP
DSP Constant block
• Value: ceil((462.5625e6 -432e6) /80e6*2^29)
• Data Type: int32
• The equation used in calculating the DSP constant is the same as the one presented in tutorial 3
for setting the carrier frequency. The carrier frequency of FRS channel 1 is 462.5625 MHz, which
is obtained from intermediate frequency (IF) 30.5625 MHz (controlled by the DSP constant) and
heterodyned with a frequency of 432 MHz.
• Because the DAC and ADC are AC coupled, you must always work at an IF higher than 3 MHz.
10 Right-click the RF Module block and select Block properties. Enter the value 0 in the Priority field.
Because the conversion module gets its clock signal form the RF module, the latter must
be initialize first.
11 Double-click the Set Bitstream block, and then select the bitstream created in tutorial 6.
Building the model

2 On the model’s Tools menu, point to Real-Time Workshop, and then click Build Model.
Before building the model, verify that the value of Fs_DSP is 31250. If it is not, close the
model, and then reopen it. Alternately, you can type Fs_DSP = 31250 at the MATLAB command
prompt.
Connecting to the target and running the model

1 Make sure that the SFF SDR development platform is on and that an Ethernet cable is plugged to its
Ethernet port.
36
Alternately, you can click the connect to target button.

Turn on the FRS handset supplied with the platform, tune into channel 1, and then make sure that
there is no privacy code. If this is the case, you see 00 next to the channel number. When you press
button S5 on the digital processing module, the audio signal from the line out connector stops and
is output by the FRS handset.
Stopping and disconnecting

1 Click the disconnect from target button.
2 Close the model.
37

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SFF SDR development

Version 3.1—May 2010

1.0 2008-05-01 First edition.

1.1 2008-06-01 Corrections of erroneous information and instructions.

The TM and ® marks have been omitted from the text.

Purpose and structure

Table 1 Glossary of terms

Computer communication development Refers to developing custom communications applications to

cPCI Short for CompactPCI, refers to a 3U or 6U Eurocard-based

cPCI chassis system Refers to the chassis-CPU board-case system.

Example Refers to examples used to demonstrate functions or applications

Eurocard Refers to a European standard format for printed-circuit boards

HDL Stands for hardware description language.

Host A host is defined as the device that configures and controls a

Reception Any data received by the referent is a reception. Abbreviated RX.

Reference design Blueprint of an FPGA system implanted on Lyrtech boards. It is

Transmission Any data transmitted by the referent is a transmission.

VHDL Stands for VHSIC hardware description language.

VHSIC Stands for very-high-speed integrated circuit.

You should be familiar with MATLAB and Simulink before proceeding.

DSP development software

FPGA development software

• SFF SDR development platform user’s guide

Using the platform’s DSP

Targeting the DSP

1 Create a new model or modify an existing model.

Tutorial 1—Audio loopback simulation

Creating a new model

Frame time = Sample Time × Frame Size

By default, the Sample Time is 1.

7 Insert the following blocks in the new model:

Figure 1 MBDK DSP default configuration dialog box

9 Connect the blocks as illustrated.

10 Configure the blocks as follows

14 Press CTRL+D on your keyboard.

Figure 3 Updated model

Simulating the model

Figure 4 Time domain and frequency domain simulation results

Configuring the Real-Time Workshop target

2 Select Real-Time Workshop.

Figure 5 Real-Time Workshop configuration parameters

Configuring model Solver parameters

Configuring the hardware implementation model

2 Select Hardware Implementation.

3 Make sure that the Device type is TI C6000.

Building the model

◊ On the toolbar of the model window, click the build button.◊

Running the model

1 On the Tools menu, click External mode Control Panel.

2 Click Signal & Triggering.

You must not be connected to the platform to modify this parameter.

Figure 10 External Signal & Triggering

Saving, stopping, and disconnecting

Tutorial 2—Processing an audio signal

Modifying an existing model

4 Configure the blocks as follows:

6 In the Response Type group, select Lowpass.

Running the model on your platform

Building the model

Running the model

3 Connect an audio source such as an MP3 player to the line in connector.

6 Click the play button.