MOSFET Current Source Equivalent Circuit

■ Small-signal model: source resistance is ro2 by inspection

gm1vgs1 ro1 vgs2 = 0 V gm2vgs2 ro2

■ Combine output resistance with DC output current for approximate equivalent

circuit ... actual iOUT vs. vOUT characteristics are those of M2 with VGS2 = VREF

iOUT
iOUT
+

(W/L)2 (W/L)2
IREF ro2 vOUT IREF
(W/L)1 1/ro2
(W/L)1

VDS vOUT
SAT2
−

(a) (b)

EE 105 Spring 1997

Lecture 27
 The Cascode Current Source

■ In order to boost the source resistance, we can study our single-stage building
blocks and recognize that a common-gate is attractive, due to it high output
resistance

VDD
iOUT
IREF

M3 M4

M1 M2

■ Adapting the output resistance for a common gate ampliÞer, the cascode current
source has a source resistance of

R S = ( 1 + g m4 r o2 )r o4 ≈ g m4 r o4 r o2
■ Penalty for cascode:
needs larger VOUT to function

EE 105 Spring 1997

Lecture 27
 MOSFET Current Sources and Sinks

■ n-channel current source sinks current to ground ... how do we source current
from the positive supply? Answer: p-channel current sources...?

VDD

M1 M2
MR M3

iOUT1 iOUT2 iOUT3

IREF

■ By mixing n-channel and p-channel diode-connected devices, we can produce

current sinks and sources from a reference current connected to VDD or ground.

VDD

M1
MR M2
iOUT1 iOUT2

iOUT4
IREF
M3 M4

EE 105 Spring 1997

Lecture 27
 Two-Stage BiCMOS Transconductance AmpliÞer

■ Concept: cascade two common-emitter stages to get more transconductance --

not an ideal solution but illustrates DC biasing and interstage coupling

iout
RS

+v +
+ in1
vs Rin1 Rout1 Rin2 vin2 Rout2 RL
_ _ Gm1vin1 _ Gm2vin2

CE (npn) CE (pnp)

■ DC Issues:
First stage: npn common-emitter ampliÞer (DC level shifts up)
Second stage: pnp common-emitter ampliÞer (DC level shifts down)

EE 105 Spring 1997

Lecture 27
 AmpliÞer Topology

■ Basic structure -- connect output of CE (npn) to input of CE (pnp),

attach small-signal voltage input (with RS) and load (RL)

V+ = + 2.5 V

iSUP1

Q2
iout
RS
+ Q1
vs RL
_
+
iSUP2
V
_ BIAS

V - = - 2.5 V

■ Current source design:

assume that the reference current is generated by a resistor (to ground)

EE 105 Spring 1997

Lecture 27
 DC Currents from Reference

■ p-channel diode-connected M3 is used to generate source-gate voltages for M4

(which generates iSUP1) and for M5. The second current supply is generated by
Þrst using -ID5 to generate a DC gate-source voltage via diode-connected M7.

V+ = + 2.5 V
M4
M3 M5

iSUP1 - ID5

IREF
RREF

iSUP2
ID7
M6 M7
V - = - 2.5 V

EE 105 Spring 1997

Lecture 27
 Two-Stage BiCMOS Transconductance AmpliÞer

■ Combine current source circuit with basic ampliÞer topology

V+ = + 2.5 V
M4
M3 M5

Q2
RREF iout
RS
+ Q1
vs
_ RL
+
V
_ BIAS M6 M7
V -= - 2.5 V

EE 105 Spring 1997

Lecture 27
 DC Bias of Transconductance AmpliÞer

■ Given: VOUT = 0 V (DC); V+ = 2.5 V, V - = -2.5 V; RS = RL = 50 kΩ

■ Standard simpliÞcations: assume IB = 0 for bipolar transistors, neglect Early
effect (BJT) and channel-length modulation (MOSFETs) for hand calculations

V+ = + 2.5 V
M4
M3 M5

Q2
RREF iout
RS
+ Q1
vs
_ RL
+
V
_ BIAS M6 M7
V -= - 2.5 V

■ Device Properties: (for simplicity, make all n-channel and all p-channel
MOSFETs the same dimensions)
MOSFETs: µn Cox = 50 µAV-2, (W/L)n = (50/2), VTn = 1 V, λn = 0.05 V-1
µp Cox = 25 µAV-2, (W/L)p = (80/2), VTp = - 1 V, λp = 0.05 V-1
BJTs: βon = 100, VAn = 50 V, βop = 50, VAp = 25 V

EE 105 Spring 1997

Lecture 27
 Reference Resistor

■ Find RREF such that IREF = 50 µA and then find all node voltages and DC bias
currents ...

+2.5 V
+ V_SG3
M3 V SG3 = V DD Ð I REF R REF Ð V SS
- ID3
Ð I D3
0 V SG3 = Ð V Tp + ---------------------------------------------
IREF ( W ⁄ ( 2L ) ) p µ p C ox
RREF

- 2.5 V

■ Substituting IREF = - ID3 = 50 µA, the source-gate voltage drop is

50 µA
V SG3 = Ð ( Ð 1 V ) + ---------------------------------------------------- = 1.22 V
 ---------------
80 
- ( 50 µA/V )
2
 ( 2 ( 2 ) )

■ Solve for the reference resistor:

( V DD Ð V SS ) Ð V SG3 2.5 V Ð ( Ð 2. 5 V ) Ð 1.22 V

R REF = ---------------------------------------------------- = ----------------------------------------------------------------- = 75.6 kΩ
I REF 50 µA

EE 105 Spring 1997

Lecture 27
 DC Operating Point

■ Since width-to-length ratios are identical for n-channel and p-channel devices
(separately), the DC supply currents are equal to the reference current

V+ = + 2.5 V

ISUP1 =
50 µA

Q2
iout
RS
+ Q1
vs RL
_
+ ISUP2 =
V
_ BIAS 50 µA

V - = - 2.5 V

■ Neglecting base currents, IC1 = 50 µΑ and IC2 = 50 µΑ

Q1: gm1 = 2 mS, rπ1 = 50 kΩ, ro1 = 1ΜΩ
Q2: gm2 = 2 mS, rπ2 = 25 kΩ, ro2 = 500 kΩ
Source resistances of the current supplies for Þrst and second stages:
roc1 = ro4 = (λ4(-ID4))-1 = (0.05(0.05))-1 = 400 kΩ
roc2 = ro6 = (λ6(ID6))-1 = (0.05(0.05))-1 = 400 kΩ

EE 105 Spring 1997

Lecture 27
 Overall Two-Port Model

■ Rin = Rin1 = 50 kΩ and Rout = Rout2 = ro2 || roc2 = 500 kΩ || 400 kΩ = 220 kΩ
■ Overall short-circuit transconductance Gm -- must apply procedure
iout

+v +
+ in1
vin Rin1 Rout1 Rin2 vin2 Rout2
_ _ Gm1vin1 _ Gm2vin2

CE (npn) CE (pnp)

Find input voltage to the second stage:

vin2 = - Gm1( Rout1 || Rin2 ) vin = - gm1 ( ro1 || roc1 || rπ 2 ) vin

Output current

iout = Gm2 vin2 = gm2 [- gm1 (ro1 || roc1 || rπ2)] vin

■ Overall transconductance:

Gm = iout / vin = - gm2 gm1 (ro1 || roc1 || rπ2)

Gm = - (2 mS)(2 mS)(1 MΩ || 400 kΩ || 25 kΩ) = - (2 mS)(2 mS)(23 kΩ)

Gm = - 92 mS

EE 105 Spring 1997

Lecture 27
 Output Voltage Swing

■ Find the maximum and minimum values of vOUT

V+= 2.5 V
M4
M3 M5

Q2
RREF
Q1 vOUT

+
V
_ BIAS M6 M7
V -= - 2.5 V

■ Determine how high the output node can rise before a device leaves its constant-
current region
Q2 saturates when vOUT = VOUT(max) = 2.4 V ... VEC(sat) = 0.1 V
Note that M4 is still saturated since VSD4 = VEB4 = 0.7 V > vSG4 + VTp = 0.22 V
■ Determine how low the output node can drop ...
M6 goes triode when vOUT = VDS7(sat) = VGS7 - VTn = 1.22 V - 1 V = 0.22 V
VOUT(min) = - 2.5 V + 0.22 V = 2.23 V

EE 105 Spring 1997

Lecture 27