1

# 3 Vaishali, Palace Garden Apts,

23/24 Palace Cross Road,
Bangalore, India. PIN – 560020
e-mail: abhishekkamath@yahoo.com
Abhishek Prasad Kamath
www.geocities.com/abhishekkamath

OBJECTIVE To pursue graduate studies and research in analog and mixed

signal IC design and its applications in allied fields like RF and
SoC.

RESEARCH INTEREST Analog and mixed signal IC design, Data converters, PLLs and
analog signal processing.

AGE / SEX / NATIONALITY 21 years/ Male / Indian

EDUCATION Birla Institute of Technology and Science(BITS), Pilani,

India.
B.E.(Hons) Electrical and Electronics, June 2005.
Major GPA: 9.72/10 or 3.86/4.
Overall GPA : 9.57/10 or 3.79/4.

National Public School (NPS), Bangalore, India

A.I.S.S.C.E (std XII), June 2001
GPA(percentage) – 96.2% nationwide (equivalent) – 5th rank

St. Joseph’s Boys’ High School, Bangalore, India

I.S.C.E (std X), June 1999
GPA(percentage) – 92.5%

TEST SCORES GRE : Verbal–670/800, Quantitative–790/800. Essay–5.5/6.

TOEFL – 300/300. TWE: 6/6.
TSE – 50/60

PROFESSIONAL U&I System Design Ltd. India

EXPERIENCE Summer Intern May 2003 – June 2003
Implemented AES standards block ciphers– RC6 and MARS.

Indian Institute of Science(IISc), Bangalore, India

Summer Intern May 2004 – July 2004
Designed and implemented a novel 5 bit 30MS/s Current Mode
Flash ADC which consumed 50mW of average power, and
implemented it in 0.7um CMOS technology.

ACADEMIC EXPERIENCE Professional and Teaching Assistant

Responsible for developing course material and tutoring
undergraduate students in the course work
- Circuits and Signals, January 2004 – May 2004
- Control Systems, August 2004 – present

abhishekkamath@yahoo.com Abhishek Prasad Kamath www.geocities.com/abhishekkamath

 2

SELECTED PROJECTS - Design and Implementation of a 10bit 80MS/s 60db SFDR

Pipelined ADC (with digital error correction) in 0.25um
CMOS technology
- Design and Implementation of Charge Pump Phase Locked
Loops and development of software to automate the
process.
- Design and Implementation of a 5 bit 30MS/s 50mW
Current Mode Flash ADC in 0.7um CMOS technology.
- Design and Implementation of Switched capacitor circuits
(integrators, low pass filters) in 1um CMOS technology.

TERM PROJECTS - Design and Implementation of two stage Op-amp.

- Implementation of MD5 hash algorithm in Verilog HDL
- Design and implementation (in hardware) of 3-D Scanner
for APOGEE 2003.
- Design of Black and White Scanner using Intel 8086
microprocessor.

AWARDS / HONOURS - Recipient of the BITS Pilani Merit Cum Need Scholarship
- Course topper of Analog and Digital VLSI Design at
BITS,Pilani
- Secured the 5th rank in All India Senior Secondary School
exam. (CBSE)
- Secured the 72nd rank (out of two hundred thousand students)
in nationwide Common Entrance Test for admission to
undergraduate studies in engineering
- Awarded the prestigious All India Youth Leadership for
Science by Government of India.
- Nominated the President of Science Association in College
- Was Awarded College Topper Award at NPS.
- Appeared in International (Australian) competitive exams
and secured distinction in Math, Science and English
- Was Awarded Principal’s Gold Medal for Highest marks in
English, Science and Social Studies

CAD TOOLS - Magma, Tanner EDA, FPGA Advantage 5.2 from

Mentor Graphics

COMPUTER SKILLS - Languages – C , C++ , Assembly (Intel 8086, Texas

Instruments C54x 6x), Verilog HDL.
- Packages – MATLAB;
- Operating system – Unix/Linux

UNDERGRADUATE - Electrical Science-I, Electrical Science-II, Circuits and

COUSREWORK Systems, Microelectronic Circuits, Digital Electronics and
Computer Organization, Electronic Devices and Integrated
Circuits, Analog Electronics, Analog and Digital VLSI
Design, Introduction to MEMS, Communication Systems,
Digital Signal Processing, Data Communication and
Networks, Analog IC Design(informal attendance).

abhishekkamath@yahoo.com Abhishek Prasad Kamath www.geocities.com/abhishekkamath

 3

EXTRA CURRICULAR - Member of EEE Association at BITS which is responsible for

ACTIVITIES organizing exhibits for APOGEE (a BITS inter university
academic festival) and in helping out undergraduate students
academically.
- Secretary of ENGLISH DRAMA CLUB at BITS
(2003-2004)
- Member of Department of Controlz which is responsible for
organizing nationwide inter university cultural
festival/competition.

REFERENCES Dr. Subash Chandra Bose

Scientist
IC Design Group
Central Electronic Engineering Research Institute, Pilani
email: subash@ceeri.ernet.in

Dr. S. Gurunarayanan
Assistant Dean
Engineering Service Division
BITS, Pilani
email: sguru@bits-pilani.ac.in

Dr. H S Jamadagni
Chairman
Centre for Electronic Design and Technology
Indian Institute of Science, Bangalore
email: chairman@cedt.iisc.ernet.in
(or) hsjam@cedt.iisc.ernet.in

Dr. Anu Gupta

Assistant Professor
Department of Electrical and Electronic Engineering
BITS, Pilani.
email: anug@bits-pilani.ac.in

abhishekkamath@yahoo.com Abhishek Prasad Kamath www.geocities.com/abhishekkamath

 4

Summary of Projects done/currently doing

1. Design and Implementation of switched Capacitor Circuits

(under Dr. Gurunarayanan, Asst. Dean, ESD, BITS, Pilani)

The Project aimed at exploring and understanding an effective technique used to overcome present
technology limitation to fabricate accurate sized resistors for analog circuits. Different switched
capacitor circuits – stray sensitive, insensitive integrators, low pass filters were implemented. For the
circuits a two stage opamp was designed to meet gain (A=8000),slew rate (SR= 7V/ s) and
bandwidth (BW= 2Mhz).

2. Design and Implementation of 5 bit 30MS/s CURRENT MODE FLASH ADC

(under Prof Jamadagni, Chairman CEDT, IISc Bangalore)

The project explored the interesting possibility of using current mode approach in FLASH ADC to
improve speed, because it was reasoned that since current signals do not suffer RC delays, their
operation would be faster than VOLTAGE MODE. Previous work in this field had used sense
amplifiers (complex using lots of area) and large power consumption. Various current comparators
such as Traff’s and Tang’s were implemented and used. However a modified comparator based on a
recent publication (Kluwer, 2001) with a latching mechanism was designed. An efficient method
was designed to convert thermometer code to digital output word. The ADC was optimized to
consume only 50mW of power. The speed of the ADC was limited due to skewing of current pulses
in MOS current mirror.

3. Design and Implementation of 10bit, 80MS/s , 60dB SFDR Pipelined ADC

(under Dr. Anu Gupta, Assistant Professor, BITS, Pilani)

The project aims at developing a fully function pipelined ADC of the above specification as a part of
a live project ( SoC) sponsored by Broadcom Inc. A 1.5 bit/stage architecture with digital error
correction was chosen. Behavioral modeling of ADC was carried out using Matlab, in order to get
tolerance limits and check for functionality. As a member of the team I am working on
implementing the cascode opamp with gain boosting and associated switched capacitor circuitry of
S&H and DAC. The opamp design is extremely critical. The opamp has the following specifications:
settling time: 5.5ns, gain: 92dB, unity gain bandwidth: 1.2Ghz. The gain boosting amplifiers were
implemented as single ended telescopic cascode with a gain of 60dB.

4. CAD for PLL,

(under Dr. Subash Chandra Bose, Scientist, IC Design Group, CEERI Pilani)

The Project aims at automating PLL design. A charge pump PLL has already been implemented.
Different ways of implementing the VCO are being explored. Currently I have implemented three
ring oscillator architectures using – inverters, differential amplifiers, and differential amplifiers with
negative resistance. The purpose is to find out which VCO is suitable for which application.(in terms
of range, speed etc). The Oscillators are working in the Megahertz range. The ultimate goal is to link
the transfer function to the circuit parameters(W/Ls). The transfer function will in turn be linked to
broad specifications like lock range, capture range etc. Thus the end result is expected to be software
that will take such broad specifications from the user, select an appropriate architecture and generate
the netlist.

abhishekkamath@yahoo.com Abhishek Prasad Kamath www.geocities.com/abhishekkamath