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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010
A Non-Inverting Buck-Boost DC-DC Switching
Converter with High Efficiency and Wide
Bandwidth
Carlos Restrepo∗ , Student Member, IEEE, Javier Calvente, Member, IEEE, Angel Cid-Pastor, Member, IEEE,
Abdelali El Aroudi, Member, IEEE, and Roberto Giral, Senior Member, IEEE
Abstract—A novel DC-DC switching converter consisting of
a boost stage cascaded with a buck converter with their coils
magnetically coupled is presented. The disclosed converter has
the same step-up or step down voltage conversion properties
than the single inductor non-inverting buck-boost converter but
exhibits non-pulsating input and output currents. The converter
control-to-output transfer function is continuous between oper-
ation modes if a particular magnetic coupling is selected. The
addition of a damping network improves the dynamics and
results in a control-to-output transfer function that has, even
in boost mode, two dominant complex poles without right half
plane zeroes. An example shows that an output voltage controller
can be designed with the same well-known techniques usually
applied to the second-order buck regulator. Details of a prototype
and experimental results including efficiency, frequency and
time domain responses are presented. The experimental results
validate the theoretical expected advantages of the converter,
namely, good efficiency, wide bandwidth and simplicity of control
design.
Index Terms—Non-inverting buck-boost converter, coupled
inductors, right-half-plane (RHP) zero, high efficiency, wide-
bandwidth, high-side driver.
I. I NTRODUCTION
I N many converter applications such as battery charging and
discharging, power factor correction, fuel cell regulation,
maximum power point tracking of solar panels, a DC-DC
converter is used to obtain a regulated voltage from an
unregulated source. When the regulated voltage is within the
voltage range of the unregulated voltage source, a step-up/step-
down DC-DC converter is required [1]–[13].
Step-up/step-down DC-DC converters with a single active
switch, such as buck-boost, flyback, SEPIC and Ćuk topolo-
gies, have high component stresses and low efficiencies in the
same operating point than the boost or the buck converter if
the output voltage is greater or smaller than the input voltage
respectively [14].
It is possible to combine a buck with a boost to obtain a two
independently controllable switch buck-boost converter with
This work was supported by the Spanish Ministerio de Ciencia e Inovación
under the projects ESP2006-12855-C03-02, CSD2009-00046, TEC2009-
13172, DPI2010-16481 and the FPU scholarship AP2008-03305.
C. Restrepo, J. Calvente, A. Cid-Pastor, A. El Aroudi and R. Giral are
with the Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, Escola
Tècnica Superior d’Enginyeria, Universitat Rovira i Virgili, 43007 Tarragona,
Spain.
∗ Corresponding author. Email: carlos.restrepo@urv.cat. Postal Address:
Avda. Paı̈sos Catalans 26, Campus Sescelades, 43007, Tarragona, Spain. Fax:
(+34)977559605. Telephone number: (+34)977297052.
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1
size and performance comparable to those of the simple buck
or boost stages [15]. For example, combining a buck in cascade
with a boost results in a single inductor non-inverting buck-
boost converter that exhibits high performance and it is widely
used in low voltage applications [4]–[8]. These converters do
not operate in buck-boost mode because it is more efficient
to operate them either in buck mode if the output voltage is
lower than the input one or in boost mode in the opposite
case [2]. There are also high efficiency non-inverting buck-
boost converters at higher operational voltages [12], [13] with
the drawback of a complex control. In [12], the authors state
that the detailed modelling of the plant and the controller
is an ongoing work. In [13], two different output voltage
regulators are required depending on either boost or buck mode
of operation.
The single inductor non-inverting buck-boost converter is
used in applications where it is important to have low size and
cost of the magnetic elements. However, when the voltages
are high, the size of the capacitors of this converter is also
important. In that case, it can be interesting to use the cascade
buck-boost power converter that has two inductors, one at the
input and another at the output [1], [3]. With these inductors,
the input and output currents are non-pulsating, the noise level
is lower and the control and the limiting of the currents can
be easier than in the pulsating case.
Most of the converters mentioned above, when operating
in continuous conduction boost mode, have a right-half-plane
(RHP) zero that makes the controller design a difficult task,
limits the bandwidth of the loop and penalizes the size
of the output capacitor [6]. One possible solution to these
problems is a topology named KY buck-boost converter [16].
This converter has a very fast transient response, which is
achieved by using switched capacitors for energy transfer, and
is advisable for low power applications. The tri-state boost
converter reported in [17] eliminates the RHP zero but exhibits
a poor efficiency, this technique having never been applied
to the buck-boost topology. In [11] a two inductor boost
superimposed with a buck converter solves satisfactorily the
RHP zero problem but both active switches of the structure
are floating, what requires complex drivers. Another solution
to the problem of the RHP zeros adopted in the work here
reported is using magnetic coupling between inductors [18]
combined with damping networks [19], [20]. This solution has
allowed the design of high-power boost converters with high
efficiency and wide bandwidth [21]–[23].
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 2

1:n 1:n

ig Lm L iL ig Lm L iL
iLm Ds1 + Q2 + iLm Ds1 + +
vg +
Q1 vC Ds2 Co vo Ro vg +
Q1 vC Co vo Ro
− C − C
− − − −

(a)
Fig. 1. Schematic circuit diagram of the buck-boost converter with magnetic
coupling between inductors. 1:n

ig Lm L iL
iLm + Q2 +
The purpose of this paper is to analyze the cascaded con-
nection of a boost and buck converter, with magnetic coupling vg +
vC Ds2 Co vo Ro
− C
between inductors, shown in Fig. 1. This converter can operate
− −
in boost mode, as in Fig. 2(a), and buck mode, as in Fig. 2(b).
Both topologies have non-minimum phase transfer functions
(b)
under certain parametric conditions and have been previously
proposed for battery charge/discharge regulators for satellites Fig. 2. Operating modes of the buck-boost converter: (a) boost mode; (b)
[24]. As it will be seen, the proposed converter exhibits high buck mode.
efficiency in the desired range of operation in spite of using
diodes instead of synchronous rectification. It also presents a
wide bandwidth and low current ripples that reduce the size
of the input capacitor and especially that of the output one. be observed from Fig. 3, a common characteristic of the two
Finally, the converter control is simple in comparison with the operation modes is that currents ig and iL are non-pulsating
state-of-the-art, what could reduce design costs. with triangular-shaped ripple.
The remainder part of this paper is organized as follows: Assuming a continuous conduction mode (CCM) of oper-
Section II presents the key waveforms of the converter and ation, no parasitic effects and a switching frequency much
discusses the small-signal converter model. In the same sec- higher than the converter natural frequencies, the use of
tion, the turns ratio n of the transformer that avoids the need the state space averaging (SSA) method [25] to model the
of using two transfer functions, namely, one for the buck converter leads to the following set of differential equations
mode and another one for the boost mode, is also determined.
This allows to use the same transfer function to describe the
converter in both modes and simplifies the controller design.
A damping network is added in Section III where analytical
diLm (t) vg (t) − v C (t)(1 − d1 (t))
expressions are obtained to design a minimum phase transfer =
function. Section IV focuses on a complete circuit design dt Lm
for the buck-boost converter and its control. Finally, the last diL (t) v C (t)d2 (t) + n(vg (t) − v C (t)(1 − d1 (t)))
=
two sections present respectively simulated and experimental dt L
results, and the conclusions of this work. v o (t)
−
L
II. A NALYSIS OF THE B UCK -B OOST C ONVERTER WITH dv C (t) −iL (t)d2 (t) + (iLm (t) + niL (t))(1 − d1 (t))
=
MAGNETIC COUPLING BETWEEN INDUCTORS dt C
dv o (t) iL (t) v o (t)
Lets us consider the unidirectional buck-boost converter = − (1)
dt Co Ro Co
with magnetic coupling between the input and output inductors
shown in Fig. 1. The current and voltage typical waveforms
of this converter in steady state are depicted in Fig. 3. In
boost mode, the currents are shown in Fig. 3 (a) and the where d1 and d2 are the duty cycles of the switches Q1 and Q2
corresponding voltages in Fig. 3 (b). Fig. 3 (c) and (d) respectively and the overline stands for averaging during one
represent current and voltage waveforms in buck mode. The switching period. A circuital procedure to obtain equations (1)
bottom traces of each plot correspond to u1 and u2 , which are is by means of the replacement of the switches in the converter
respectively the logic activation signals of switches Q1 and by their time averaged models [26], which leads to the large
Q2 . In boost mode u2 = 1 while u1 is switching whereas in signal averaged circuit of Fig. 4(a). Assuming that the con-
buck mode u1 = 0 while u2 switches. The duty cycles of u1 verter is in steady-state with constant duty cycles, d1 (t) = D1
and u2 have been adjusted to obtain a mean output voltage and d2 (t) = D2 , and input voltage vg (t) = Vg , and using the
of 48 V. In a typical design, the ripple in the intermediate principles of inductor volt-second and capacitor charge balance
capacitor voltage vC is bigger than that of the output voltage, [14], the steady-state expressions of the inductor currents and
which permits to use a small intermediate capacitor. As it can capacitor voltages are

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10.3 50

vQ1 [V ]
iQ1 [A]

2.1
0 0
10
6.3

vQ2 [V ]
iQ2 [A]

0
3.7 −10
48.2
6.3
iL [A]

vo [V ]
48
3.7 47.8
10.3

vC [V ]
49.4
i g [A]

44.9
2.1
u1 , u2

u1 , u2
1 1
0 0
0 T 2T 3T 0 T 2T 3T

(a) (b)

1
iQ1 [A]

56.2

vQ1 [V ]
0
−1 54.4

5.9 56.2
iQ2 [A]

vQ2 [V ]
4.1 54.4

0 0
48.2
5.9
iL [A]

vo [V ]

48
4.1
47.8

5.5 55.6
vC [V ]
i g [A]

3.6 53.8
u1 , u2

u1 , u2

1 1
0 0
0 T 2T 3T 0 T 2T 3T

(c) (d)
Fig. 3. Typical waveforms of the Fig 1 converter for Vo = 48 V: (a), (b) currents and voltages in boost mode with Vg = 39 V; (c), (d) currents and voltages
in buck mode with Vg = 55 V. Logic signals u1 (in black) and u2 (in white) indicate switch Q1 and Q2 states respectively.

Our goal is that the converter could operate in both boost

Vg D2 (D2 − n + nD1 ) (0 < D1 < 1 and D2 = 1) or buck (0 < D2 < 1 and D1 = 0)
ILm = modes, and that it could switch from one mode to another in
Ro (1 − D1 )2
Vg D 2 a smooth form. Let us define a single control variable u that
IL = can take the values between 0 and 2 (0 < u < 2). The duty
Ro (1 − D1 )
cycles D1 and D2 are related to the new variable u as
Vg
VC =
1 − D1
Vg D 2 D1 = max(0, u − 1)
Vo = (2)
1 − D1 D2 = min(1, u) (4)
These equations could be also derived from (1) by noting
The new voltage conversion ratio can be expressed as follows
that, in steady-state, the derivatives are zero or, equivalently,
from the DC circuit of Fig 4(b). It is worth noting that the min(1, u)
DC values of the state variables v o , v C and iL do not depend M (u) = (5)
1 − max(0, u − 1)
on the transformer turns ratio n. From the output capacitor
voltage Vo in (2) the voltage conversion ratio M (D1 , D2 ) is With this control input, the DC voltage conversion ratio M (u)
given by is continuous between the boost and buck modes of operation,
as depicted in Fig. 5(a). In the border between the two modes
Vo D2 of operation u = 1, so that D1 = 0 and D2 = 1. Fig. 5(b)
M (D1 , D2 ) ≡ = (3)
Vg 1 − D1 shows how to generate the switch activation signals u1 (t) and

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1:n
plus some superimposed small AC variations db1 (t) and db2 (t)
− + respectively.
ig Lm L iL
iLm v C d1 + iL d2 +
vg +
vC Co v o Ro vg (t) = Vg
− (iLm + niL)d1 C +
v C d2
d1 (t) = D1 + db1 (t)
−
− −

d2 (t) = D2 + db2 (t) (6)

(a)
After these inputs are considered, the averaged inductor
1:n
currents and capacitor voltages can also be expressed in
− + terms of their corresponding steady-state values plus some
Ig + IL +
ILm VC D1 ILD2 superimposed small AC variations.
Vg +
VC + Vo Ro
(ILm + nIL)D1 VC D2
= ILm + biLm (t)
−
− iLm (t)
− − iL (t) = IL + biL (t)
(b) v C (t) = VC + vbC (t)
Fig. 4. Schematic circuit diagrams of the buck-boost converter with magnetic v o (t) = Vo + vbo (t) (7)
coupling between inductors: (a) large-signal averaged model and (b) DC
model. With the assumption that the AC variations are much smaller
than the steady-state values, it is possible to linearize the set of
differential equations (1). The small signal state-space vector
u2 (t) from the control signal u, and a symmetric triangular x
b is defined as
wave of amplitude Vramp = 1 V. £ ¤T
x
b= biLm biL vbC vbo (8)
3 Linearizing (1) around the equilibrium point (2) and sepa-
rating the dynamic AC small-signal terms from the DC steady-
2.5 state component, the following dynamic model is obtained
dbx
2 = Abx + B1 db1 + B2 db2 (9)
dt
where A is the state matrix and B1 and B2 are respectively
M(u)

1.5
the input vectors corresponding to d1 and d2 .
1  D1 −1

0 0 Lm 0
 D2 +n(−1+D1 ) 
0.5  0 0 − L1 
A= 1−D1 n(1−D1 )−D2
L 
 C C 0 0 
1
0 0 Co 0 − Ro1Co
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
u h 2
iT
V nV V D
B1 = − Lm (Dg1 −1) − L(D1 g−1) − CRo (Dg 2
1 −1)
2 0
(a)
h iT
V Vg D2
B2 = 0 − L(D1g−1) CRo (D 1 −1)
0
Hence, in the boundary between the two modes of operation,
the small-signal control-to-output transfer function with re-
spect to the duty cycle db1 is
¯ ¯
¯ vbo (s) ¯¯ N1 (s)
Gvod1 (s)¯¯ ≡ ¯ = (10)
u=1 db1 (s) u=1 D(s)

(b)
where

Fig. 5. (a) DC conversion ratio M (u) of the buck-boost converter.; (b)

activation signal generation: comparison of control signals with a triangular N1 (s) = Vg (Ro nCLm s2 + (Lm n − Lm )s + Ro )
signal to obtain the MOSFETs binary activation signals u1 (t) and u2 (t).
D(s) = Lm CLRo Co s4 + Lm CLs3 + (LmRo Co
− 2Lm nRo Co + Lm CRo + LRo Co
To obtain a small-signal model around a steady-state op-
erating point, we assume that the input voltage is constant + Lm n2 Ro Co )s2 + (Lm − 2Lm n
and the duty cycles d1 (t) and d2 (t) are equal to D1 and D2 + Lm n2 + L)s + Ro

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In the same way, the small-signal control-to-output transfer intermediate capacitor. This damping network can be seen as
function with respect to the duty cycle db2 is a low frequency snubber. The modified procedure to calculate
the parameter values of the passive damping network will be
¯ ¯
¯ vbo (s) ¯¯ N2 (s) given in the next section.
Gvod2 (s)¯¯ ≡ ¯ = (11)
u=1 db2 (s) u=1 D(s)
III. A NALYSIS OF THE COUPLED INDUCTORS
where B UCK -B OOST C ONVERTER WITH DAMPING NETWORK
In this section, the buck-boost converter with the damping
2 network included, which is depicted in Fig. 6, will be analyzed.
N2 (s) = Vg (Ro CLm s + (Lm n − Lm )s + Ro )
The damping network consists of a series connection of a
If the turns ratio n is equal to 1, the transfer functions Gvod1 (s) resistor Rd and a capacitor Cd connected in parallel with
and Gvod2 (s) are coincident, and the converter intermediate capacitor C. With this damping
¯ ¯ network included, the SSA model in CCM is
¯ ¯
Gvod1 (s)¯¯ = Gvod2 (s)¯¯
u=1; n=1 u=1; n=1 diLm (t) vg (t) − v C (t)(1 − d1 (t))
=
Vg R o dt Lm
= (12)
LRo Co s2 + Ls + Ro diL (t) v C (t)d2 (t) + vg (t) − v C (t)(1 − d1 (t)) − v o (t)
=
A similar procedure can be used to determine the small-signal dt L
control-to-output transfer functions GiL d1 (s) and GiL d2 (s). dv C (t) −iL (t)d2 (t) + (iLm (t) + iL (t))(1 − d1 (t))
=
These transfer functions are also identical between the two dt C
modes of operation if n = 1. v C (t) − v Cd (t)
−
CRd
¯ ¯
¯ ¯ dv Co (t) iL (t) v o (t)
GiL d1 (s)¯¯ = GiL d2 (s)¯¯ = −
u=1; n=1 u=1; n=1 dt Co CRo
Vg (Ro Co s + 1) dv Cd (t) v C (t) − v Cd (t)
= (13) = (17)
LRo Co s2 + Ls + Ro dt Cd Rd
¯
¯ N3 (s)
Gvo d1 (s)¯¯ = (14) 1:1
D2 =1;n=1 D3 (s)
ig Lm L i
iLm L
where Ds1 + Q2 +
vg + Rd
2 Q1 vC Co vo Ro
N3 (s) = Vg ((Lm CRo − Lm CRo D1 )s − LmD1 s − C
+
Ds2

+(Ro + RoD1 2 − 2Ro D1 )) (15) −

Cd vCd −
−

Fig. 6. Coupled inductor buck-boost converter with RC type damping

D3 (s) = (D1 − 1)2 (LmCLRo Co s4 + LmCLs3 network and turns ratio 1:1 (n = 1).

+(Lm D1 2 Ro Co + Lm CRo + LRo Co As it can be expected from (2), with n = 1 and the steady-state
behavior of VCd , the converter operating point for constant
−2D1 LRo Co + D1 2 LRo Co )s2 ) + (Lm D1 2 + L
duty cycles d1 (t) = D1 , d2 (t) = D2 , and input voltage
−2D1 L + D1 2 L)s + (Ro − 2Ro D1 + Ro D1(16)
2
)) vg (t) = Vg is
According to (15), Gvo d1 has two RHP zeroes. The presence
of these RHP zeroes tends to destabilize feedback loops with Vg D2 (D2 + D1 − 1)
ILm =
wide bandwidth making the converter prone to oscillation [15]. Ro (1 − D1 )2
The dynamics of the zeroes is the inner behavior of the system Vg D 2
IL =
when the control is regulating the output without error, e.g., in Ro (1 − D1 )
a high gain closed-loop linear system, the poles are attracted Vg
by the zeroes. In a converter with an ideal regulation of the VC =
1 − D1
output voltage, the inner dynamics is usually associated to the Vg
input filter. Thanks to the magnetic coupling, the dynamics VCd =
1 − D1
of the zeroes of our converter in boost mode is of second Vg D 2
order, associated to the variables iLm and vc . Note that the Vo = (18)
1 − D1
zeroes in (15) depend on the parameters Lm and C. Therefore,
damping the dynamics of iLm and/or vc by adding a passive Linearizing the set of equations (17) around the operating point
network could transfer the RHP zeroes to the left half-plane (18), we obtain the small-signal SSA model (19)
(LHP). Following a similar procedure to the one reported db
x
in [18]- [19], a passive network has been connected to the x + B1 db1 + B2 db2
= Ab (19)
dt

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where the small signal state vector x

b, the state matrix A and
the input vectors B1 and B2 of the system are now given by r
Lm
£ ¤T Cd = 8C, Rd ≈ 0.65 (25)
x
b= biLm biL vbC vbCd vbo C

 D1 −1
 In the previous section it was concluded that the small-signal
0 0 Lm 0 0 control-to-output transfer functions Gvod1 (s) and Gvod2 (s)
 0 0 D2 +D1 −1
0 − L1 
 L  have the same expression at u = 1. Moreover, this expression
 1−D1 1−D2 −D1 
A= C C − Rd1C 1
Rd C 0  corresponds to the small-signal control-to-output transfer func-
 1 
 0 0 Rd Cd − Rd1Cd 0  tion of a buck converter. To test the validity range of the small-
1
0 Co 0 0 − Ro1Co signal model, a PSIM frequency response simulation has been
carried out using the switched model schematic circuit diagram
h 2
iT shown in Fig. 7 and compared with the MATLAB calculated
V V V D
B1 = − Lm (Dg1 −1) − L(D1g−1) − CRo (D
g 2
2 0 0 frequency response corresponding to the SSA model (12). In
1 −1)

both cases, the parameters, whose selection will be explained

h iT in the next section, are: Lm = 14 µH, C = 2.6 µF,
V Vg D2
B2 = 0 − L(D1g−1) CRo (D1 −1) 0 0 Rd = 1.5 Ω, Cd = 22 µF, L = 30 µH, Co = 110 µF,
Ro = 9.6 Ω. Three different input voltages Vg = 39 V
The transfer functions Gvod1 (s) and Gvod2 (s) have now (step-up, u > 1), Vg = 48 V (border, u = 1), and
a third order numerator and a fifth order denominator with Vg = 55 V (step-down, u < 1) have been considered. The
two dominant complex poles. In the border between buck and duty cycles have been chosen to have a steady state output
boost operation modes, where u = 1, there is a triple zero- voltage Vo = 48 V. The waveforms depicted in Fig. 3 were
pole cancellation and the two transfer function correspond to obtained for the previous list of component values.
expression (12). Since this control-to-output transfer function
The Bode plots of both frequency responses obtained from
is identical to that of a second order buck converter, it is
PSIM (switched) and MATLAB (small-signal) are superim-
possible to design its control loop compensator in the same
posed for the three different values of the input voltage and
well-known way if the internal dynamics corresponding to
are depicted in Fig. 8. In this figure, the maximum frequency
the cancelled poles is sufficiently damped. The poles of the
plotted corresponds to 50 kHz, which is half of the switching
internal dynamics are the roots of the cancelled polynomials
frequency. The frequency responses are very similar in shape
in
to a second order system with two complex poles and no
¯ ¯ zeroes. We conclude that our buck-boost converter can be
¯ ¯ p(s)(vg Ro )
Gvod1 (s)¯¯ = Gvod2 (s)¯¯ = modelled and controlled as a buck converter for the input
u=1 u=1 p(s)(LRo Co s2 + Ls + Ro ) voltage range considered in the example.
(20)
where

p(s) = Lm Rd CCd s3 + (Lm Cd + Lm C)s2 + Rd Cd s + 1 (21)

Equating the coefficients of (21) to a third degree polynomial
in the following factorized form
p(s) = (ατ s + 1)(τ 2 s2 + 2ζτ s + 1) (22)
yields the expression of the damping network capacitor (see
Appendix)

2ζC(1 + 2αζ + α2 )
Cd = (23)
α
Since it is desired to minimize the size of the capacitor Cd ,
a value of α = 1 is selected. With this choice, the expression
of the damping resistance Rd is given by
√ r
(1 + 2ζ) 1 + 2ζ Lm
Rd = (24)
4ζ(ζ + 1) C
Finally, ζ = 1 is selected as a trade-off between the size of the
capacitor and a sufficient and robust damping of the internal Fig. 7. Circuit diagram corresponding to the PSIM simulation used to
calculate the frequency response of the control-to-output transfer function.
dynamics. The resulting expressions of the damping network
parameters are

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80
vg=39 V
where fc is the crossover frequency of the voltage loop.
vg=48 V
60 TABLE I
vg=55 V P EAK TO PEAK RIPPLE OF THE CONVERTER VARIABLES iL , ig AND vC IN
vg=39 V CCM
Magnitude [dB]

40
v =48 V
g
v =55 V Ripple Buck mode Boost mode
g
20 (Vg − Vo )Vo T Vg (Vo − Vg )T
4iLpp
Vg L Vo L
(Vg − Vo )Vo T Vg (Vo − Vg )T (L + Lm )
0 4igpp
Vg L Vo LLm
(Vg − Vo )Vo2 T (Vo − Vg )T
−20 4vCpp
Vg2 Ro C Ro C

−40 3 4 5
10 10 10 After performing a worst case analysis in both buck and
Frequency [Hz] boost modes to get the specifications at the nominal power,
0
vg=39 V the finally selected components of the buck-boost converter
vg=48 V power stage are the ones listed in Table II. To achieve a
−50 vg=55 V good efficiency, N-channel MOSFETs with low on-resistance
vg=39 V and fast Schottky diodes have been selected. Kool Mµ core
Phase [deg]

−100
vg=48 V inductors have been chosen by their low-cost and availability.
v =55 V Capacitors that must absorb high pulsed current are ceramic.
g

The ESR (Equivalent Series Resistance) of Cd is much smaller

−150
than Rd . All components are rated up to 100 V.
TABLE II
−200 C OMPONENTS OF BUCK - BOOST CONVERTER
Component Description Type
−250 3 4 5
Q1 , Q2 Power MOSFET IRFB4110PbF
10 10 10 Ds1 , Ds2 Schottky Rectifier 40CPQ080GPbF
Frequency [Hz] Coupled Core: 77083A7 Magnetics
Lm inductors Wire size: 15 AWGb
Fig. 8. Frequency response of the small-signal control-to-output transfer
Number of turns: 13:13
function. The black lines correspond to the simulation of the switched model
using PSIM (Fig. 7) while the white lines correspond to MATLAB simulation C Ceramic Capacitor 3 × 2.2 µFa
of the linear small signal model (12). X7R dielectric
Co MKT Capacitor 5 × 22 µF
Core: 77083A7 Magnetics
IV. C IRCUIT DESIGN L Inductor Wire size: 15 AWGb
Number of turns: 20
A. Buck-boost converter power stage Rd Damping Resistor 1.5 Ω, 4 W
The buck-boost converter is designed as a battery discharge Cd MKT Capacitor 22 µF
a
regulator (BDR) of 13 in-series Lithium-ion battery cells, so The capacitance depends on the operating voltage. For
that an input voltage Vg range of 39 V to 55 V is considered. Vc = 48 V the equivalent capacitance is 2.6 µF.
b
The output voltage Vo regulates a DC bus of 48 V. The Multifilar equivalent.
maximum power output is 480 W corresponding to a load
resistance Ro = 9.6 Ω and the switching frequency is B. Buck-boost control circuit
100 kHz. The parameter values of the buck-boost converter of Once the model (12) has been verified in the previous
Fig. 6 have been selected according to specifications of input section, the next step is to design the control loop compensator.
and output peak to peak current ripples of 4igpp = 12 A A compensation network for the buck converter-like transfer
and 4iLpp = 4 A; maximum output impedance of function plotted in Fig. 8 has been designed following classical
Zomax = 150 mΩ; maximum power dissipation in the rules [27]. The third order compensator transfer function is
damping resistor PRd = 4 W, and also expression (25). The
expressions used to calculate the ripples of iL , ig and vc are u
b (τ3 s + 1)(τ4 s + 1)
Gc = =K (28)
listed in Table I. If a triangular shaped vc ripple is assumed, vbo s(τ1 s + 1)(τ2 s + 1)
the power loss in Rd is where the compensator parameters has been selected as follow:
4vCpp τ1 = 1 µs, τ2 = 2 µs, τ3 = τ4 = 1/(2π) ms, and
P Rd = (26) K = 210 s/V.
12Rd
The circuit diagram of the compensator and the PWM
The maximum output impedance in closed loop can be calcu-
implemented in PSIM is presented in Fig. 9(a), where an
lated approximately as
estimation of the switching delays has been included. The
1 existence of delays impedes having extreme duty cycles and
Zomax = (27) causes a nonlinearity in the transitions between boost and
2πfc Co

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010
buck modes [28]. To mitigate these problems, a third mode
of operation is permitted in an adjustable small vicinity zone
between buck and boost modes [7], [28]. The new operation
mode is called buck-boost mode because the previous two
modes overlap in interleaving-like manner, i.e., both MOS-
FETs can switch in the same period but their switching instants
are almost π rad out of phase. The overlapping adjustment is
achieved by reducing the displacement between the signals
that generate u1 and u2 when compared with the triangular
signals.
The circuit schematic diagram of the buck-boost control
experimental stage is shown in Fig. 9(b). The main component
of the control system is the dual PWM controller integrated
circuit TL1451A that generates the switch activation signals
u1 (t) and u2 (t). This single monolithic chip has two error
amplifiers, an adjustable oscillator, a reference voltage of
2.5 V, and dual common-emitter output transistor circuits.
The triangular signal oscillator has been adjusted to have a
frequency of 100 kHz, an amplitude of 0.7 V and a DC offset
of 1.4 V. One of the error amplifiers is used to implement the
compensator (28) to obtain the signal u, and the other one
is used to get the signal (u − 0.7 + overlapping adjustment)
in the manner presented in Fig. 9(c). This figure shows an
example of the driving signals u1 and u2 generation.
(a)
(b)
(c)
Fig. 9. Schematic of: (a) the compensator Gc and the dual PWM simulated
in PSIM, (b) buck-boost control circuit diagram, (c) an example of driving
signals generation.
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8
C. Buck-boost driver with modified bootstrap
An IR2110 integrated driver has to switch the low side N-
Channel MOSFET in the boost stage Q1 , and the high side
N-Channel MOSFET of the buck stage Q2 . A bootstrap circuit
is needed to supply the floating voltage to drive Q2 . In buck
operation, Q1 should be always OFF while Q2 switches. In
buck-boost mode both Q1 and Q2 are switched in the same
period. In these two previous modes a classical bootstrap
circuit would operate correctly. The most critical operation
of the driver occurs in pure boost mode because the bootstrap
capacitor CB must be sufficiently charged to keep Q2 ON
for as long as needed. In these circumstances, the capacitor of
conventional bootstrap circuits could be insufficiently charged.
To avoid the malfunction of the converter in boost mode, it
is then necessary to refresh the capacitor charge. A solution
of this problem is presented in [29], where a charge pump
topology with an external clock signal is used. A similar
charge pump driver that refreshes the bootstrap capacitor with
the use of the boost control pulses is shown in Fig. 10. Since
the source of Q2 is always at a level higher than 15 V, the
usual bootstrap path through diode DA will be cut OFF, and
an additional bootstrap circuit made of CBaux , DB , DC , TC ,
TD , and a couple of resistors, has been added to recharge CB .
The boost pulses turn on the auxiliary Darlington transistor
TD , permitting that CBaux charges to 15 V through DA ,
DC and TD . The direct polarization of DC keeps TC OFF.
When TD turns OFF, TC starts conducting providing through
DB a current path to recharge CB from CBaux . Fig. 9(b)
shows a variable resistor that permits the empirical overlapping
adjustment that guarantees a proper charging of the bootstrap
capacitor by switching the high side MOSFET when the boost
driving pulses are narrower than 2%. A couple of cascaded
linear regulators provide the supply voltages (15 V and 5 V)
of the driver and control circuit from the input voltage.
Fig. 10. Scheme of the buck-boost driver with a modified bootstrap circuit
and auxiliary supplies.
V. E XPERIMENTAL RESULTS
Fig. 11 shows pictures of the power stage and the control
circuit of the buck-boost regulator prototype. The experimental
response of the buck-boost regulator to a low-frequency trian-
gular input voltage going from 36.8 V to 55.8 V is depicted
in Fig.12 where the waveform of the output voltage could be
compared with its corresponding simulation. In addition to the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 9

97.5

97
vg= 39 V
96.5 v = 43 V
g

η [%]
vg= 47 V
96
v = 48 V
g
vg= 51 V
95.5
vg= 55 V

95

94.5
2 4 6 8 10
(a) (b) iR [A]
o

Fig. 11. Regulator prototype (a) buck-boost power stage, (b) dual PWM (a)
control stage.
97.5

97 iR = 2 A
o
input and output voltages, the simulated logic signals u1 and 96.5
iR = 4 A
o
u2 , ranging from 0 V to 1 V, are also depicted on the left. i =5A

η [%]
R
o
The oscillogram on the right shows the equivalent signals that 96
iR = 6 A
correspond to the outputs of the dual PWM controller that o
iR = 8 A
95.5
are in the 0 V to 5 V range. The input voltage range ensures o
iR = 10 A
that in both simulation and experimental measurements the 95 o

converter works in its three operation modes. The output

voltage is well regulated and exhibits a smooth behavior in all
the transitions between modes. These good results are due to
the use of the same controller in all the operation modes. The
sampling capabilities of the digital oscilloscope have permitted
to capture the switching noise in the output voltage waveform.
There is less switching noise in boost mode because it is
attenuated at the output by a third order filter while the buck
stage has only a second order filter between its switches and
the output.
94.5
40 45 50 55
vg [V]
(b)
Fig. 14. Energy conversion efficiency for Vo = 48 V as: (a) a function of
the output current iRo for different input voltage vg levels, (b) a function of
the input voltage vg for different output current iRo levels.
efficiencies as a function of the output current iRo for different
input voltage vg levels are shown in Fig. 14(a), whereas in
Fig. 14(b), the horizontal axis is the input voltage and the
output current is the parameter of the set of curves. Since
some switching losses penalty is paid in buck-boost mode, for
a given current the maximum efficiencies are attained in boost
and buck modes when the input voltage is close to the desired
output level. The maximum efficiency obtained of about 97%
would be improved if the diodes could be substituted by
synchronous rectifier MOSFETs [12], [13]. Other techniques
like multiphase and ZVS [12] or dynamic adjustment of the
switching frequency [13] are also possible.
TABLE III
C ROSSOVER FREQUENCY (CF) AND PHASE MARGIN (PM) FOR DIFFERENT
INPUT VOLTAGES

Simulated Experimental
Vg CF PM CF PM
Fig. 13. Experimental configuration of the measurement of efficiency: (a)
buck-boost converter, (b) buck-boost control, (c) DC power supply, (d) Power [V] [kHz] [deg] [kHz] [deg]
analyzer, (e) oscilloscope, (f) DC electronic load. 39 13 54 11 51
48 18 62 18 61
Figure 13 shows the experimental setup for measuring the 55 17 65 16 65
efficiency of the hard-switching buck-boost converter. The
efficiency measurements take into account the consumption PSIM-simulated and experimental Bode plots of the regu-
of the drivers and control stages. A Voltech PM6000 Power lator loop gain are illustrated in Fig. 15. In the simulations,
Analyzer with calibrated precision shunt resistors is used to an estimation of delays and loses have been taken into ac-
measure the input and output currents. The energy conversion count. The frequency measurements have been obtained using

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 10

Vg [V]
60
40
20
100 150 200 250 300
Time [ms]
Vo [V]

48.5
48
47.5
100 150 200 250 300
Time [ms]
u2 [V]

1.5
1
0.5
0
−0.5
100 150 200 250 300
Time [ms]
u1 [V]

1.5
1
0.5
0
−0.5
100 150 200 250 300
Time [ms]
(a) (b)
Fig. 12. Waveforms of input voltage Vg , output voltage Vo , boost pulses u1 and buck pulses u2 for changes in the input voltage. (a) PSIM simulation (b)
Waveforms measured. CH1: Vg (10 V/div), CH2: Vo (1 V/div, AC coupling), CH3: u1 (5 V/div), CH4: u2 (5 V/div), timebase: 20 ms/div.

a frequency response analyzer (FRA) Venable 3120. This
frequency response has the three above mentioned different
modes of operation that are achieved by varying the value
of the input voltage vg . Some of the differences that can
be observed between simulated and experimental results for
vg = 48 V are attributed to the nonlinearities in the transitions
between modes mentioned previously. Other differences are
mainly due to nonlinearities in some passive components of
the experimental prototype. For instance, the capacitance of
the intermediate capacitor exhibits a strong dependency on
the applied voltage as has already been noted in Table II.
Also, the parameters of the magnetic components vary with
the mean average current flowing through them. The crossover
frequency (CF) and phase margin (PM) are calculated and
listed in Table III for each input voltage value. In spite
of the differences observed between the simulated and the
experimental frequency responses, the table shows remark-
ably similar results in all cases. Like in a buck regulator, a
wide bandwidth is achieved since the crossover frequency is
between one tenth and one fifth of the switching frequency.
Furthermore, the phase margins indicate that the feedback
system is stable for the desired input voltage range.
Figs. 16, 17, and 18 show simulated and experimental
transient responses to load changes for different constant input
voltages corresponding to boost, near buck-boost and buck
modes respectively. For each input voltage, the load current
has been changed from 10 A to 5 A in the top subplots (a)
and (b) and back form 5 A to 10 A in the bottom subplots
(c) and (d). In all cases, the output voltage is well regulated
and the transient deviations are within the desired boundaries.
In addition to output voltage and current, the input current
and the intermediate capacitor voltage are also depicted. The
transient dynamics of these variables is damped as expected,
with a reasonable agreement between simulated and measured
variables. The main discrepancy appears near the buck-boost
mode as it is illustrated in Figs. 17(a) and 17(b). Extreme
duty cycles, close to zero or to one, are required to obtain
a smooth transition between operation modes, but they are
not possible to achieve in practice due to the unavoidable
switching delays. For this reason, when the input and output
voltages are close, switching pulses can be skipped and the
resulting ripple contains components at frequencies below of
the converter switching frequency [28].The skipped pulses
also appear in transients like the one depicted in Fig. 18(d)
where a couple of buck pulses are missed and an intermediate
unexpected boost pulse appears. In our prototype, this noise
is attenuated by the output LC filter or rejected by the control
loop and has little effect on the output voltage.
VI. C ONCLUSION
A new non-inverting buck-boost DC-DC switching con-
verter has been obtained by magnetically coupling the input
and output inductors of a cascade connection of a boost
and a buck stages. The combination of a coupling and a
damping network at the intermediate capacitor provides a
minimum-phase control-to-output transfer function with two
dominant complex poles. Simulation and experimental results
of a prototype verify the predicted wide control bandwidth due
to the absence of RHP zeroes. A high efficiency is obtained
by operating the converter switches in three regions depending
on the input-output voltage ratio: boost, buck and buck-boost.
In the buck-boost region both MOSFET are allowed to switch
in the same period but this overlapping is permitted only for
a narrow range of nearly equal input and output voltages
to improve the efficiency. The converter operates usually in
the other more efficient modes in which there is only one
periodically switching MOSFET. In buck mode, the MOSFET
of the boost stage is always OFF, whereas in boost mode, the
buck stage MOSFET is continuously ON, which has required
a specially built bootstrap driver for the buck stage high-side
N channel MOSFET.
For a given specification of output impedance and volt-
age ripple, we believe that the proposed converter could
offer a solution with larger magnetic components but smaller
capacitors than other state-of-the-art topologies. Since both
input and output currents are of non pulsating nature there

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20 20
v =39 V v =39 V
g g
15 v =48 V 15 v =48 V
g g
v =55 V v =55 V
10 g 10 g
Magnitude [dB]

Magnitude [dB]
5 5

0 0

−5 −5

−10 −10

−15 −15

−20 4
−20 4
10 10
Frequency [Hz] Frequency [Hz]
(a) (b)
−100 −100

−110 −110

−120 −120
Phase [deg]

Phase [deg]
−130 −130

−140 −140

−150 −150

−160 v =39 V −160 v =39 V

g g
v =48 V v =48 V
−170 g −170 g
v =55 V v =55 V
g g
−180 4
−180 4
10 10
Frequency [Hz] Frequency [Hz]
(c) (d)

Fig. 15. Loop gain Bode plots of the buck-boost converter: boost mode for vg = 39 V, buck-boost mode for vg = 48 V and buck mode for vg = 55 V. a)
Simulated magnitude, b) Experimental magnitude, c) Simulated phase, d) Experimental phase.

are two or more possible current control strategies. For that

reason, controlling the converter in current mode is a work in Lm C(α + 2ζ)
τ2 = (A.4)
progress. The capability of cycle-by-cycle limiting the input α
and/or output converter currents offers interesting possibilities
Substituting (A.4) in (A.2) and isolating Cd gives (23). From
to many applications like battery, supercapacitor, PV panel
(A.3) and (A.4), it is straightforward that
or fuel cell energy management. Future works contemplate
also a bidirectional implementation of the switches that could
τ (α + 2ζ)
provide even higher conversion efficiencies. Another open Rd = (A.5)
problem is the converter operation at light loads where several Cd
discontinuous conduction modes can appear. Since the derivative of (23) with respect to α is

A PPENDIX dCd 2ζC(α2 − 1)

DAMPING NETWORK PARAMETER CALCULATION = (A.6)
dα α2
Equating (21) and (22) gives the following set of equations
Cd has a minimum for α = 1.
Expression (A.5), particularized for α = 1, yields (24).
ατ 3 = Rd Cd Lm C (A.1)

ACKNOWLEDGMENT
τ 2 (2αζ + 1) = Lm (Cd + C) (A.2)
The authors would like to thank José Maria Bosque for his
τ (α + 2ζ) = Rd Cd (A.3) aid in the construction of the prototype, and Luis Martı́nez-
Salamero and the anonymous reviewers for their valuable
Dividing (A.1) by (A.3) and isolating τ 2 yields comments.

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20

15
Current [A]
10

0
3.98 4 4.02 4.04 4.06 4.08 4.1 4.12 4.14 4.16
Time [ms]

60 48.5

vo [V]
vc [V]

50 48

40 47.5
4 4.05 4.1 4.15 4.2
Time [ms]

(a) (b)

25

20
Current [A]

15

10

0
7.95 8 8.05 8.1 8.15 8.2 8.25 8.3
Time [ms]

60 48.5
vo [V]
vc [V]

50 48

40 47.5
7.95 8 8.05 8.1 8.15 8.2 8.25 8.3
Time [ms]

(c) (d)
Fig. 16. PSIM simulations (a), (c) and experimental measurements (b), (d) of the converter main variables when the load current changes from 10 A to 5 A
and back to 10 A while the input voltage is Vg = 39 V. Black traces shows the simulated output current iRo and output voltage vo while the input current ig
and the intermediate capacitor voltage vc are in white. CH1: vc (5 V/div), CH2: vo (500 mV/div, AC coupling), CH3: ig (5 A/div) and CH4: iRo (5 A/div).

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 13

12

10
Current [A]
8

2
3.98 4 4.02 4.04 4.06 4.08 4.1 4.12 4.14 4.16
Time [ms]

55 48.5

50 48

vo [V]
vc [V]

45 47.5

40 47
4 4.05 4.1 4.15 4.2
Time [ms]

(a) (b)

20

15
Current [A]

10

0
7.95 8 8.05 8.1 8.15 8.2 8.25 8.3
Time [ms]

60 48.5
vo [V]
vc [V]

50 48

40 47.5
7.95 8 8.05 8.1 8.15 8.2 8.25 8.3
Time [ms]

(c) (d)
Fig. 17. Simulated (a), (c) and measured (b), (d) converter main variables for the same load changes of Fig. 16 and Vg = 46 V.

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Conf. Expo., APEC, Mar. 2006, pp. 603–609.
[22] E. Sanchis-Kilders, A. Ferreres, E. Maset, J. Ejea, V. Esteve, J. Jordan,
J. Calvente, and A. Garrigos, “Bidirectional high-power high-efficiency
non-isolated step-up dc-dc converter,” in Proc. 37th IEEE Annu. Power
Carlos Restrepo (S’10) graduated, with honors,
Electron. Specialists Conf., PESC, Jun. 2006, pp. 1–7.
as Ingeniero Electricista and Master en Ingenierı́a
[23] E. Sanchis, E. Maset, A. Ferreres, J. B. Ejea, J. Calvente, A. Garrigos, Eléctrica in 2006 and in 2007, respectively, from the
V. Esteve, J. Jordan, and B. J. M., “Bidirectional high-efficiency non- Universidad Tecnológica de Pereira, Colombia. He
isolated step-up battery regulator,” IEEE Trans. Aerosp. Electron. Syst., obtained the Master en Ingenierı́a Electrónica from
To be published. the Universitat Rovira i Virgili de Tarragona, Tarra-
[24] J. Calvente, L. Martinez-Salamero, P. Garces, R. Leyva, and gona, Spain, in 2008. He is currently working toward
A. Capel, “Dynamic optimization of bidirectional topologies for bat- the Ph.D. degree in the Departamento d’Enginyeria
tery charge/discharge in satellites,” in Proc. 32nd IEEE Annu. Power Electrònica, Elèctrica i Automàtica, Escola Tècnica
Electron. Specialists Conf., PESC, vol. 4, 2001, pp. 1994–1999. Superior d’Enginyeria, Universitat Rovira i Virgili
[25] R. Middlebrook and S. Ćuk, “A general unified approach to modeling de Tarragona. His main research interests includes
switching-converter power stages,” in Rec. IEEE Power Electron. Spe- fuel cell modelling and power converters design.
cialists Conf., Jun. 1976, pp. 18–34.
[26] E. Van Dijk, J. Spruijt, D. O’Sullivan, and J. Klaassens, “Pwm-switch
modeling of dc-dc converters,” IEEE Trans. Power Electron., vol. 10,
no. 6, pp. 659 – 665, Nov. 1995.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 14

10

Current [A] 8

2
3.98 4 4.02 4.04 4.06 4.08 4.1 4.12 4.14 4.16
Time [ms]

60 48.5

vo [V]
vc [V]

55 48

50 47.5
4 4.05 4.1 4.15 4.2
Time [ms]

(a) (b)

10
Current [A]

2
7.95 8 8.05 8.1 8.15 8.2 8.25 8.3
Time [ms]

60 48.5
vo [V]
vc [V]

55 48

50 47.5
7.95 8 8.05 8.1 8.15 8.2 8.25 8.3
Time [ms]

(c) (d)
Fig. 18. Simulated (a), (c) and measured (b), (d) converter main variables for the same load changes of Fig. 16 and Vg = 55 V.

Javier Calvente (S’94-M’03) received the Inge-
niero de Telecomunicación degree and the Ph.D.
degree from the Universitat Politècnica de Catalunya
(UPC), Barcelona, Spain, in 1994 and 2001, re-
spectively. He was a visiting scholar with Alca-
tel Space Industries, Toulouse, France, in 1998.
He is currently an Associate Professor with the
Departamento dEnginyeria Electrònica, Elèctrica i
Automàtica, Universitat Rovira i Virgili (URV), Tar-
ragona, Spain, where he is working in the fields of
power electronics and control systems.
Angel Cid-Pastor (S’99-M’07) He graduated as
Ingeniero en Electrónica Industrial in 1999 and as
Ingeniero en Automática y Electrónica Industrial
in 2002 at Universitat Rovira i Virgili, Tarrag-
ona, Spain. He received the M.S. degree in de-
sign of microelectronics and microsystems circuits
in 2003 from Institut National des Sciences Ap-
pliquèes, Toulouse, France. He received the Ph.D.
degree from Universitat Politècnica de Catalunya,
Barcelona, Spain, and from Institut National des Sci-
ences Appliquèes, LAAS-CNRS Toulouse, France in
2005 and 2006, respectively. He is currently an associated professor at the
Departament dEnginyeria Electrònica, Elèctrica i Automàtica, Escola Tècnica
Superior dEnginyeria, Universitat Rovira i Virgili, Tarragona, Spain. His
research interests are in the field of power electronics and renewable energy
systems.
Abdelali El Aroudi (M’00) was born in Tangier
(Morocco), in 1973. He obtained the graduate de-
gree in physical science from Facult des sciences,
Université Abdelmalek Essadi, Tetouan, Morocco, in
1995, and the Ph.D degree (with honors) from Uni-
versitat Politècnica de Catalunya, Barcelona, Spain
in 2000. During the period 1999-2001 he was a
visiting Professor at the Department of Electronics,
Electrical Engineering and Automatic Control, Tech-
nical School of Universitat Rovira i Virgili (URV),
Tarragona, Spain, where he became an associate
professor in 2001 and a full-time tenure Associate Professor in 2005. During
the period September 07-January 08 he was holding a visiting scholarship
at the Department of Mathematics and Statistics, Universidad Nacional de
Colombia, Manizales, conducting research on modeling of power Electronics
circuits for energy management. From February 2008 to July 2008, he was
a visiting scholar at the Centre de Recherche en Sciences et Technologies
de Communications et de l’Informations (CReSTIC), Reims, France. He
has participated in different Spanish domestic and cooperative international
research projects. His research interests are in the field of structure and
control of power conditioning systems for autonomous systems, power factor
correction, stability problems, nonlinear phenomena, chaotic dynamics, bi-
furcations and control. He is a reviewer for IEEE Transaction on Circuits
and Systems part. I- Regular papers and II Express Briefs, IEEE Trans-
actions on Power Electronics, IEEE Transactions on Industrial Electronics,
International Journal of Control, International Journal of Power Electronics,
IET Electric Power Applications, International Journal of Systems Science,
Circuits, Systems and Signal Processing, International Journal of Sound and
Vibration and Nonlinear Dynamics. He has published more than 150 papers
in scientific journals and conference proceedings. He is a member of the
GAEI research group (Universitat Rovira i Virgili) on Industrial Electronics

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 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. X, NO. X, JANUARY 2010 15

and Automatic Control whose main research fields are power conditioning for
vehicles, satellites and renewable energy. He has given invited talks in several
universities in Europe, South America and Africa.

Roberto Giral (S’94-M’02-SM’10) received the

B.S. degree in ingeniera técnica de telecomuni-
cación, the M.S. degree in ingeniera de telecomu-
nicación, and the Ph.D. (with honors) degree from
the Universitat Politècnica de Catalunya, Barcelona,
Spain, in 1991, 1994, and 1999, respectively. He
is currently an Associate Professor with the De-
partament dEnginyeria Electrònica, Elèctrica i Au-
tomàtica, Escola Tècnica Superior dEnginyeria, Uni-
versitat Rovira i Virgili, Tarragona, Spain, where he
is working in the field of power electronics.

Copyright (c) 2010 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.