8255

Introduction to Input-Output
o m
address & Memory . c
control
interface
address
e rs MEMORY
CPU
data bus
in e
n g
I/O address
& control
O E
I/O interface Outside world
D o eg. keyboard
a a printer
F CRT display
mass storage
ELE3230 - Chapter 12 2
I/O interface
❚ Input-output involves the transfer to (or from) peripheral devices
o m
from (or to) the data bus of the cpu eg. data transfer to the CRT
. c
rs
display, from the keyboard, to/from a hard disk drive, to/from a
modem to another computer system.
❚ Input-output operations fall into one n e e
g i of the following types:
E n
• Programmed I/O - cpu polls peripherals to check if I/O is needed
o O
• Interrupt I/O - peripheral sends an interrupt request to cpu for I/O
• Direct memory access
a D (DMA) - peripheral writes directly to memory
a I/O (I/O addresses are not part of memory
❚ 8088 usesFIsolated
address) as distinct from Memory mapped I/O (peripherals are
mapped to locations in the memory address space).
Q: pros and cons of isolated I/O and memory mapped I/O?
Memory and I/O Map
Memory
o m I/O
The Memory and I/O FFFFF
. c FFFF
maps for the 8086/8088
1M × 8
e rs 64K × 8
microprocessor.
in e
(a) Isolated I/O.
g
00000
n (a)
0000
(b) Memory mapped I/O.
O E
D o FFFFF
Memory + I/O
a a
F I/O
00000
(b)
I/O interface
cpu side
m
peripheral side
o
. c
data bus
data buffer registers
e rs Output ports
in e
address bus
g
status register
n
Input ports
control bus O E protocol line
D o I/O protocol unit
a a
F example of an I/O interface
Typically, not all data, address or control lines are needed.

Input and output ports maybe the same.
I/O interface
❚ I/O interface functions can include
o m
• data storage buffer for sending and receiving data
. c
• low-level communications protocol (handshaking)
e rs
• error detection in e
• data format conversion (eg. parallel/serial)
n g
• addressing of different peripherals
O E
o
❚ I/O interface are typically implemented by LSI (large scale
D
a
integration) - many different types are available from different
a
F
manufacturers.
❚ Data can be transferred through I/O interface by either
programmed I/O or interrupt I/O. DMA typically needs a separate
controller.
8088 maximum mode I/O interface
IORC
o m I/O device
. c 0
rs
IOWC
CLK Bus
ee
controller AIOWC
I/O device
S0-S3
8288
g i
ALE
n 1
E n DT/ R
DEN
I/O
8088
o O interface
circuitry
a D
AD0-AD7
F a A8-A19 I/O device

IO/ M N-1
Generalized I/O interface connections to maximum mode 8088

Parallel and Serial Data Transfer
❚ Data Transfer between the I/O interface and the peripheral can
o m
c
involve either parallel or serial data transmission, depending on the
.
rs
peripheral and the actual implementation of the I/O interface.
e
❚ Parallel data transfer involves usingn e
i lines are needed for the
at least 8 separate lines for the
g
8 data bits in a byte. Normally, other
communications protocol (eg.n
when data is valid, ACK O E STB [data strobe] line to indicate
line to acknowledge data has been read).
o
D is usually fast. Each data bit typically needs
STB: sent by sender ACK:sent by receiver
❚ a
a return line to reduce noise. A popular parallel data
Parallel data transfer
F
it’s own ground
transfer interface standard is the CENTRONICS type interface
which uses a 36-pin connector. The centronics interface is
commonly used in printers.
Parallel and Serial Data Transfer
(cont.)
m
❚ Serial data transfer involves sending the data on a single line, bit
o
c
by bit. The I/O interface converts the data from parallel to serial or
.
vice-versa using shift registers.
e rs
❚ i
Serial connections are commonly usedn efor data transfer over
n g
longer distances (eg over telephone line). A popular standard for
serial data transmission isE
the RS232C standard.
o O
a D
Fa
Serial I/O
❚ Serial I/O can be either
o m
c
markers. Individual characters within a block do not.need start and stop
(1) Synchronous - data are sent in blocks, with start and end-of-block
s
e
bits since the receiver identifies every 8 bits as r
one character, eg.
one framein
e
n g
syn syn stx
O E data field etx bcc pad
D o
a
syn = sync character (ascii code 16)
Fa
stx = start of text (ascii code 02)
etx = end of text (ascii code 03)
bcc = block check characters (error detection)
pad = end of frame pad ( ascii code ff)
Serial I/O
(2) Asynchronous - no block synchronization bits. Each character is
identified by the start and stop bit(s) (stop bits can be 1, 1!, 2 bits)
o m
inserted at the start and end of each character. . c
e rs
e
MSB LSB
in
Stop Parity Start
bit bit data bit
n g
O E
❚ Synchronous serial data transfer is more efficient (ie. faster) since
o
asynchronous transfer “wastes” about 30% of the bits for start and
D
a
stop bits in sending a 7-bit ASCII code.
a
❚
F
An example of asynchronous serial data transfer is the RS232
serial port found in most computers.
8255 Programmable Peripheral
Interface (PPI)
m
❚ Intel 8255A is a general purpose parallel I/O interface. It provides three
o
I/O port (A, B and C) and can be programmed as
. c
• Simple parallel I/O - no handshaking implemented
• Single handshake I/O - uses STB-ACK handshake e rs
in e
• Double handshake I/O - uses STB-ACK and STB-ACK
n g
data
O E simple
D o (no handshake)
strobe
a a
ACK
F
Single
Handshake
data
8255 Programmable Peripheral
Interface (PPI) (cont.)
strobe
o m
Tx
. c
rs
ee
Rx ACK Double
g i n Handshake
E n data
Data transferred after the
first STB and ACK.
o O
a D
❚ F
8255A’s mode
aof operation is determined by the contents of its control
register (see Intel data sheet for further details).
❚ Port A and Port B can be set to different mode and input/output
independently.
8255A Programmable Parallel
Port Device
Power +5V
o m
c
GROUP A I/O
.
Supply GND GROUP PORTA
PA7-PA0
rs
A (8)
CONTROL
e e
g in GROUP A
PRRT C
I/O
PC7-PC4
n
Bi-directional UPPER
Data Bus
E
DATA
Internal structure CI,CO BUS
O
BUFFER
8 BITS
block diagram
o
GROUP B I/O
INTERNAL PRRT C PC3-PC0
D
DATA BUS LOWER
a a
F RD
WR
A1
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROU B
PORT B
(8)
I/O
PB7-PB0
A0
RESET
CS
8255A Mode 0 Operation
❚ In Mode 0 operation, no handshaking will be used.
o m
If both port A and port B are initialized as mode 0coperation, port C
❚
r s
can be used together as an additional 8-bit port,
. or two 4-bit ports.
e e
❚ When used as an outputs, port C line
g
special control word to the control
n can be set/reset by sending
iregister address.
E n
❚
o O
The two halves of port C are
or output port independently.
independent and can be set as input
a D
Fa
ADDRESS BUS
o m
CONTROL BUS
. c
DATA BUS
e rs
in e
R D, W R
n g D7-D0 A0-A1
O E CS
D o 8255A
MODE 0
a a C
NO
F B A
HANDSHAKE 8 I/O 4 I/O 4 I/O 8 I/O

SIGNALS
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
❚ In Mode 1 operation, single handshaking (strobed) is used.
o m
❚ In this mode, some of the port C pins are used for
s . c handshaking
purpose.
e r
n e
❙ Port A set to mode 1 & input port: PC3, PC4, and PC5 pins are used.
i
n
❙ Port A set to mode 1 & output g
port: PC3, PC6, and PC7 pins are used.
❙ Port B set to mode 1 O

E
& input port: PC0, PC1, and PC2 pins are used.
❙ Port B set toa

o
D 1 & output port: PC0, PC1, and PC2 pins are used.
mode
Fa
o m
MODE 1
. c
B PC0 PC1 PC2 PC3 PC4
e rs
PC5 PC6 PC7 A
8 I/O
in e 8 I/O
n g
PB7-PB0
O E PA7-PA0
INTRB
D o
IBFB STB B INTRA STB A IBFA I/O I/O
HANDSHAKING
a a OR OR OR OR OR OR
INPUT
SIGNAL F
INTRB OBF B ACK B INTRA I/O I/O ACK A OBF A
HANDSHAKING
PORT A, PORT B CONTROL OUTPUT
SIGNAL
❚ Only port A can be initialized in mode 2.
o m
. c
❚ In mode 2, port A can be used as bi-directional handshake data
transfer.
e rs
❚ In this mode, PC3-PC7 are used forin
e
handshake lines.
n g
❚
O E
PC0-PC2 can be used as I/O pins if port B is set to mode 0.
❚
D
PC0-PC2 can be usedo as handshake lines if port B is set to mode 1.
a
Fa
Summary of Port C Usage
MODE 2
o m
for port A
. c
rs
B PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 A
e e
8 I/O
g in 8 I/O
PB7-PB0
E n PA7-PA0
o O
aD INTRA STB A IBFA ACK A OBF A BI-
F a
I/O OR CONTROL
DIRECTIONAL
BUS
PORT A CONTROL
PORT B MAY BE MODE 0
OR MODE 1
8255A Control Words
❚ Two control word formats are used:
o m
(1) mode-set control word format : to set the modes of each port
. c
rs
(2) port C bit set/rest control word format : to set the particular bit in
port C.
e e
❚
word. g i n
These two formats are differentiated by the MSB of the control
❚ The control words can be E nto the corresponding address where

sent
8255A is assigned to. O
Ex. AssumeD o
8255A is located at FFF8H, control register address
a isaFFFEH and the control word is to be set to 10001110B
F → MOV AL, 10001110B
MOV DX, 0FFFEH
OUT DX, AL
8255A Control Word Formats
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0 GROUP B
o m
PORT C (LOWER)
. c
rs
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
e e
MODE SELECTION
g
0 = MODE 0
in
n
1 = MODE 1
O E GROUP A
D o PORT C (UPPER)
1 = INPUT
a
0 = OUTPUT
F a PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG (a) Mode-set control word

1 = ACTIVE
8255A Control Word Formats
CONTROL WORD
o m
. c
BIT SET/RESET
rs
D7 D6 D5 D4 D3 D2 D1 D0
1 = SET
e e 0 = RESET
X X X
g in BIT SELECT
DON’T CARES
E n 0
0
1
1
2
0
3
1
4
0
5
1
6
0
7
1 B0
o O 0
0
0
0
1
0
1
0
0
1
0
1
1
1
1 B1
1 B2
a D
F a BIT SET/RESET
FLAG 0=FLAG
(b) Port C bit set/reset control word
Control Word examples for 8255A
Suppose we want to set
o
Port B as mode 1 inputm
. c
Port A as mode 0 output
D7 D6 D5 D4 D3 D2 D1 D0
e rs
Port C upper as inputs
1 0 0 0 1 1 1 0
in e
Port C bit 3 output and set bit 3
n g PORT C Lower (incl. BIT 3 )= OUT
O E PORT B INPUT
D o PORT B MODE 1
a a PORT C UPPER = IN
PORT A OUTPUT
F PORT A MODE 0
MODE SET WORD
(a) mode-set control word
Control Word examples for 8255A
(cont.)
o m
D7 D6 D5 D4 D3 D2 D1 D0
. c
0 0 0 0 0 1 1 1
e rs
in e SET BIT
n g
O E BIT # 3
D o MUST BE 0*
a a BIT SET/ RESET WORD
F
*:D6-D4 are set to 0 for simplicity and compatibility with future product.
(b) Port C bit set/reset control word to set bit 3
Strobed Output Operation
of 8255A (Mode 1 Port A)
Mode 1 Port A
o m
. c
Port A
e rs
CONTROL WORD
INTE A PC6 ACK
in e
n g D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1/0
2 1
PC7
O E OBF
D o PC4+5
3
a a 1 = INPUT
F PC3 INTR 0 = OUTPUT
PC4+5 I/O
Internal structure
(Mode 1) of 8255A
Mode 1 Port B
o m
. c
rs
Port B
INTE B
e e
in
PC2 ACK CONTROL WORD
PC1 OBF
n g
5 4
O E D7 D6 D5 D4 D3 D2 D1 D0
1 1 0
D o
6
a aPC0 INTR
F
Internal structure
Signal Definition of Mode 1
Strobed Output
❚ Whenever data are written to a port programmed as a strobed output
m
port, the OBF signal becomes a logic 0 to indicate that data are present
o
. c
in the port latch and is ready for external device to access. The external
ACK returns the OBF to logic 1. e rs

device strobes the ACK signal to indicate it has received the data. The
i n e
❚ OBF
port A or port B latch n
g
an output that goes low whenever data are output (OUT) to the
❚ ACK
O
an Acknowledge signalE that cause pin to return to a logic 1.
OBF
This signal is o
a response from external device to indicate it has
a D from 8255 port.
received data
❚ INTR
F a that often interrupts the processor when the external
a signal
device receives the data and sends back the ACK signal.
❚ INTE an internal bit programmed to enable or disable the INTR pin.
INTE A is programmed as PC6 (for output mode) or PC4 (for
input mode) and INTEB is PC2 (for both input/output mode).
(Mode 1) of 8255A
(Program) OUT DS
o m
WR
. c
OBF (buffer full)
e rs
in e
INTR
n g (Interrupt requested)
ACK
O E
D o
a a
Port
F
data sent to port data removed from port
Timing diagram
Example of Strobed Output
Mode of Operation for 8255A
o m
. c
rs
8255A printer
PB0
i n ee D0
n
ASCII
g
PB7
O E D7
o
aD PC2
ACK
ACK
Fa PC4 DS (Data Strobe)
8255A connected to a parallel printer interface
Strobed Input Operation
(Mode 1) of 8255A
Mode 1 Port A
o m
. c
rs
Port A
INTE A
e e CONTROL WORD
in
PC4 STB
PC5
n
IBFg D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0
2 1
O E
D o PC6+7
3
a a PC3 INTR
1 = INPUT
F PC6+7
0 = OUTPUT
I/O
Internal Structure
(Mode 1) of 8255A
Mode 1 Port B
o m
. c
Port B
e rs
INTE B PC2 STB
in e CONTROL WORD
n g D7 D6 D5 D4 D3 D2 D1 D0
5 4
PC1
O E IBF
1 1 1
D o
6
a a
F PC0 INTR
Internal Structure
(Mode 1) of 8255A
Level 0 trigger Port Latch
STB
o m
. c
IBF
e rs
INTR
in e
(buffer full)
g
(Interrupt requested)
n
RD
O E
D o
Port
a a
F data strobed into port data read by microprocessor
Timing diagram
8255A Status Word Format for
Mode 1 Input and Output
PORT C BITS
o m
D7 D6 D5 D4 D3 D2 D1 D0
. c
rs
GROUP A STATUS
i n ee GROUP B STATUS
INPUT PORT
n g INPUT PORT
O E
D7 D6 D5 D4
oD3 D2 D1 D0
aD
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Fa
STB STB
OUTPUT PORT OUTPUT PORT
D7 D6 D5 D4 D3 D2 D1 D0
OBF A INTEA I/O I/O INTRA INTEB OBF B INTRB
ACK ACK
Interfacing a Microprocessor to
Keyboard
o m
. c
Keyswitch Types
e rs
in e
(a) Membrane
n g
O E
D o
a a (c) Hall Effect
F (100M key strokes)
(b) Capacitive (D. Hall Fig 9-18)

20M key strokes
Detecting a Matrix Keyboard
Keypress
+5V
Q:
o m
+5V
. cAssume key “9” is pressed.
rs
For the following cases,
OUTPUT C D
e
E F
PORT 01 what are the values of D3-
Y D0
8 9 A
in
Be D0 at Port 2?
(1). Port 1, D3-D0=0000
X
O
D1
4 5
n g
6 7
(2). Port 1, D3-D0=1110
Y D2
O E (3). Port 1, D3-D0=1101
o
0 1 2 3
O open close
X
high high high
a
D3
D
low high low
F a
INPUT
PORT 02
D7
10 K Ω
D6
D5
D4
D3
D2
D1
D0 Port connections
Detecting a Matrix Keyboard
Keypress
o m
KEYBRD Read
. c
rs
Output
Columns Zero to
e e
DETECT
One Row
in
Zero to Read
All Rows N Key
Pressed?
n g Columns
Read
O E Y
Wait
N Key
Found?
ENCODE
Columns
D o 20 ms DEBOUNCE
Y
a a Read
Convert
N
F
All Keys
Open?
Y Columns
to HEX
N Key Y RETURN
Pressed?
Flowchart for procedure (D. Hall)

Interfacing to Alphanumeric Display
o m
. c
e rs
in e
n g
O E
D o
(a) 18-segment a
a (b) 5 by 7 dot matrix
displayF display format
(c) 5 by 7 dot matrix

circuit connections
(D Hall Fig 9-23)
Circuit Driving a 7-Segment LED
with 7447
o m
+5V
. c
rs
MAN 7
e e
g in
E n
o O
160 Ω EACH
aD 13 12 11 10
a b c d
9
e
15 14
f g
+6V
Fa +5V
16
8
Vcc
GND 7447
BI
RBI
LT
5
4
3
A B C D
7 1 2 6
BCD INPUTS
Multiplexing 7-segment Displays
with a Microcomputer
o m
. c
e rs
in e
n g
O E
D o
a a
F
Q: Only one 7447 for all 7 digits. → display the same values for all?
A: multiplex method
8254 Software-Programmable
Timer/Counter
❚ 8254 is very versatile and can be used in many applications.
o m
❚ There are several modes of operation for different applications.
. c
rs
❚ Intel 8253 and 8254 are almost pin-to-pin compatible except
e
in e
❙ The maximum input clock frequency for 8253 and 8254 is 2.6 MHz
and 8 MHz, respectively. (10MHz for 8254-2)
n g
❙ 8254 has a read-back feature which allows you to latch the count in all
have this feature. O E

the counters and the status of the counter at any point. 8253 does not
D o
❚ 8254 contains three 16-bit counters. The counter can be
a a
programmed to load the initial count, start and stop the count.
F
❚ 8254 has an 8-bit interface to data bus, and two address input A0
and A1 to address each of the three counters.
8254 Block Diagram
DATA COUNTER
o m CLK 0
D7-D0 8 BUS
. c GATE 0
rs
0 OUT 0
BUFFER
e e
RD
in
INTERNAL BUS
WR READ/
n g COUNTER
CLK 1
A0 WRITE
LOGIC
O E 1
GATE 1
OUT 1
A1
D o
a a
CS
F CONTROL
WORD
COUNTER
CLK 2
GATE 2
2
REGISTER OUT 2
8254 Pin Configuration
o m
D7 1 24 Vcc
. c
D6
D5
2 23
e
WR
rs
e
3 22 RD
in
D4 4 21 CS
g
D3 5 20 A1
D2
D1
E
6
7 n8254
19
18 CLK2
A0
o O
D0 8 17 OUT2
aD CLK 0
OUT 0
9
10
16
15
GATE2
CLK1
F a GATE 0
GND
11
12
14
13
GATE1
OUT1
Internal Block Diagram of a Counter
INTERNAL BUS
o m
. c
CONTROL STATUS
LATCH
e rs
e
WORD
REGISTER
in
CRM CRL
g
STATUS
REGISTER
E n
CONTROL
o O CE
D
LOGIC
a a
F OL M OL L
GATE n
CLK n OUT n
Initializing 8254
❚ When power on, programmable peripheral devices such as
8254 are usually in undefined state. → need initializationo m
. c
❚ Initialization steps:
e rs
in e
1. Determine the base address of the device from the address decode
circuitry or the address decoder truth table.
n g
2. Determine the internal address for each 8254 internal device (control
E
register, port, counters, status register, etc.)
O
D o
3. Add each of the internal address to the system base address to
determine the system address of each device.
a a
4. Look in data sheet for the device for the format of the control word(s)
F
that you have to send to the device to initialize it.
5. Construct the control word required to initialize the device.
6. Send the control word to the device. In case of the 8254, you need to
send the starting count to each of the counter registers.
8254 Addresses
A1 A0 SELECTS
o m
. c
rs
0 0 COUNTER 0
Internal 0
1
1
0
COUNTER 1
COUNRER 2
e e
1 1 in
CONTROL WORD REGISTER
g
E n
o O
SYSTEM ADDRESS 8254 PART
FDF 0 1
a
aF F 0 3 COUNTER 0 Register
System*
F F F 0 5
COUNTER 1 Register
COUNTER 2 Register
F F 0 7 CONTROL Register
Note : This system address is circuit-dependent.

In this example, 8254’s A1 and A0 are connected to CPU’s pin A2 and A1.
8254 Control Word Format
A1A0 = 11 CS = 0 WR = 0 RD = 1
o m
D7 D6 D5 D4 D3 D2 D1 D0
. c
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
e rs
in e
(1) SC - Select Counter
n g
SC1 SC0
O E
0
D o
0 Select Counter 0
0
a a 1 Select Counter 1
F1 0 Select Counter 2
1 1 Read-Back Command
(see Read Operations)
8254 Control Word Format (cont.)
(2) RW - Read/ Write
RW1 RW0
o m
. c
0 0 Counter Latch Command
e
(see Read Operations) rs
0 1
i n
Read/Write least esignificant byte only
1 0
n g
Read/Write most significant byte only
1 1
O E
Read/Write least significant byte first
D o then most significant byte

(4) BCD a a
F0 Binary Counter 16-bits
1 Binary Coded Decimal (BCD) Counter
(4 Decades)
8254 Control Word Format (cont.)
(3) M - Mode
o m
M2 M1 M0
s . c
0 0 0 r
e One-Shot
Mode 0 - Interrupt on Terminal Count
0 0 1
n e
Mode 1 - Hardware
i
× 1 0 g
Mode
n 2 - Pulse Generator
× 1 1 EMode 3 - Square Wave Generator
O Mode 4 - Software Triggered Strobe
1 0
D o0
1 0
a a 1 Mode 5 - Hardware Triggered Strobe
F
NOTE:
Don’t Care bits (×) should be 0 to insure
compatibility with future Intel products
Example of a control word
Task: Use counter 0 of the 8254 to divide a clock signal at 2.45 MHz to
78.6 kHz (1/32).
o m
. c
MOV AL, 00010111B
e rs
; Control word for counter 0
e
; Read/write LSB only, mode 3, BCD countdown
in
;
n g
; 00 01 011 1
BCD countdown
;
O E Mode 3
D o ; R/W LSB only
a a ; Select counter 0
MOV
OUT F
DX, 0FF07H
DX, AL
; Point at 8254 control register (see page 54)
; Send control word
MOV AL, 32H ; Load lower byte of count
MOV DX, 0FF01H ; Point to counter 0 count register
OUT DX, AL ; Send count to count register
Six Modes of Operation for 8254
Programmable Interval Timer
o m
. c
e rs
in e
n g
O E
D o
a a
F
(Brey Fig10-35)
ELE3230
The G input stops - Chapter
the count when 12 0 in modes 2, 3 and 4 65
8254 Mode Operation
❚ Mode 0: Allows 8254 counter to be used as an event counter. The
o m
output becomes a logic 0 when the control word is written and remains
until N plus the number of programmed counts.
. c
e rs
multivibrator (one shot). In this mode, i n e
❚ Mode 1: Causes the counter to function as a retriggerable monostable
n
that it develops a pulse at the OUT g the G input triggers the counter so
connection that becomes a logic 0 for
the duration of the counter. IfE
o O
goes low for 10 clock period
the count is 10, then the OUT connection
when triggered. If the G input occurs within
the duration of theD
a connection continues for the total length of the count.
count and theaOUT
output pulse, the counter is again reloaded with the
F
❚ Mode 2: Allows the counter to generate a series of continuous pules
that are one clock pulse in width. The separation between pulses is
determined by the count. (periodic pulse generator)
8254 Mode Operation (cont.)
❚ Mode 3: Generates a continuous square-wave at the OUT connection,
o m
provided the G pin is a logic 1. If the count is even, the output is high for
. c
one-half of the count and low for one-half of the count. If the count is odd,
rs
the output is high for one clocking period longer than it is low.
e
in e
g
❚ Mode 4: Allows the counter to produce a single pulse at the output. If
n
O E
the count is 10, the output is high
clocking period. (software-triggered
for 10 clocking period and then low for 1
strobe) (Writing the count to the
counter register startso the count.)
a D
❚
a
Mode 5:FA hardware triggered one-shot that functions as mode 4
except that it is started by a trigger pulse on the G pin instead of by
software. This mode is also similar to mode 1 because it is retriggerable.
(hardware-triggered strobe) (Count will be transferred to counter register
after trigger goes high.)

8255

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Introduction to Input-Output

control bus O E protocol line

D o I/O protocol unit

Typically, not all data, address or control lines are needed.

F a A8-A19 I/O device

Generalized I/O interface connections to maximum mode 8088

HANDSHAKE 8 I/O 4 I/O 4 I/O 8 I/O

❙ Port B set to mode 1 O

❙ Port B set toa

❚ The control words can be E nto the corresponding address where

MODE SET FLAG (a) Mode-set control word

(b) Port C bit set/reset control word

n g PORT C Lower (incl. BIT 3 )= OUT

(a) mode-set control word

a a BIT SET/ RESET WORD

(b) Port C bit set/reset control word to set bit 3

F PC3 INTR 0 = OUTPUT

ACK returns the OBF to logic 1. e rs

Fa PC4 DS (Data Strobe)

8255A connected to a parallel printer interface

(b) Capacitive (D. Hall Fig 9-18)

Flowchart for procedure (D. Hall)

(c) 5 by 7 dot matrix

have this feature. O E

Note : This system address is circuit-dependent.

D o then most significant byte

D o ; R/W LSB only

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