Quantization Effects in Digital Filter
Rupinder Kaur
RB6803A02
10807906
LOVELY PROFESSIONAL UNIVERSITY
Abstract- The rapid development of integrated
circuit technology led to the development of very
powerful digital machines able to perform a very
high number of computations in a very short
period of time. In addition, digital machines are
flexible, reliable, reproducible, and relatively
cheap. As a consequence, several signal
processing tasks originally performed in the
analog domain have been implemented in the
digital domain. A digital filter is one of the basic
building blocks in digital signal processing
systems. Digital filtering consists of mapping a
discrete-time sequence into another discrete-time
sequence that highlights the desired information
while reducing the importance of the undesired
information. The term paper includes a short
overview of digital filter (what actually it is, its
types) and a brief overview of Quantization effects
in it.
Keywords-Digital, Filter, Quantization, Error
1. Introduction
In signal processing, the function of a filter is to
remove unwanted parts of the signal, such as
random noise, or to extract useful parts of the
signal, such as the components lying within a
certain frequency range. The following block
diagram illustrates the basic idea.
Digital filtering consists of mapping a discrete-time
sequence into another discrete-time sequence that
highlights the desired information while reducing
the importance of the undesired information. To
make it clearer let us take an example of a discrete-
time signal shown as
follows in fig:
In a digital filter, the
input signal x (n) is a
sequence of numbers
indexed by the integer
n that can assume only
a finite number of
amplitude values. Such a sequence might originate
from a continuous-time signal x (t) by periodically
sampling it at the time instants t = nT, where T is
the sampling interval. The output sequence y(n)
arises by applying x(n) to the input of the digital
filter, with the relationship between x(n) and y(n)
represented by the operator F as:
y (n) = F[x (n)]
Defining the z transform of the sequence x (n) is
written as:
X (z) =∑n= -∞∞ x (n) z-n
The transfer function of a digital filter is the ratio of
the z transform of the output sequence to the z-
transform of the input signal: H (z) = Y (z)/ X (z)
Digital filters are of two types on the basis of
impulse response-FIR & IIR. FIR & IIR Digital
filters are briefly discussed below. Digital filters
are present in various digital signal processing
applications related to speech, audio, image, video,
and multi-rate processing systems as well as in
communication systems, CD players, digital radio,
television, and control systems. Digital filters can
have either fixed or adaptive coefficients
2. FIR filter-
It stands for finite impulse response filter. It is also
called non recursive filter. In this filter, output
depends on present and previous input.
For example- y (n) =2x (n) +1/2x (n-1) +3x (n-2)
FIR filters can be designed to have a linear phase.
A linear phase is a desirable feature in a number of
signal processing applications (e.g., image
processing). FIR filters can be designed by using
optimization packages. The main drawback is that
to satisfy demanding magnitude specifications, the
FIR filter requires a relatively high number of
multiplications, additions, and storage elements.
These facts make FIR filters potentially more
expensive than IIR filters (discussed below)in
applications where the number of arithmetic
operations or numbers of storage elements are
expensive or limited. However, FIR filters are
widely used because they are suitable for designing
linear phase filters. An FIR filter has a linear phase
if and only if its impulse response is symmetric or No. Of delays=4
anti-symmetric.
3. IIR filter- Adders=4
An IIR filter is one whose impulse response
Multipliers=5
(theoretically) continues for ever i.e. infinite
impulse response. It is also called recursive filter. We can get Direct form 2 realisation from direct
Here, output depends on present input, previous form 1 realisation simply by interchanging the two
input and previous output. filters and then merge it.
For instance- y (n) =2y (n-1) +3y (n-2)-2x (n)-1/2x
(n-1)

4. Digital filter realizations-

Digital filters use three basic types of operations:
• Delay: Used to store previous samples of the
input and output signals, besides internal states of
the filter
• Multiplier: Used to implement multiplication
operations of a particular digital filter structure and
also used to implement divisions
• Adder: Used to implement additions and
subtractions of the digital filter
4.1. FIR Filter Realization-Let us Direct form 2 realization
take the same example i.e. y (n) =2x (n)
+1/2x (n-1) +3x (n-2) to understand the No. Of delays=2
FIR Filter realisation.
The following figure shows the direct-form non Adders=4
recursive structure for FIR filters. Here only Direct
form realization is possible. Multipliers=3
Adders=2
5. Quantization effects in Digital
Multipliers=3 Filters
Quantization errors in digital filters can be
No of delays=2 classified as:
Direct form • Round-off errors derived from internal
realisation signals that are quantized before or after
more down additions;
4.2.
4.2. • Deviations in the filter response due to
IIR filter Realization- To understand the IIR finite word length representation of
filter realisation and difference in FIR & multiplier coefficients; and
IIR filters,
• Errors due to representation of the input
let us take an example-- y (n) =2y (n-1) +3y (n-2)-
signal with a set of discrete levels.
2x (n)-1/2x (n-1).Here Direct form 1 & direct form
A general, digital filter structure with quantizers
2, two realisations are possible that are shown :
before delay elements can be represented as in
following fig. with the quantizers implementing
rounding for the granular quantization and
saturation arithmetic for the overflow nonlinearity.
The criterion to choose a digital filter structure for
a given application entails evaluating known
structures with respect to the effects of finite word
length arithmetic and choosing the most suitable
one.

This is the case of Direct form 1 Realisation.

Here,
 noise source e (n) as shown in Figure A.
For product quantization performed by
rounding and for signal levels throughout
the filter much larger than the quantization
step q = 2-b, it can be shown that the power
spectral density of the noise source ei(n) is
given by:
Pei(z)=q2/12=2-2b/12
In this case, ei(n) represents a zero mean
white noise process. We can consider that
in practice, ei(n) and ek(n + l) are
statistically independent for any value of
n or l (for i != k). As a result, the
contributions of different noise sources
can be taken into consideration separately
by using the principle of superposition.
The power spectral density of the output
noise, in a fixed point digital-filter
implementation, is given by:
Py(z)=σe2 ∑i=1 k Gi(z) Gi(z-1)
Fig: Digital Filter Including Quantizers at the
Delay Inputs

5.1. Coefficient Quantization-

Approximations are known to generate Figure A
digital filter coefficients with high Model for the Noise generated after a
accuracy. After coefficient quantization, multiplication
the frequency response of the realized
digital filter will deviate from the ideal
response and eventually fail to meet the
prescribed specifications. Because the
sensitivity of the filter response to
coefficient quantization varies with the
structure, the development of low-
sensitivity digital filter realizations has
raised significant interest.
A common procedure is to design the
digital filter with infinite coefficient word
length satisfying tighter specifications
than required, to quantize the coefficients,
and to check if the prescribed
specifications are still met. Figure B: Digital Filter Including Scaling and
Noise Transfer Functions.
5.2. Quantization Noise- In fixed-
where Pei(ejw) = (σe)2, for all i, and each Gi(z) is a
point arithmetic, a number with a modulus
transfer function from multiplier output (gi(n)) to
less than one can be represented as
the output of the filter as shown in Figure B. The
follows: x = bob1 b2b3 . . . bb; where b0
word length, including sign, is b + 1 bit, and K is
is the sign bit and where bl b2b3 . . . bb
the number of multipliers of the filter.
represent the modulus using a binary code.
For digital filtering, the most widely used 5.3. Overflow Limit Cycle- Overflow
binary code is the two's complement nonlinearities influence the most
representation, where for positive numbers significant bits of the signal and cause
b0 = 0 and for negative numbers b0 = 1. severe distortion. An overflow can give
The fractionary part of the number, called rise to self-sustained, high-amplitude
x2 here is represented as: oscillations known as overflow limit
x2 = {x if b0 =0 & 2-|x| if b0 = 1 cycles. Digital filters, which are free of
The discussion here concentrates in the zero input limit cycles, are also free of
fixed-point implementation. A finite word overflow oscillations if the overflow
length multiplier can be modelled in terms nonlinearities are implemented with
of an ideal multiplier followed by a single saturation arithmetic, that is, by replacing
the number in overflow by a number with
the same sign and with maximum
magnitude that fits the available word
length. When there is an input signal
applied to a digital filter, overflow might
occur. As a result, input signal scaling is
required to reduce the probability of
overflow to an acceptable level. Ideally,
signal scaling should be applied to ensure
that the probability of overflow is the
same at each internal node of the digital
filter. This way, the signal-to-noise ratio is
maximized in fixed-point
implementations. In two's complement
arithmetic, the addition of more than two
numbers will be correct independently of
the order in which they are added even if
overflow occurs in a partial summation as
long as the overall sum is within the
available range to represent the numbers.
As a result, a simplified scaling technique
can be used where only the multiplier
inputs require scaling. To perform scaling,
a multiplier is used at the input of the filter
section as illustrated in Figure B. It is
possible to show that the signal at the
multiplier input is given by:
xi(n) =( 1/2Пj)∫ Xi(z)z n-1dz = 1/2П∫(limits
from zero to 2П) Fi(ejw)X(ejw)ejwndw ;where
c is the convergence region common to
Fi(z) and X(z).
The constant λ is usually calculated by
using Lp norm of the transfer function
from the filter input to the multiplier input
Fi(z), depending on the known properties
of the input signal. The Lp norm of Fi(z) is
defined as:
||Fi(ejw)||p = [1/2П]1/p
for each p > =1, such that ∫(limits from
zero to 2П) |Fi(e jw)|p dw <=∞. In general,
the following inequality is valid
|xi(n) | <=[ ||Fi||p||X||q,(1/p + 1/q=1) for
p, q = 1, 2 and ∞.
The scaling guarantees that the
magnitudes of multiplier inputs are
bounded by a number Mmax when |x(n)|<
=Mmax. Then, to ensure that all multiplier
inputs are bounded by Mmax we must
choose λ as follows:
Λ=1/(Max{||F1||p,.......... ||Fi||p,.......... ,||Fk||p}
Which means that:
||Fi (ejw)||p<=1, for ||X(ejw)||q<=Mmax ;The
K is the number of multipliers in the filter.
The norm p is usually chosen to be infinity
or 2. The L∞ norm is used for input signals
that have some dominating frequency
component, whereas the L2 norm is more
suitable for a random input signal. Scaling
coefficients can be implemented by simple
shift operations provided they satisfy the
overflow constraints. In case of modular
realizations, such as cascade or parallel
realizations of digital filters, optimum
scaling is accomplished by applying one
scaling multiplier per section. As an
illustration, we present the equation to
compute the scaling factor for the cascade
realization with direct-form second-order
sections:
Λi = 1/(||П (from j=1 to i-1) Hj(z)Fi(z)||
2
p ;Where Fi(z) = 1/(z +m1iz+m2i)
The noise power spectral density is
computed as
Py(z)= σe 2[3+(3/λ1 2)П(from i=1 to
m)Hi(z)Hi(z-1)+5∑(from j=2 to m)1/λj 2
П(from i=j to m) Hi(z)Hi(z-1)]
Whereas the output noise variance is given
by:
σe 2 = σe 2[3+3/λ1 2 ||П(from i = 1 to m)
Hi(ejw)||22 +5∑j=2m 1/λ1 2 ||П(from i = j to m)
Hi(ejw)||22]
As a design rule, the pairing of poles and
zeros is performed as explained here:
poles closer to the unit circle pair with
closer zeros to themselves, such that ||H
i(z)||p is minimized for p = 2 or p =∞
For ordering, we define the following:
Pi=||Hi(z)||∞ / ||Hi(z)||2
For L2 scaling, we order the section such
that Pi is decreasing. For L∞ scaling, Pi
should be increasing.
5.4. Granularity Limit Cycles-The
quantization noise signals become highly
correlated from sample to sample and
from source to source when signal levels
in a digital filter become constant or very
low, at least for short periods of time. This
correlation can cause autonomous
oscillations called granularity limit cycles.
In recursive digital filters implemented
with rounding, magnitude truncation, 4
and other types of quantization, limit
cycles oscillations might occur.
In many applications, the presence of limit
cycles can be harmful. Therefore, it is
desirable to eliminate limit cycles or to
keep their amplitude bounds low.
If magnitude truncation is used to quantize
particular signals in some filter structures,
it can be shown that it is possible to
eliminate zero-input limit cycles. As a
consequence, these digital filters are free
of overflow limit cycles when overflow
nonlinearities, such as saturation
arithmetic, are used.
In general, the referred methodology can
be applied to the following class of
structures:
• State-space structures: Cascade
and parallel realization of
 second-order state-space
structures includes design
constraints to control nonlinear
oscillations.
• Wave digital filters: These filters
emulate doubly terminated
lossless filters and have inherent
stability under Linear conditions
as well as in the nonlinear case
where the signals are subjected to
quantization.
• Lattice realization: Modular
structures allowing easy limit
cycles elimination.
6. Real-Time Implementation of
Digital Filters
There are many distinct means to implement a
digital filter. The detailed description of these
implementation methods is beyond the scope of
this term paper.
The most straightforward way to implement digital
filters relies on general purpose computers by
programming their central processing units (CPUs)
to execute the operations related to a particular
digital filter structure. This type of implementation
is very flexible because it consists of writing
software, allowing fast prototyping and testing.
This solution, however, might not be acceptable in
applications requiring high-processing speed, fast
data input/output interfaces, or large-scale
production.
Efficient software implementations of digital filters
are usually based on special-purpose CPUs known
as Digital Signal Processors (DSPs). These
processors are capable of implementing a sum of
product operations, also referred to as multiply-
and-accumulate (MAC) operations, in a very
efficient manner.
Another implementation alternative is to employ
programmable logic devices (PLD) that include a
large number of logic functions on a single chip.
An advanced version of PLD is the field-
programmable gate array (FPGA). An FPGA is an
array of logic macro-cells that are interconnected
through a number of communication channels
configured in horizontal and vertical directions.
The FPGAs allow the system designer to configure
very complex digital logic that can implement
digital signal processing tasks at low cost with
reduced power consumption. Usually, high-level
software tools are available for the design of digital
systems using FPGAs.
Special purpose hardware is also possible for
implementing a digital filter. Hardware
implementations consist of designing and possibly
integrating a digital circuit with logical gates to
perform the basic operating blocks inherent to any
digital filter structure, namely multiplications,
additions, and storage elements. Multiplications
and additions can be implemented using bit-serial
or bit-parallel architectures. In general, hardware
implementations of digital filters are less flexible
than software (CPU-based) implementations.
Special purpose hardware, however, is usually
necessary when high cost of development is offset
by a large production and a DSP-based solution is
too expensive or is incapable of meeting sampling
frequency specifications.
Consider a heuristic related to the computational
complexity of digital filters in a full custom design.
The following figure shows an intuitive plot of
complexity as a function of filter order for all
digital filter implementations meant to satisfy a
given set of specifications. The complexity of a
digital filter is measured in terms of number of bits
used in the coefficients and number of multiplier
operations’.
Figure: Complexity of Digital filter
For a prescribed set of frequency specifications and
a particular filter structure, a certain order N0 may
be capable of meeting the specifications with
infinite precision. For filters with an order lower
than N0, it is not possible to meet the prescribed
specifications. Infinite precision is translated as
very high complexity because an infinite number of
bits is required. If higher order is used, the number
of bits necessary for multiplier coefficients may be
reduced, implying lower complexity. An order N1
(in figure above) is the order of the implementation
with the lowest possible complexity. Orders higher
than N 1will necessarily imply higher complexity.
The heuristic introduced here, when applied to the
case of FIR filter designs using direct form
realizations, leads to complexity curves that are
very flat around their minimum point, indicating
that almost minimum complexity can be achieved
for a wide range of values for the filter order. On
the other hand, for IIR filters, the complexity curve
is rather sharp, implying that a more careful choice
for the filter order should be made.
7. Advantages & disadvantages of
digital filter over analog filter
7.1. Advantages- The advantages are
as follows:
• A digital filter is programmable, i.e.
its operation is determined by a
program stored in the processor's
memory. This means the digital filter
can easily be changed without
affecting the circuitry (hardware). An
analog filter can only be changed by
redesigning the filter circuit.
• Digital filters are easily designed,
tested and implemented on a general-
purpose computer or workstation.
• The characteristics of analog filter
circuits (particularly those containing
active components) are subject to drift
and are dependent on temperature.
Digital filters do not suffer from these
problems, and so are
extremely stable with respect both to
time and temperature.
• Unlike their analog counterparts,
digital filters can handle low
frequency signals accurately. As the
speed of DSP technology continues to
increase, digital filters are being
applied to high frequency signals in
the RF (radio frequency) domain,
which in the past was the exclusive
preserve of analog technology.
• Digital filters are very much
more versatile in their ability to
process signals in a variety of ways;
this includes the ability of some types
of digital filter to adapt to changes in
the characteristics of the signal.
7.2. Disadvantages- The
disadvantages are as follows:
• Long design and development times-1) the
design and development times for digital
filters, especially hardware development,
can be much longer than for analog filter.
2) However, once developed the hardware
and / or software can be used for other
filtering or DSP tasks with little or no
modifications.
3) Good computer aided design (CAD)
support can make the design of digital
filters an enjoyable task
• Speed Limitation- 1) The maximum
bandwidth of signals that digital filters can
handle, in real time, is much lower than
for analog filters
2) In real-time situations, the analog-digital-
analog conversion processes introduce a
speed constraint on the digital filter
performance. The conversion time of the
ADC and the settling time of the DAC
limit the highest frequency that can be
processed
3) Further, the speed of operation of a digital
filter depends on the speed of the digital
processor used and on the number of
arithmetic operations that must be
performed for the filtering algorithm,
which increases as the filter response is
made tighter
• Finite Word length Effects- Digital filters
are subject to ADC noise resulting from
quantizing a continuous signal, and to
round-off noise incurred during
computation.
8. Application of Digital filter-
Traditionally, most digital filter applications
have been limited to audio and high-end image
processing. With advances in process
technologies and digital signal processing
methodologies, digital filters are now cost-
effective in the IF range and in almost all video
markets. Digital filters are commonly used for
audio frequencies for two reasons. First, digital
filters for audio are superior in price and
performance to the analog alternative. Second,
audio Analog-to-Digital Converters (A/Ds)
and Digital-to- Analog Converters (DACs) can
be manufactured with high accuracy and are
available at low cost. Thus, the combined cost
of filtering and conversion is low. The cost
trades are much more difficult in the 1MHz to
100MHz signal range, such as the IF ranges of
many radio receivers. While digital signal
processing technology can now produce cost
effective digital filters for IF, the cost or even
the availability of data conversion products are
limiting factors. Many IF digital filtering
applications are band-limiting and decimating.
In these cases the design engineer must not
only know digital filters, but also understand
the effects of narrow-band-filtering
processing-gain on A/D requirements.
Additionally, power dissipation must be
considered. Currently, digital IF filter solutions
are excluded from low power applications such
as personal communication devices. In dealt with by placing a three-time sample
contrast, audio frequency digital filters are rate expander in front of the DDC.
essential. One of its applications in detail is as The HSP50016 and HSP43216 Data
follows: Sheets provide greater detail.
• IF Processing- Intersil’s HSP43216 Half
band Filter IC (Figure C) can perform a
quadrature split on a real signal. In this
example, the input signal undergoes anti-
alias filtering and is digitized and passed
to the Halfband Filter IC. The quadrature
fS/4 local oscillator (LO) and mixer
circuits on the IC center the upper
sideband of the real signal spectrum at
DC.
The Halfband Filter itself operates on the
resultant complex signal to filter out the
lower sideband, forming a quadrature
signal (a characteristic of which is a
single-sided spectrum). Other circuits in
the IC then decimate the real and
imaginary output by two to eliminate the
unused spectral region.
To cite a more specific application, IF
processing can be implemented in a
cellular base station using the HSP50016
Digital Down Converter (DDC) and two
HSP43124 Serial I/O Filters (Figure D). In Figure C: REAL TO QUADRATURE
this example a 4MHz band of the GSM CONVERSION USING THE HSP43216
spectrum has already been mixed to a near HALFBAND FILTER
baseband IF, has been appropriately anti-
alias filtered, and digitized by an A/D.
The spectral plot makes the point that
aliasing may take place as long as it does
not encroach on the band of interest.
Because this is a channelizing application,
there is a Signal to- Noise Ratio (SNR)
processing gain of 3dB for every factor of
2 that the noise bandwidth is reduced. In
this example, the processing gain is
approximately 17dB. As a result, the SNR
of the A/D can be 17dB lower than the
desired output SNR.
The A/D’s Spurious Free Dynamic Range
(SFDR), however, must be equal to the
desired output SFDR since there is no gain
effect on in-band frequency spurs.
The DDC is a single-chip quadrature
down-converter and two stage filter. It is
used to tune the channel of interest to
baseband, and to perform narrow-band
filtering and decimation.
Figure D: GSM BASE STATION EXAMPLE
The Serial I/O Filters are used to apply
the GSM filter shape to the output
quadrature data stream. This process 9. Conclusion-
includes decimation by two to modify the As this term paper include the quick view about the
output sampling rate to that required by Digital Filters and a brief overview of the
the GSM Specification. quantization effects in digital filter. From all
This requirement forces the DDC to mentioned above, it is clear that these filters are
decimate at a rate below its minimum of very important building blocks for signal
64 in quadrature-output mode. This is processing systems implemented in discrete-time
domain. In particular, the widely available digital
technology allows the implementation of very fast
and sophisticated filters in a cheap and reliable
manner. As a result, the digital filers are found in
numerous commercial products such as audio
systems, biomedical equipment, digital radio, and
TV just to mention a few. Quantization effects in
digital filters tell us about the quantisation errors,
noise, and limit overflow cycles which plays very
important role in the real time implementation of
Digital filters.
10. References-
• http://en.wikipedia.org/wiki/Digital_filter
• http://www.scribd.com/doc/30426027/Dig
ital-Filters
• Jackson, L.B. (1996). Digital filters and
signal processing. (3rd ed.). Boston, MA:
Kluwer Academic
• Antoniou, A. (1993). Digital filters:
Analysis, design, and applications.
(2nd). New York: McGraw-Hill.
• http://en.scientificcommons.org/19830423
• http://www.dsptutor.freeuk.com/dfilt1.htm