80486

80486DX is the first CPU with an on chip floating-point unit. For

fast execution of complex instructions of xxx86 family, the 80486 has
introduced five stage pipelines. Two out of the five stages are used for
decoding the complex instructions of xxx86 architecture. This feature,
which has been, used widely in RISC architectures results in very fast
instruction execution. The 80486 is also the first amongst the xxx86
processor to have an on-chip cache. This 8Kbytes cache is a unified
data and code cache and acts on physical addresses.

Architecture of 80486
The 32-bit pipelined architecture of Intel’s 80486 is shown in
Figure 5.8. The internal architecture of 80486 can be broadly divided
into three sections, namely bus interface unit, execution and control unit
and floating point unit.
The bus interface unit is mainly responsible for coordinating all
the bus activities. The address driver interfaces the internal 32-bit
address output of cache unit with the system bus. The data bus
transreceivers interface the internal 32-bit data bus with the system bus.
The 48X80 write data buffer is a queue of four 80-bit registers, which
hold the 80-bit data to be written to the memory. The bus control and
request sequences handles the signals like ADS#, W/R#, D/C#, M/IO#,
PCD, PWT, RDY#, LOCK#, PLOCK#, BOFF#, A20M#, BREQ, HOLD,
HLDA, RESET, INTR, NMI, FERR# and IGNNE# which basically control
the bus access and operations.
The burst control signal BRDY# informs the processor that the
burst is read. The BLAST# output indicates to the external system that
the previous burst cycle is over. The bus size control signals BS16#
and BS8# are used for dynamic bus sizing. The cache control signals
KEN#, FLUSH, AHOLD and EADS# control and maintain the in
coordination with the cache control unit. The parity generation and
control unit maintain the parity and carry out the related checks during
the processor operation. The boundary scan control unit, that is built in
50MHZ and advanced versions only, subject the processor operation to
boundary scan tests to ensure the correct operation of various
components of the circuit on the mother board, provided the TCK input
is not tied high.
The prefetcher unit fetches the codes from the memory ahead of
execution time and arranges them in a 32-byte code queue. The
instruction decoder gets the code from the code queue and then
decodes it sequentially. The output of the decoder drives the control
unit to derive the control signals required for the execution of the
decoded instructions. But prior to execution, the protection unit
checks, if there is any violation of protection norms. If any protection
norm is violated, an appropriate exception is generated. The control
ROM store a microprogram for deriving control signals for execution of
different instructions. The registers bank and ALU are used for their
conventional usages. The barrel shifter helps in implementing the shift
and rotate algorithms. The segmentation unit, descriptor registers,
paging unit, translation look aside buffer and limit and attribute PLA
work together to manage the virtual memory of the system and provide
adequate protection to the codes or data in the physical memory. The
floating-point unit with its register bank communicates with the bus
interface unit under the control of memory management unit, via its 64-
bit internal data bus. The floating-point unit is responsible for carrying
out mathematical data processing at a higher speed as compared to the
ALU, with its built in floating-point algorithms.

Signal Descriptions of 80486

Timing Sigel CLK : This input provides the basic system timing for the
operation of 80486.
Address Bus : A31- A2 These are the address lines of the
microprocessor, and are used for selecting memory I/O devices.
However, for memory/IO addressing we also need another set of signals
known as byte enable signals BE0 – BE3. These active-low byte enable
signals (BE0# - BE3#) indicate which byte of the 32-bit data bus is active
during the read or write cycle.
Data Bus : D0-D31 This is bi-directional data bus with D0 as the least
and D31 as the most significant data bit.
Data Parity Group: The pins of this group of signals are extremely
important, because they are used to detect the parity during the memory
read and write operations.
DP0-Dp3: These four data parity input/output pins are used for
representing the individual parity of 4bytes (32bits) of the data bus.
M/IO#: This output pin differentiates between memory and I/O
operations.
D/C#: This output pin differentiates between data/control operations.
W/R#: This output pin differentiates between read and write bus cycle.
PLOCK#: This pseudo lock pin indicates that the current operation may
require more than one bus cycle for its completion. The bus is to be
locked until then.
LOCK# : This output pin indicates that the current bus cycle is locked.
ADS# : The address status output pin indicates that a valid bus cycle
definition and addresses are currently available on the corresponding
pins.
RDY# : This input pin acts as a ready signal for the current non-burst
cycle.
BRDY# & BLAST# : refer Architecture of 80486
RESET : This input pin reset the processor, if its goes high
INTR : This is a maskable interrupt input that is controlled by the IF in
the flag register
NMI : This is a non-maskable interrupt input, of type 2.
BREQ : This active high output indicates that the 80486 has generated a
bus request.
HOLD : This pin acts a a local bus hold input, to be activated by another
bus master like DMA controller, to enable to gain the control of the
system bus.
HLDA : This is an output that acknowledges the receipt of a valid HOLD
request.
BOFF#: When a CPU requests the access of the bus, and if the bus is
granted to it, then the current bus master which is currently in charge of
the bus will be asked to back off or release the bus.
AHOLD: The address holds request input pin enables other bus masters
to use the 80486 system bus during a cache invalidation cycle.
EADS#: The external address input signal indicates that a valid address
for external bus cycle is available on the address bus.
KEN# : The cache enable input pin is used to determine whether the
current cycle is cacheable or not.
FLUSH#: The cache flush input, if activated, clears the cache contents
and validity bits.
PCD, PWT : The page cache disables and page write-through output
pins reflect the status of the corresponding bits in page table or page
directory entry.
FPU: Error Group
FERR : The FERR output pin is activated if the floating point unit reports
any error.
IGNNE: If ignore numeric processor extension input pin is activated, the
80486 ignores the numeric processor errors and continues executing
non-control floating-point instructions.
BS8# and BS16# : The bus size-8 and bus size-16 inputs are used for the
dynamic bus sizing feature of 80486. These two pins enable 80486 to be
interfaced with 8-bit or 16-bit devices though the CPU has a bus width of
32-bits.
A20M3 : If this input pin is activated, the 80486 masks the physical
address line A20 before carrying out any memory or cache cycle.
Test Access Port Group: This is a unique facility available in 80486,
which enables it to check the fault conditions of the other on-board
components. This is invoked using the JTAG instruction.
TCK : The test clock input provides the basic clock required by the
boundary scan feature.
TDI : The test data input is the serial input used to shift the JTAG
instructions and data into the component.
TDO : The test data output is the serial output pin used to shift the JTAG
instruction and data out of the component under test. The TDI and TDO
are sampled or driven during the SHIFT-IR and SHIFT-DR TAP controller
states.
TMS: The test mode select input is decoded by the JTAG TAP ( tap
access port) to select the operation of this test logic.
Vcc : In all 24 pins are allocated for the power supply.
Vss : These act as return lines for the power supply. In all 28 pins are
allocated for the power supply return lines.
N/C : No connection pins are expected to be left open while connecting
the 80486 in the circuit.

Addressing Modes: The addressing modes supported by 80486 are

exactly the same as those of 80386.
Data types of 80486: The 80486 CPU supports a wide range of data types
including the floating-point data types, as listed briefly.
1. Signed/unsigned data type : 8-bit, 16-bit, 32-bit signed and
unsigned integers are supported by 80486 while the FPU supports
16-bit, 32-bit and 64-bit signed data.
2. Floating Point data types: Single precision, double precision,
extended precision real data are supported only by the FPU.
3. BCD Data types : Packed and unpacked BCD data types. The CPU
supports 8-bit packed and unpacked data types. The FPU
supports 80-bit packed BCD data types.
4. String Data Types : String of bits, bytes, words and double words
are supported by the CPU. Each of the strings may contain upto
4Gbytes.
5. ASCII Data Types : The ASCII representation of the characters are
supported by 80486.
6. Pointer Data Types: 48-bit pointers containg 32-bit offset at the
least significant bits and 16-bit selector at the most significant
bits are supported by the CPU. Also 32-bit pointers containing
32bit offsets are supported by the CPU.
7. Little Endian and Big Endian data types: The 8086 family uses
Little Endian data format normally. This means for a data of size
bigger than one byte, the least significant byte is stored at the
lowest memory address while the most significant byte is stored
at the highest memory address. A complete data is referred to by
the lowest memory address, i.e. the address of the least
significant byte. The Big Endian format allows the storage of data
in the exactly opposite manner, i.e. the MSB is stored at the
lowest memory address, while the LSB is stored at highest
memory address.