DI2CSB

I2C Bus Interface Slave - Base version

ver 2.00
● Support for reads, writes, burst reads,
OVERVIEW burst writes, and repeated start
I2C is a two-wire, bi-directional serial bus that
provides a simple and efficient method of ● 7-bit addressing
data transmission over a short distance be- ● No programming required
tween many devices. The DI2CSB provides
an interface between a passive target device ● Simple interface allows easy connection
e.g. memory, LCD display, pressure sensors to target device e.g. memory, LCD dis-
etc. and an I2C bus. It can works as a slave play, pressure sensors etc.
receiver or transmitter depending on working ● Fully synthesizable
mode determined by a master device. Very
simple interface, composed with the read, ● Static synchronous design with positive
write and data signals, allows easy connec- edge clocking and synchronous reset
tion to the target devices. The core doesn’t ● No internal tri-states
required programming and is ready to work
after power up/reset. The read, write, burst ● Scan test ready
read, burst write and repeated start transmis-
sions are automatically recognized by the
APPLICATIONS
core. The core incorporates all features re- ● Embedded microprocessor boards
quired by I2C specification. The DI2CSB sup- ● Consumer and professional audio/video
ports the following transmission modes:
Standard, Fast and High Speed. ● Home and automotive radio
● Low-power applications
KEY FEATURES
● Communication systems
● Conforms to v.3.0 of the I2C specification
● Cost-effective reliable automotive sys-
● Slave operation
tems
○ Slave transmitter
○ Slave receiver DELIVERABLES
♦ Source code:
● Supports 3 transmission speed modes
◊ VHDL Source Code or/and
○ Standard (up to 100 kb/s) ◊ VERILOG Source Code or/and
○ Fast (up to 400 kb/s) ◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
○ Fast Plus (up to 1 Mb/s) ment
○ High Speed (up to 3,4 Mb/s) ◊ Active-HDL automatic simulation mac-
ros
● Allows operation from a wide range of
◊ ModelSim automatic simulation macros
input clock frequencies
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Copyright 1999-2009 DCD – Digital Core Design. All Rights Reserved.

 ◊ Tests with reference responses
♦ Technical documentation
SYMBOL
◊ Installation notes datai(7:0) datao(7:0)
◊ HDL core specification
◊ Datasheet rd
♦ Synthesis scripts wr
♦ Example application scli
♦ Technical support sdai sdao
◊ IP Core implementation support clk
◊ 3 months maintenance rst
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
PINS DESCRIPTION
PIN TYPE DESCRIPTION
LICENSING clk input Global clock

Comprehensible and clearly defined licensing rst input Global reset

methods without royalty per chip fees make datai(7:0) input Data bus from target device
using of IP Core easy and simply. scli input I2C bus clock line (input)
Single Site license option is dedicated for sdai input I2C bus data line (input)
small and middle sized companies making its datao(7:0) output Data bus to target device
business in one place. wr output Write strobe for target device
Multi Sites license option is dedicated for cor- rd output Read strobe for target device
porate customers making its business in sev- sdao output I2C bus data line (output)
eral places. Licensed product can be used in
selected branches of corporate.
In all cases number of IP Core instantiations BLOCK DIAGRAM
within a project, and number of manufactured Figure below shows the DI2CSB IP Core
chips are unlimited. The license is royalty per block diagram.
chip free. There is no time of use restrictions.
Target device Interface – Performs the inter-
There are two formats of delivered IP Core face functions between DI2CSB internal
blocks and target device. Allows easy con-
● VHDL, Verilog RTL synthesizable source nection of the core to a passive devices e.g.
code called HDL Source memory, LCD display, pressure sensors, I/O
● FPGA EDIF/NGO/NGD/QXP/VQM called devices etc..
Netlist

datai(7:0)
Receive
Data Input sdai
datao(7:0) Filter
Shift
Target device Register
we Interface Output sdao
rd Register
Send
Data Own
address
detection

Control
Logic

rst Synchronization Input

scli
clk Logic Filter

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are trademarks of their respective owners. http://www.dcd.pl

Copyright 1999-2009 DCD – Digital Core Design. All Rights Reserved.

Control Logic – Manages execution of all PERFORMANCE
commands sent via interface. Synchronizes
The following table gives a survey about the
internal data flow.
Core area and performance in ASIC devices
Shift Register – Controls SDA line, performs (all key features have been included):
data and address shifts during the data
transmission and reception. Technology Optimization Gates Fmax
0.25 typical area 400 220 MHz
Input Filter – Performs spike filtering. 0.25 typical speed 800 640 MHz
Synchronization Logic – Synchronizes data Core performance in ASIC devices
and address shifts during the data transmis-
sion and reception. SCLI spikes are filtered
by this unit.

The main features of each Digital Core Design I2C compliant cores have been summarized in table
below. It gives a briefly member characterization helping user to select the most suitable IP Core
for its application.

High-speed mode
10-bit addressing

User defined tim-

Master operation

Interrupt genera-

Clock synchroni-
I2C specification

7-bit addressing

Fast Plus mode

Slave operation

Standard mode
Passive device
CPU interface

Spike filtering
Fast mode
Design
Arbitration
interface
version

zation
tion

ing
DI2CM 3.0 - -
DI2CS 3.0 - - - -
DI2CSB 3.0 - - - - - - -
DI2CMS 3.0 -
I2C cores summary table

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are trademarks of their respective owners. http://www.dcd.pl

Copyright 1999-2009 DCD – Digital Core Design. All Rights Reserved.

 CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
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fax : +48 32 282 74 37
Distributors:
Please check hhttp://www.dcd.pl/apartn.php
ttp://www.dcd.pl/apartn.php

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

Copyright 1999-2009 DCD – Digital Core Design. All Rights Reserved.