Digital Design with VHDL

Project Assignments for supplementing Course Work

General Instructions:
a. Each student is required to work on his / her own.
b. At the time of submission, each student should submit a detailed report containing
problem analysis, architectural design, VHDL code (source code), detailed simulation
results, RTL schematic, technology schematic of FPGA and analytical remarks.
c. The total marks of 20 will be awarded as follow: 10 for correctness of logic, 5 for report
writing and 5 for timeliness of submission.
d. Reports are to be submitted on or before April 24, 2011. All delayed submissions are
subjected to prosecution and penalization accordingly.
e. Each problem may be assigned to a maximum of 5 students.
f. Each student is required to work separately. Copying others work in any form is liable to
be punished and will be marked zero.

1. Model a fault tolerant superscalar multi-core RISC processor architecture in VHDL that
can perform vector processing on 2-D arrays of data. The processor can be used for
image processing applications. The processor should have dedicated blocks for image
compression using JPEG compression standards. The memory accessed by the processor
is a two dimensional memory with memory operations limited to loads and stores only.
Realize the processor using FPGA.

2. Model using VHDL a self-adaptive fault tolerant neural network trained with back-
propagation algorithm and weight adjustment using gradient descent rule. The neural
network should be capable of online learning with adjustments of weights within hard
real time deadlines. Realize the computing unit using FPGA.

3. Model a fuzzy processor using VHDL, based on pipelined parallel hybrid architecture.
There should be pipelining of detection, antecedent and rule units. The processor should
be capable of producing an output crisp decision for the input being provided within hard
real time deadlines. Realize the processor using FPGA.

4. Model a superscalar floating point processor using VHDL that can operate on single
precision floating point numbers in the IEEE 754 floating point format. The processor is
capable of performing basic operations on floating point numbers such as addition,
subtraction, multiplication and division. Realize the processor using FPGA.

5. Model a Huffman codec in VHDL. The codec can accept 8 bit data and depending on the
value, the result is transferred to appropriate memory location. The storage and retrieval
should be optimized for minimum latency access. Realize the codec using FPGA.

6. Model a 2Kx16 content addressable memory block using VHDL. The maximum length
of the key register is 8 bits. The content addressable memory block should have the
facility of masking some of the key bits used for accessing a memory location. Realize
the CAM using FPGA.