1

8051 MICROCONTROLLER

Block diagram of 8051

The basic architecture consists of the following features:

· An eight bit ALU

· 32 discrete I/O pins (4 groups of 8) which can be individually accessed

· Two 16 bit timer/counters

· Full duplex UART

· 6 interrupt sources with 2 priority levels

· 128 bytes of on board RAM

· Separate 64K byte address spaces for DATA and CODE memory
MES: Unit 1 Bhoopesh Kumawat
 2

Pin Diagram

8051 processor cycle: One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve
oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the
interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by
dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles
required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock,
you can compute the number of instructions per second by dividing this value by 12. This gives an
instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time
taken by each instruction cycle (1.085 microseconds).

Memory Organization:

Types of Memory

1. Code Memory

• Code memory is the memory that holds the actual 8051 program that is to be run.

• This memory is limited to 64K.

• Code memory may be found on-chip, either burned into the microcontroller as ROM or EPROM.
Code may also be stored completely off-chip in an external ROM or, more commonly, an external
EPROM.
MES: Unit 1 Bhoopesh Kumawat
 3

• When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k, or 16k.

• Since code memory is restricted to 64K, 8051 programs are limited to 64K.

2. External RAM

• External RAM is any random access memory which is found off-chip.

• Since the memory is off-chip it is not as flexible in terms of accessing, and is also slower. For
example, to increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction
cycle. To increment a 1-byte value stored in External RAM requires 4 instructions and 7 instruction
cycles. In this case, external memory is 7 times slower.

• While Internal RAM is limited to 128 bytes the 8051 supports External RAM up to 64K.

3. On-Chip Memory

• On-chip memory is really one of two (SFR) memories.

• 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the 8051 so it is
the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying
its contents.

• Internal RAM is volatile, so when the 8051 is reset this memory is cleared.
MES: Unit 1 Bhoopesh Kumawat
 4

• The 128 bytes of internal ram is subdivided as shown on the memory map.

• The first 8 bytes (00h- 07h) are "register bank 0". By manipulating certain SFRs, a program may
choose to use register banks 1, 2, or 3. These alternative register banks are located in internal RAM
in addresses 08h through 1Fh.

• Bit Memory resides in internal RAM, from addresses 20h through 2Fh.

• The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user
variables that need to be accessed frequently or at high-speed. This area is also utilized by the
microcontroller as a storage area for the operating stack. This fact severely limits the 8051’s stack
since, the area reserved for the stack is only 80 bytes--and usually it is less since this 80 bytes has to
be shared between the stack and user variables.

7F – 30 = 4F (0 1 0 0 1 1 1 1) => 79(Decimal) + 01 = 80 Bytes

Same as 1 à 10 = 10 numbers => 10(Max) – 1(Min) = 9 + 1

Register Banks

Register Bank 0 à 00H to 07H Register Bank 1 à 08H to 0FH

Register Bank 2 à 10H to 17H Register Bank 3 à 18H to 1FH

MES: Unit 1 Bhoopesh Kumawat

 5

• The 8051 uses 8 "R" registers numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7) which
are used in many of its instructions.

• These registers are generally used to assist in manipulating values and moving data from one
memory location to another.

• For example: ADD A,R4 : This instruction adds the contents stored in register R4 with Accumulator
and stores the result in Accumulator.

From the memory map, the register R4 is having an address 04H. So we can also write the same
instruction as: ADD A,04h : This instruction adds the value found in Internal RAM address 04h to the
value of the Accumulator, leaving the result in the Accumulator.

Note: But, the 8051 has four distinct register banks. When the 8051 is first booted up, register bank
0 (addresses 00h through 07h) is used by default. So, the program instructs the 8051 to use one of
the alternate register banks; i.e., register banks 1, 2, or 3. In this case, R4 will no longer be the same
as Internal RAM address 04h.

Tip for Programming: If you only use the first register bank (i.e. bank 0), you may use Internal RAM locations
08h through 1Fh for your own use. But if you plan to use register banks 1, 2, or 3, be very careful about
using addresses below 20h as you may end up overwriting the value of your "R" registers!

Bit Memory

• There are 128 bit variables available to the user, numbered 00h through 7Fh. The user may make
use of these variables with commands such as SETB and CLR.

• The 128 bit variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if we write
the value FFh to Internal RAM address 20h, we effectively set bits 00h through 07h.

• For example, if output lines P0.0 through P0.7 are all clear (0) and you want to turn on the P0.0
output line you may either execute: MOV P0,#01h || SETB 80h. Both these instructions
accomplish the same thing. However, using the SETB command will turn on the P0.0 line without
affecting the status of any of the other P0 output lines. The MOV command effectively turns off all
the other output lines which, in some cases, may not be acceptable.

MES: Unit 1 Bhoopesh Kumawat

 6

Tip for Programming: If your program does not use bit variables, you may use Internal RAM locations 20h
through 2Fh for your own use. But if you plan to use bit variables, be very careful about using addresses
from 20h through 2Fh because it may end up overwriting the value of your bits!

Special Function Register (SFR) Memory

• Special Function Registers (SFRs) are areas of memory that control specific functionality of the 8051
processor.

• For example, four SFRs permit access to the 8051’s 32 input/output lines. Another SFR allows a
program to read or write to the 8051’s serial port. Other SFRs allow the user to set the serial baud
rate, control and access timers, and configure the 8051’s interrupt system.

• For example, if you want to write the value "1" to Internal RAM location 50 hex you would execute
the instruction: MOV 50h,#01h Similarly, if you want to write the value "1" to the 8051’s serial port
you would write this value to the SBUF SFR, which has an SFR address of 99 Hex. Thus, to write the
value "1" to the serial port you would execute the instruction: MOV 99h,#01h

Special Function Registers (SFRs)

• P0, P1, P2 and P3 are I/O port SFRs.

• PCON, TCON, TMOD, SCON, IE, IP and PSW are Control SFRs.

• SP, DPL, DPH, TL0, TL1, TH0, TH1, SBUF, ACC and B are other SFRs.

MES: Unit 1 Bhoopesh Kumawat

 7

• SFRs which lie in first column of above memory map are bit-addressable i.e. can be accessed bitwise.

• In total, There are 21 SFRs. These SFRs are accessed as if they were normal Internal RAM. The only
difference is that Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the
address range of 80h through FFh.

• All other addresses in the SFR range (80h through FFh) are considered invalid. Writing to or reading
from these registers may produce undefined values or behavior.

SFR Descriptions

1. P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of this SFR
corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is
pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

Programming Tip: While the 8051 has four I/O port (P0, P1, P2, and P3), if your hardware uses
external RAM or external code memory (i.e., your program is stored in an external ROM or EPROM
chip or if you are using external RAM chips) you may not use P0 or P2. This is because the 8051 uses
ports P0 and P2 to address the external memory.

2. P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this SFR
corresponds to one of the pins on the microcontroller.

3. P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this SFR
corresponds to one of the pins on the microcontroller.

4. P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this SFR
corresponds to one of the pins on the microcontroller.

5. SP (Stack Pointer, Address 81h): This is the stack pointer of the microcontroller. This SFR indicates
where the next value to be taken from the stack will be read from in Internal RAM. If you push a
value onto the stack, the value will be written to the address of SP + 1. That is to say, if SP holds the
value 07h, a PUSH instruction will push the value onto the stack at address 08h. This SFR is modified
by all instructions which modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever
interrupts are provoked by the microcontroller.

Programming Tip: The SP SFR, on startup, is initialized to 07h. This means the stack will start at 08h
and start expanding upward in internal RAM. Since alternate register banks 1, 2, and 3 as well as the
MES: Unit 1 Bhoopesh Kumawat
 8

user bit variables occupy internal RAM from addresses 08h through 2Fh, it is necessary to initialize
SP in your program to some other value.

6. DPL/DPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and DPH work together to
represent a 16-bit value called the Data Pointer. The data pointer is used in operations regarding
external RAM and some instructions involving code memory. Since it is an unsigned two-byte
integer value, it can represent values from 0000h to FFFFh (0 through 65,535 decimal).

Programming Tip: DPTR is really DPH and DPL taken together as a 16-bit value. In reality, you almost
always have to deal with DPTR one byte at a time. For example, to push DPTR onto the stack you
must first push DPL and then DPH. You can't simply plush DPTR onto the stack. Additionally, there is
an instruction to "increment DPTR." When you execute this instruction, the two bytes are operated
upon as a 16-bit value. However, there is no instruction that decrements DPTR.

7. PSW (Program Status Word, Addresses D0h, Bit-Addressable): The Program Status Word is used to
store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR
contains the carry flag, the auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the
PSW register contains the register bank select flags which are used to select which of the "R"
register banks are currently selected.

Programming Tip: If you write an interrupt handler routine, it is a very good idea to always save the
PSW SFR on the stack and restore it when your interrupt is complete. Many 8051 instructions
modify the bits of PSW. If your interrupt routine does not guarantee that PSW is the same upon exit
as it was upon entry, your program is bound to behave rather erradically and unpredictably.

8. ACC (Accumulator, Addresses E0h, Bit-Addressable): The Accumulator is one of the most-used SFRs
on the 8051 since it is involved in so many instructions. The Accumulator resides as an SFR at E0h,
which means the instruction MOV A,#20h is really the same as MOV E0h,#20h. However, it is a good
idea to use the first method since it only requires two bytes whereas the second option requires
three bytes.

9. B (B Register, Addresses F0h, Bit-Addressable): The "B" register is used in two instructions: the
multiply and divide operations. The B register is also commonly used by programmers as an auxiliary
register to temporarily store values.

10. PCON (Power Control, Addresses 87h): The Power Control SFR is used to control the 8051's power
control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep"
MES: Unit 1 Bhoopesh Kumawat
 9

mode which requires much less power. These modes of operation are controlled through PCON.
Additionally, one of the bits in PCON is used to double the effective baud rate of the 8051's serial
port.

11. SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is used to configure
the behavior of the 8051's on-board serial port. This SFR controls the baud rate of the serial port,
whether the serial port is activated to receive data, and also contains flags that are set when a byte
is successfully sent or received.

Programming Tip: To use the 8051's on-board serial port, it is generally necessary to initialize the
following SFRs: SCON, TCON, and TMOD. This is because SCON controls the serial port. However, in
most cases the program will wish to use one of the timers to establish the serial port's baud rate. In
this case, it is necessary to configure timer 1 by initializing TCON and TMOD.

12. SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive data via the
on-board serial port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise,
any value which the 8051 receives via the serial port's RXD pin will be delivered to the user program
via SBUF. SBUF serves as the output port when written to and as an input port when read from.

13. TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is used to configure
and modify the way in which the 8051's two timers operate. This SFR controls whether each of the
two timers is running or stopped and contains a flag to indicate that each timer has overflowed.
Additionally, some non-timer related bits are located in the TCON SFR. These bits are used to
configure the way in which the external interrupts are activated and also contain the external
interrupt flags which are set when an external interrupt has occurred.

14. TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the mode of
operation of each of the two timers. Using this SFR your program may configure each timer to be a
16-bit timer, an 8-bit autoreload timer, a 13-bit timer, or two separate timers. Additionally, you may
configure the timers to only count when an external pin is activated or to count "events" that are
indicated on an external pin.

15. TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Bh): These two SFRs, taken together, represent timer
0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these
timers always count up. What is configurable is how and when they increment in value.

MES: Unit 1 Bhoopesh Kumawat

 10

16. TL1/TH1 (Timer 1 Low/High, Addresses 8Ch/8Dh): These two SFRs, taken together, represent timer
1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these
timers always count up. What is configurable is how and when they increment in value.

17. IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and disable specific
interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the
highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are
disabled regardless of whether an individual interrupt is enabled by setting a lower bit.

18. IP (Interrupt Priority, Addresses B8h, Bit-Addressable): The Interrupt Priority SFR is used to specify
the relative priority of each interrupt. On the 8051, an interrupt may either be of low (0) priority or
high (1) priority. An interrupt may only interrupt interrupts of lower priority.

8051 Register Set: Basic Registers

• Accumulator: Accumulator, as it’s name suggests, is used as a general register to accumulate the
results of a large number of instructions. It can hold an 8-bit (1-byte) value.

• "R" registers: The "R" registers are a set of eight registers that are named R0, R1, etc. up to and
including R7. These registers are used as auxillary or "helper" registers in many operations. The "R"
registers are also used to temporarily store values.

• "B" Register: The "B" register is very similar to the Accumulator in the sense that it may hold an 8-
bit (1-byte) value. The "B" register is only used by two 8051 instructions: MUL AB and DIV AB. Aside
from the MUL and DIV instructions, the "B" register is often used as yet another temporary storage
register much like a ninth "R" register.

• Data Pointer (DPTR): The Data Pointer (DPTR) is the 8051’s only user-accessable 16-bit (2-byte)
register. The Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as the name
suggests, is used to point to data. It is used by a number of commands which allow the 8051 to
access external memory. When the 8051 accesses external memory it will access external memory
at the address indicated by DPTR.

• Program Counter (PC): The Program Counter (PC) is a 2-byte address which tells the 8051 where the
next instruction to execute is found in memory. When the 8051 is initialized PC always starts at
0000h and is incremented each time an instruction is executed. It is important to note that PC isn’t
always incremented by one. Since some instructions require 2 or 3 bytes the PC will be incremented

MES: Unit 1 Bhoopesh Kumawat

 11

by 2 or 3 in these cases. The Program Counter is special in that there is no way to directly modify it’s
value. There is no way to read the value of PC.

• Stack Pointer (SP): The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-
byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack
should be taken from. When you push a value onto the stack, the 8051 first increments the value of
SP and then stores the value at the resulting memory location. When you pop a value off the stack,
the 8051 returns the value from the memory location indicated by SP, and then decrements the
value of SP. SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET,
and RETI.

8051 Addressing Modes

Definition: The CPU can access data in various way. The data could be in a register, or in memory, or to be
provided as an immediate data. The various way of accessing data are called addressing mode. The way by
which the address of the operand (source or destination operand) is specified in the instruction is known as
addressing mode.

8051 micro controller supports the following addressing modes.

1) Register addressing 3) Indirect addressing 5) Immediate addressing

2) Direct addressing 4) Register specific addressing 6) Index addressing mode

Register Addressing Mode

• In the register addressing mode the operands are in the registers.

• The register addressing modes occurs between register A and R0 to R7. The programmer can select
register bank by modifying bits 4 and 3 in the PSW.

For Example:

1.) MOVA, R0: Copy data from the register R0 to register A

2.) ADD A, R1: Add the content of R1 and A. Store the result in A

3.) ANL A, R2: AND each bit of A with the same bit of register R2.

MES: Unit 1 Bhoopesh Kumawat

 12

Direct Addressing Mode

• In direct addressing mode, the address of the operand is specified by an 8-bit address in the
instruction.

• Using this mode one can access internal data RAM and SFRs, directly. Internal RAM uses addresses
from 00H to 7FH to address each byte. The SFR addresses exist from 80H to FFH.

For Example:

1.) MOVA, 80H: Copy data from the port 0 to register A

2.) MOV 80H, A: Copy data from the register A to port 0

3.) MOV 0F0, 12H: Copy data from RAM location 12H to register B

4.) MOV 8CH, R7: Copy data from the resister R7 to timer 0 high byte

5.) MOV 5CH, A: Copy data from register A to RAM location 5CH

6.) MOV 0A8, 77H: Copy data from RAM location 77H to IE register

Indirect Addressing Mode

• In indirect addressing mode instruction specifies a register which holds address of an operand.

• In this mode, only registers R0 or R1 may be used to hold the address of one of the data location in
RAM from address 00H to FFH.

Note: The symbol used for indirect addressing is the "at" sign, which is printed as @. @Rp means
register R1 or R0 addressing internal RAM locations from 00H to FFH.

For Example:

1.) MOV A, @ R0: Copy contents of memory location, whose address is specified in R0 of selected bank
to accumulator.

2.) ADD A, @ R1: Add the contents of memory location, whose address is specified in R1 and
accumulator. Store the result in A.

3.) ANL A, @ R0: AND each bit of A with same bit of the contents of address contained in R0. Store
result in A.
MES: Unit 1 Bhoopesh Kumawat
 13

Register Specific Addressing Mode

• In the register specific addressing mode, the operand is specified by certain specific register such as
accumulator or DPTR.

For Example:

1.) SWAP A: SWAP nibbles within the accumulator.

2.) DAA: Decimal adjust accumulator.

3.) RRA: Rotate the contents of accumulator to the right.

Immediate Addressing Mode

• In immediate addressing mode the operand is specified within the instruction itself. In this "data" is
part of the instruction.

Note: The mnemonic for immediate data is the pound sign (#). '#' sign is used in the instruction to
indicate the "immediate" data.

For Example:

1.) MOV A, # 30H: Move data 30H immediately to accumulator.

2.) MOV B, # 50H: Move data 50H immediately to B register.

3.) MOV DPTR, #OABCDh: Move the immediate data bytes ABCDh to the DPTR.

4.) MOV P1, #00H: Move data 00H immediately to port 1.

Indexed Addressing Mode

• In the indexed addressing mode, only the program memory can be accessed. The program memory
can only be read.

• This addressing mode is preferred for reading look up tables in the program memory.

• Either the DPTR or PC can be used as Index register.

For Example:

MES: Unit 1 Bhoopesh Kumawat

 14

1.) MOVC A, @ A + DPTR: Copy the code byte, found at the ROM address formed by adding A and the
DPTR, to A.

2.) MOVC A, @ A + PC: Copy the code byte, found at the ROM address formed by adding A and the PC,
to A.

MES: Unit 1 Bhoopesh Kumawat

 15

Special Function Registers: Detailed Description

1. Program/Processor Status Word(PSW)

• Bit-Addressable.

• This register contains the carry bit, an auxiliary carry bit which is used with BCD operations, the
Accumulator parity flag and overflow flag, two general purpose flags, and two bits which select the
register bank to use as the default.

• The register bank selection bits make a two bit number from 0 to 3 which indicates the bank to be
used. Bank 0 begins at the base of the DATA segment (address 00H), bank 1 begins at address 08H,
bank 2 at address 10H and bank 3 at address 18H.

Program Status Word(PSW): Bit-Addressable

2. Power Control Register(PCON)

• Two power saving modes are there that can be activated by software: idle mode and power down
mode. These modes are accessed via the PCON (Power Control) SFR.

Power Control SFR

MES: Unit 1 Bhoopesh Kumawat

 16

• The idle mode is activated by setting the IDLE bit high. The idle mode causes all program execution
to stop. Internal RAM contents are preserved and the oscillator continues to run but is blocked from
the CPU. The timers and the UART continue to function as normal. Idle mode is terminated by the
activation of any interrupt. Upon completion of the interrupt service routine, execution will
continue from the instruction following the instruction which set the IDLE bit.

• The power down mode is activated by setting the PDWN bit high. In this mode, the on chip
oscillator is stopped. Thus, the timers and the UART as well as software execution are halted. As
long as a minimum of 2 volts are applied to the chip (assuming a five volt part) the contents of the
internal RAM will be preserved. The only way to force the processor out of power down mode is by
applying a power on reset.

• The SMOD (Serial Mode) bit can be used to double the baud rates of the serial port whether
generated by the timer 1 overflow rate or the oscillator frequency. Setting SMOD high causes a
doubling of the baud rate for the UART when operated in mode 1, 2, or 3. When Timer 2 is used to
generate baud rates, the value of SMOD will have no effect on the UART.

3. Serial Control Register(SCON)

• Bit Addressable.

• The SCON register is used to configure the full-duplex UART (Serial Port). It allows the user to select
the UART mode, enable reception, and check UART status.

Serial Control SFR

MES: Unit 1 Bhoopesh Kumawat

 17

8051 UART Modes

Note: The baud rate indicated in above table is doubled if PCON.7 (SMOD) is set.

4. Timer Control Register(TCON)

• The standard 8051 has two timer/counters, namely T0 and T1, each of which is of 16 bits.

• Each timer/counter can be function as a free running timer (in which case they count processor
cycles) or can be used to count falling edges on the signal applied to their respective I/O pin (either
T0 or T1).

• When used as a counter, the input signal must have a frequency equal to or lower than the
instruction cycle frequency divided by 2 (i.e. the oscillator frequency /24) since the incoming signal is
sampled every instruction cycle, and the counter is incremented only when a 1 to 0 transition is
detected (which will require two samples).

• The timer/counters can be used to force a software interrupt when they overflow.

Timer Control SFR

• The TCON (Timer Control) SFR is used to start or stop the timers as well as hold the overflow flags of
the timers.
MES: Unit 1 Bhoopesh Kumawat
 18

• The timer/counters are started or stopped by changing the timer run bits (TR0 and TR1) in TCON.
The software can freeze the operation of either timer as well as restart the timers simply by
changing the TRx bit in the TCON register.

• The TCON register also contains the overflow flags for the timers. When the timers overflow, they
set their respective flag (TF0 or TF1) in this register.

5. Timer Mode Register (TMOD)

• TMOD (timer mode) SFR is used to configure the function and mode of a timer or a counter. By
changing TMOD, the software can control the mode of both timers as well as the source they use to
count (the signal at their I/O pin or the processor cycles).

• The upper nibble of TMOD controls the operation of timer 1 and the low nibble controls the
operation of timer 0.

Timer Mode SFR

• The source for the timer can be configured by altering the C/T bit in TMOD. Setting this bit to true
will force the timer to count pulses on the I/O pin assigned to it. Setting this bit false will force
counting of processor cycles.

• When a timer is forced to count processor cycles it can do this either under hardware or software
control.

• Software control is commanded by setting the GATE bit of TMOD to 0. In this case, the timer will
count any time its TRx bit in the TCON register is high.

• In the hardware control mode, both the TRx bit and the INTx pin on the chip must be high for the
timer to count. When a low is detected at the INTx pin, the timer will stop. This is useful for
measuring pulse widths of signals on the INTx pin if one does not mind surrendering an external
interrupt source to the incoming signal.
MES: Unit 1 Bhoopesh Kumawat
 19

6. Interrupt Enable Register(IE)

• Bit Addressable.

• The basic 8051 supports six interrupt sources: two external interrupts, two timer/counter interrupts,
and a serial byte in/out interrupt.

• These interrupt sources force the processor to vector to one of five locations in the lowest part of
the CODE address space (serial input and serial output interrupts share the same vector).

Map of the interrupt vector

• Since there are only 8 bytes available to write the interrupt service routine at the vectored location,
therefore normally a JMP instruction is written at this vectored location.

• All interrupts are enabled or blocked by setting or clearing the EA bit (Enable All) of the IE (Interrupt
Enable) register.

• Each interrupt source can be individually enabled and disabled at any time by the software by
altering the value of the corresponding enable bit in the IE SFR.

MES: Unit 1 Bhoopesh Kumawat

 20

7. Interrupt Priority Register(IP)

• The 8015 supports two interrupt priority levels: low and high.

• A low level interrupt service routine can only be interrupted by a high level interrupt and a high level
interrupt service routine cannot be interrupted.

• Each interrupt source can be individually set to one of two priority levels by altering the value of the
IP (Interrupt Priority) SFR. If an interrupt source's corresponding bit in this register is set, it will have
high priority. Similarly, if the corresponding bit is cleared the interrupt will be of low priority.

• If the same priority level interrupts request simultaneously, then within each priority level there is a
polling structure due to the inherent priority, and the interrupt will be serviced according to the
polling sequence.

• The 8051 automatically evaluates whether an interrupt should occur after every instruction. When
checking for interrupt conditions, it checks them in the following order:

1) External 0 Interrupt

2) Timer 0 Interrupt

3) External 1 Interrupt

4) Timer 1 Interrupt

5) Serial Interrupt

MES: Unit 1 Bhoopesh Kumawat